US7166232B2 - Method for producing a solid body including a microstructure - Google Patents

Method for producing a solid body including a microstructure Download PDF

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US7166232B2
US7166232B2 US10/433,875 US43387503A US7166232B2 US 7166232 B2 US7166232 B2 US 7166232B2 US 43387503 A US43387503 A US 43387503A US 7166232 B2 US7166232 B2 US 7166232B2
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substrate
layer
masking layer
coating
substrate region
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US20040147119A1 (en
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Guenter Igel
Mirko Lehmann
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TDK Micronas GmbH
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TDK Micronas GmbH
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0293—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using formation of insulating sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/143—VDMOS having built-in components the built-in components being PN junction diodes
    • H10D84/144—VDMOS having built-in components the built-in components being PN junction diodes in antiparallel diode configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Definitions

  • the invention relates to a method for producing a solid body including a microstructure, especially, a semiconductor element, wherein the surface of a substrate is provided with a masking layer which is impermeable to a substance to be applied, and wherein the substance is subsequently incorporated into substrate regions not covered by the masking layer.
  • a process of this type is known from the book Integriere Digitalbausteine [Integrated Digital Components], Siemens AG (1970), pages 12 and 13.
  • a masking layer which consists of silicon dioxide and is impermeable to a dopant, while other surface regions remain exposed.
  • the substrate is first placed in a stream of oxygen where a continuous silicon dioxide layer is formed on the surface of the substrate.
  • a light-sensitive photoresist is then applied to the substrate surface. This photoresist is exposed through a photomask which transmits light at those sites at which the substrate is to remain exposed for doping.
  • the photoresist is removed with a solvent from the exposed sites, while the unexposed regions of the photoresist which are insoluble by the solvent remain on the substrate.
  • An etching agent is then used to etch away the silicon dioxide from the resist-free sites, after which the remaining photoresist is removed.
  • the substrate is then exposed at a temperature of approximately 1000° C. to a gas phase containing the dopant, during which the dopant diffuses into the open substrate sites not covered by the silicon dioxide. When the substrate cools, the diffusion process ceases.
  • the substrate has then been doped regionally at the intended sites.
  • the method may be used, for example, to integrate transistors, diodes, or electronic functional elements in the substrate.
  • the previously known method has the disadvantage, however, that the costs of the exposure device required to expose the substrate increase significantly as the size of the microstructures to be produced decrease—see F&M, Volume 107 (1994), Number 4, pages 57–60, and Number 9, pages 40–44.
  • a principal disadvantageous aspect is that the resolution of the exposure device must be dimensioned for the smallest structure to be produced on the substrate even when large structures are simultaneously generated on the substrate. The production of solid bodies with the smallest structures is therefore complex and expensive.
  • European Patent 0 412 263 A2 describes a method for producing a via hole in an integrated semiconductor circuit in which according to the method, a mask is used to dope a semiconductor body, and then oxidize the surface of the semiconductor body, thereby creating an oxidation layer which is thicker in the doped semiconductor regions than in the undoped semiconductor regions. An etching process is then used to remove the thinner section of the oxidation layer so as to be able to contact the semiconductor body.
  • IBM Technical Disclosure Bulletin, Volume 27, No. 11, April 1985, pages 6533–6536 discloses an analogous method for producing an insulation layer including regionally thinner sections on a semiconductor body, wherein the semiconductor body is doped through these thinner sections of the insulation layer.
  • Japanese Patent 02 077135 discloses a method in which a gate oxide layer is applied to a silicon substrate. Polysilicon is deposited and structured on this gate oxide layer, a base layer being produced as a mask using the structured polysilicon. A nitride layer is then deposited and structured, a source layer being produced as a mask using the nitride layer. A thick oxide layer is subsequently produced by selective oxidation and the nitride layer is removed, so that a highly doped layer is produced as a mask using the thick oxide layer. An intermediate layer is then deposited, thereby producing a via hole and an electrode.
  • U.S. Pat. No. 5,171,705 describes a method for producing a DMOS transistor in which a self-adjusting body connection contact is produced.
  • An applied substance is diffused into a substrate layer covered by the masking layer in such a way that a concentration gradient of the substance is created, proceeding from the edge of the masking layer inward with increasing distance from the edge, in the substrate region covered by the masking layer.
  • the masking layer is next removed to expose the substrate region below it.
  • a layer of the substrate near the surface in the exposed substrate region is converted by a chemical conversion reaction into a coating with a layer thickness profile corresponding to the concentration gradient of the substance contained in this near-surface layer; and wherein a supplementary treatment is implemented in a subsection of the coating, the surface of which is smaller than the substrate surface covered by the original masking layer and in which the thickness of the coating is reduced relative to the remaining subsections of the coating, in which treatment the substrate region covered by this subsection is exposed, and/or a material is incorporated into this substrate region through the coating.
  • the region of the substrate including the incorporated substance is thus enlarged, the substance being subdiffused underneath the edge of the masking layer.
  • a concentration gradient with a locus-dependent concentration of the substance is created in the substrate region covered by the masking layer, with the concentration decreasing in the substrate plane running along the interface of the masking layer and substrate, and proceeding from the edge of the masking layer inward with increasing distance from the edge.
  • the coating which was created, after removal of the masking layer, by the chemical conversion reaction of the substrate region originally covered by the masking layer has a thickness at different sites of the substrate layer which corresponds to the concentration of the substance at the respective site.
  • the layer thickness of the coating along the substrate plane may either decrease or increase, proceeding from the edge of the substrate layer originally covered by the masking layer toward the interior of this substrate layer.
  • Appropriate chemical conversion reactions are already well known.
  • the supplementary treatment dependent on the layer thickness may be advantageously implemented for the substrate in a given region which is smaller than the region originally covered by the masking layer.
  • the entire surface of the coating facing away from the substrate may be removed until a subsection of the substrate region originally covered by the coating is exposed at the sites in which the original thickness of the coating was smaller than at the remaining sites of the coating.
  • the supplementary treatment may also incorporate a chemical substance into a subsection of the substrate region covered by the coating through the coating, for example by diffusion or bombardment with particles.
  • the layer thickness profile of the coating is matched to the diffusion properties of the substance and/or to the kinetic energy of the particles in such a way that the substance is able to penetrate the coating only regionally at those sites where the layer thickness does not exceed a specified thickness.
  • a structure may be produced, the dimensions of which are smaller than the dimensions of the smallest substrate surface still to be masked off from the light or still to be exposed, due to the limited resolution of the exposure device used for the photolithographic process.
  • a cost-effective exposure device may be advantageously employed which has a lower resolution than that required for the dimensions of the smallest structure to be produced.
  • the method is especially well suited for producing solid bodies that have both small and large structures.
  • the substrate regions laterally adjoining the masking layer are covered with an etching mask and the masking layer is then contacted with an etching agent.
  • the etching mask is preferably created by a chemical reaction in which a near-surface layer of the substrate regions to be covered by the etching mask is converted into an etching mask material.
  • the etching mask may be applied to the surface regions not covered by the masking layer in a simple manner and without the use of a supplementary photolithographic step.
  • the near-surface layer may, for example, be converted in a nitrogen atmosphere to a nitride layer resistant to the specific etching agent.
  • the entire surface of the solid body may then be contacted with the etching agent to remove the masking layer.
  • the etching mask is of a greater thickness than the masking layer
  • another etching agent may be employed which removes the etching mask in addition to the masking layer from the solid body.
  • the etching rates and the thicknesses of the masking layer and etching mask must be matched to each other in such a way that, after the complete removal of the masking layer by the etching agent, the etching mask still possesses a residual thickness so as to continue to cover the substrate.
  • the etching mask is created during the heat treatment in an oxygen-containing atmosphere while the substrate material is undergoing oxidation. This allows an additional fabrication step to be eliminated in the production of the etching mask.
  • the chemical conversion reaction is an oxidation reaction.
  • the coating may then be generated easily in an oxygen-containing atmosphere and, if required, with the input of energy.
  • a clear shaping of the layer profile of the coating is obtained as a function of the concentration gradient of the dopant in the substrate material.
  • the near-surface layer of the substrate is converted by a chemical conversion reaction into an electrically insulating coating in the substrate region in which the masking layer has been removed.
  • a metal coating is electrolytically deposited on the exposed surface of the electrically conductive substrate region.
  • the electrodeposition of the metal coating may be implemented specifically by a currentless technique.
  • a preferably metallic surface layer to be applied to the surface of the solid body, and for the adhesive properties of the substrate material and of the coating to be matched to the material of the surface layer such that this layer continues to adhere only to the exposed subsection of the substrate region.
  • the material of the surface layer here is selected so as to adhere more effectively to the exposed subsection of the surface region than to adjacent surface regions of the coating. Any layer regions adhering to the adjacent surface regions after coating may then, for example, be mechanically etched from the surface of the solid body, while the region of the surface layer adhering to the exposed subsection of the substrate region continues to adhere to this region. If required, the surface layer may also be mechanically stressed by the incorporation of impurities. When the layer regions adhering to the coating are detached, cracks may form along the periphery of the surface of the exposed subsection of the substrate region, the cracks facilitating the removal of the regions of this surface layer adhering to the coating.
  • the near-surface layer of the substrate is converted by a chemical conversion reaction to a coating which is impermeable to the chemical substance to be applied.
  • a coating which is impermeable to the chemical substance to be applied.
  • the substrate region covered by a subsection of this coating is first exposed, then the substance is incorporated into this substrate region.
  • Incorporation of the substance which may in particular be a dopant for the semiconductor substrate, may, for example, be implemented by diffusion or bombardment with particles—with the substance penetrating the exposed substrate region, while in those regions of the substrate covered by the coating, any penetration of the substance into the substrate is prevented by the coating.
  • a heat treatment is used to diffuse the incorporated substance into a substrate region covered by the masking layer such that, proceeding from the edge of the masking layer inward with increasing distance from the edge of the masking layer, a concentration gradient of the substance is created in the substrate region covered by the masking layer.
  • the masking layer is subsequently removed to expose the substrate region below it.
  • a layer of the substrate near the surface in the exposed substrate region is converted by a chemical conversion reaction into a coating with an appropriate layer thickness profile corresponding to the concentration gradient of the substance contained in this near-surface layer.
  • a supplementary treatment is implemented in a subsection of the coating, the surface of which is smaller than the substrate surface covered by the original masking layer and in which the thickness of the coating is reduced relative to the remaining subsections of the coating, in which treatment the substrate region covered by this subsection is exposed, and/or a chemical substance is incorporated into this substrate region through the coating.
  • the medium, the material of the coating laterally adjacent to the exposed substrate region, and/or the reaction conditions are preferably selected such that no chemical reaction occurs between the medium and the material of the coating. The chemical reaction is then limited to the exposed subsection of the substrate region such that this section may be chemically modified in a targeted fashion.
  • the substrate region is contacted with an etching agent for the substrate material, to which the coating surrounding the substrate region is essentially chemically resistant, in order to insert a depression in the substrate region.
  • the coating then forms an etching mask for the etching agent.
  • An anisotropic etching agent may be used to insert a groove with a roughly V-shaped cross-section into the substrate region.
  • the solid body may be a component of a microreactor, the etched depression forming, for example, a supply channel for a substance to be inserted into the chamber of the microreactor, and/or forming a discharge channel for a substance to be discharged from the chamber.
  • a metallic material is preferably used as the substrate for one component of the microreactor, for example aluminum or silver, which material provides effective dissipation of heat from or into the chamber of the microreactor.
  • FIG. 1 is a cross-section through a solid body provided to produce a semiconductor element, into the substrate of which doping regions are incorporated laterally on both sides of the masking layer;
  • FIG. 2 shows the solid body seen in FIG. 1 after a heat treatment in which the doping material is diffused underneath the masking layer;
  • FIG. 3 shows the solid body seen in FIG. 2 after removal of the masking layer and subsequent application of a coating including a thickness profile
  • FIG. 4 shows the solid body seen in FIG. 3 after the etching process in which the coating has been removed regionally from the substrate;
  • FIG. 5 shows the solid body seen in FIG. 4 after the selective application of a metal coating
  • FIG. 6 is a cross-section through a DMOS transistor cell.
  • a substrate 3 that includes preferably silicon is provided, which substrate has passivation layers 4 that include silicon dioxide on its surface, the layers covering the substrate 3 continuously.
  • passivation layers 4 that include silicon dioxide on its surface, the layers covering the substrate 3 continuously.
  • an opening 5 is incorporated into the passivation layer 4 , the opening exposing a subsection of the substrate 3 .
  • a silicon nitride layer is applied through the opening 5 by a coating method such as chemical vapor deposition, over the entire substrate region exposed in the opening 5 .
  • an etching mask resistant to an etching agent such as phosphoric acid is applied to this layer by a photolithographic procedure, which mask covers certain regions of the silicon nitride layer.
  • the solid body 1 is then contacted with the etching agent to remove those regions of the silicon dioxide layer not covered by the etching mask.
  • the etching mask is then removed. It is evident in FIG. 2 that the regions of the silicon nitride layer remaining on the substrate 3 form the masking layer 6 which covers a subsection of the substrate region located in the opening 5 , and that this masking layer 6 is spaced laterally on both sides of the passivation layer 4 .
  • the material of the masking layer 6 is selected based on its impermeability to a substance provided for doping the substrate, for example boron or phosphorus.
  • this substance is inserted into the opening 5 to dope the substrate regions not covered by the masking layer 6 .
  • This may be accomplished for example by exposing the solid body 1 to a gas stream containing the substance. The substance then diffuses into the substrate regions not covered by the masking layer 6 where it forms doping zones 7 ( FIG. 1 ).
  • a heat treatment is implemented in which the incorporated substance is diffused into a substrate region covered by the masking layer 6 .
  • the heat treatment may be performed at a temperature of, for example, 1000° C. It is clearly evident in FIG. 2 that the doping regions 7 have expanded relative to FIG. 1 and that the dopant has sub-diffused underneath the edge of the masking layer 6 .
  • there is a decrease in the concentration of the substance in the coverage plane of the doping regions 7 proceeding from the masking layer 6 into the substrate region covered by the masking layer 6 and with increasing distance from the edge of the masking layer.
  • the solid body 1 is exposed to an oxygen-containing atmosphere in which an oxide layer is deposited in the opening onto the substrate region not covered by the masking layer 6 , the oxide layer forming an etching mask 8 which is resistant to an etching agent, such as phosphoric acid, used to remove the masking layer 6 .
  • the masking layer 6 is contacted with this etching agent to remove the masking layer 6 , thus exposing the substrate region located under the masking layer 6 .
  • a layer of substrate 3 located under the exposed substrate region is converted by a chemical conversion reaction in an oxygen-containing atmosphere into a silicon dioxide coating 9 .
  • the local thickness of this coating 9 is dependent on the concentration of the substance diffused into the specific substrate region taking part in the chemical conversion reaction. It is clearly evident in FIG. 3 , that the thickness of the coating 9 decreases proceeding from the edge of the coating 9 toward the center of the coating 9 , specifically, in accordance with the respective decrease in concentration of the substance in the substrate 3 .
  • the coating 9 is exposed to an etching agent which etches away the material from the surface of the coating 9 facing away from the substrate 3 .
  • the etching process is stopped when a subsection of the coating 9 , in which the original thickness of the coating 9 relative to the adjacent subsections of the original coating 9 is reduced, is completely removed, and the substrate 3 covered by this subsection is exposed. It is evident from FIG. 4 that after completion of the etching process, the substrate region covered by the original masking layer 6 remains covered by the coating 9 only along its peripheral regions, and that a substrate region which is smaller than the substrate region covered by the original masking layer 6 has been exposed.
  • the thickness of the passivation layer 4 and that of the etching mask 8 are adjusted to be large enough so only part of their thickness is etched away, and, as a result, the substrate material located beneath them continues to remain covered after completion of the etching process.
  • the coating 9 includes an electrically insulating material.
  • a metal layer 10 is electrolytically deposited on the exposed surface of the substrate 3 , which layer may form, for example, an electrode or a conductive track. It is clearly evident from FIG. 5 that the dimensions “b” of the metal layer 10 are smaller than the dimensions “a” of the original masking layer 6 .
  • the method may thus be employed to produce a microstructure 2 , the dimensions of which are smaller than the resolution of an exposure device used during the photolithograph processing applied to the masking layer 6 . As a result, the additional costs otherwise required for a high-resolution exposure device may be eliminated.
  • a substance may be incorporated into the substrate region exposed by the regional removal of the coating 9 .
  • the material of the coating 9 is selected based on the fact that the residual amount of the coating 9 remaining on the substrate 3 after exposure of the substrate region is impermeable, at least regionally, to the substance to be incorporated.
  • the solid body is contacted with a substance, for example in a gas phase, that essentially diffuses only into the exposed substrate regions while the remaining substrate regions remain free of the substance.
  • FIG. 6 shows a DMOS transistor device produced according to the method, in which device the substance is a dopant which is incorporated into a p + zone 15 for a freewheeling diode.
  • the doping regions 7 located on both sides of the p + zone 15 are n + source regions which are embedded in a p-doped substrate region 11 .
  • This p-doped substrate region 11 is in turn embedded in an n-doped substrate region 12 .
  • Also visible in FIG. 6 are gate contacts 13 , a passivation layer 4 , a source contact 14 , and a gate oxide layer 16 .
  • the surface of the substrate 3 is thus provided with the masking layer 6 which is impermeable to the substance to be applied.
  • the substance is then incorporated into substrate regions not covered by the masking layer 6 .
  • a heat treatment is used to diffuse the substance into a specific substrate region covered by the masking layer 6 such that a concentration gradient of the substance is created, proceeding from the edge of the masking layer inward with increasing distance from the edge.
  • the masking layer 6 is subsequently removed to expose the substrate region below it, and a near-surface layer of the substrate 3 located in the exposed substrate region is converted by a chemical conversion reaction into the coating 9 which has a layer thickness profile corresponding to the concentration gradient of the substance contained in the near-surface layer.
  • a supplementary treatment is implemented in a subsection of the coating 9 in which the thickness of the coating 9 has been reduced.

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PCT/EP2000/013066 WO2002050878A1 (de) 2000-12-21 2000-12-21 Verfahren zum herstellen eines eine mikrostruktur aufweisenden festkörpers

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US20090131886A1 (en) * 2007-11-16 2009-05-21 Liu Y King Steerable vertebroplasty system
US20090131950A1 (en) * 2007-11-16 2009-05-21 Liu Y King Vertebroplasty method with enhanced control
US20090182427A1 (en) * 2007-12-06 2009-07-16 Osseon Therapeutics, Inc. Vertebroplasty implant with enhanced interfacial shear strength
US20090299282A1 (en) * 2007-11-16 2009-12-03 Osseon Therapeutics, Inc. Steerable vertebroplasty system with a plurality of cavity creation elements

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US20040147119A1 (en) 2004-07-29
WO2002050878A1 (de) 2002-06-27

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