US6838356B2 - Method of forming a trench isolation - Google Patents

Method of forming a trench isolation Download PDF

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US6838356B2
US6838356B2 US09/956,142 US95614201A US6838356B2 US 6838356 B2 US6838356 B2 US 6838356B2 US 95614201 A US95614201 A US 95614201A US 6838356 B2 US6838356 B2 US 6838356B2
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insulating layer
electrically insulating
film
teos
over
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US20020034858A1 (en
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Kenya Kobayashi
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Renesas Electronics Corp
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NEC Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates to a method of forming a semiconductor integrated circuit, and more particularly to a trench isolation in a semiconductor integrated circuit.
  • Isolations for electrically isolating semiconductor devices are important for the semiconductor integrated circuit with a high withstand voltage. It was known that one or more trench isolations are formed in a silicon-on-insulator substrate. In the semiconductor integrated circuit with the high withstand voltage, a depth of the semiconductor devices may reach a few micrometers, for which reason it is necessary that the trench depth is ranged from a few micrometers to 10 micrometers.
  • FIGS. 1A through 1D are fragmentary cross sectional elevation views illustrative of trench isolations in silicon-on-insulator substrates in sequential steps involved in a first conventional method.
  • a silicon-on-insulator substrate 20 is prepared, wherein the silicon-on-insulator substrate 20 comprises first and second silicon substrates 11 and 12 and a buried insulating layer 13 sandwiched between the first and second silicon substrates 11 and 12 .
  • a surface of the first silicon substrate 11 is subjected to a thermal oxidation to form an oxide film 14 .
  • a photo-resist film is applied on the oxide film 14 .
  • the photo-resist film is patterned by a photo-lithography technique to form a photo-resist mask on the oxide film 14 .
  • the photo-resist mask is used as an etching mask for carrying out an anisotropic etching for selectively etching the oxide film 14 , so that a part of the surface of the first silicon substrate 11 is exposed.
  • a reactive ion etching process is then carried out for selectively etching the first silicon substrate 11 to form a trench groove 15 in the first silicon substrate 11 , wherein the trench groove 15 reaches the buried insulating layer 13 .
  • a chemical vapor deposition process is carried out using a TEOS gas to deposit a TEOS-SiO 2 film 16 both within the trench groove 15 and over the oxide film 14 , whereby the trench groove 15 is completely filled with the TEOS-SiO 2 film 16 .
  • the TEOS-SiO 2 film 16 is then subjected to an etch-back so that the thickness of the TEOS-SiO 2 film 16 over the oxide film 14 becomes a predetermined thickness “d”.
  • the etch-back may be made until the surface of the oxide film 14 is exposed and the TEOS-SiO 2 film 16 remains only within the trench groove 15 .
  • the etch-back may be made until the surface of the first silicon substrate 11 is exposed and the TEOS-SiO 2 film 16 remains only within the trench groove 15 .
  • the TEOS-SiO 2 film 16 is deposited by the chemical vapor deposition process using the TEOS gas.
  • This TEOS-SiO 2 film 16 has a large surface migration and a good surface coverage.
  • the TEOS-SiO 2 film 16 is deposited with substantially keeping a thickness uniformity on side walls and a bottom of the trench groove 15 and over the oxide film 14 .
  • the thickness of the TEOS-SiO 2 film 16 is increased with keeping the thickness uniformity on side walls and a bottom of the trench groove 15 and over the oxide film 14 .
  • an upper surface of the TEOS-SiO 2 film 16 as deposited has a generally V-shaped hollow portion which is positioned over the trench groove 15 .
  • the generally V-shaped hollow portion remains after the etch back process. Therefore, it is difficult to obtain a planarized top surface of the TEOS-SiO 2 film 16 .
  • a metal interconnection layer is once entirely formed over the entire surface of the TEOS-SiO 2 film 16 , and then the metal interconnection layer is patterned or selectively removed to form an interconnection extending over the TEOS-SiO 2 film 16 . It is possible that the metal interconnection layer resides within the TEOS-SiO 2 film 16 . This residual metal in the generally V-shaped hollow portion may cause a short circuit between interconnections. If a tapered angle of the generally V-shaped hollow portion is larger than 20 degrees, it is highly possible that the metal interconnection layer resides within the TEOS-SiO 2 film 16 .
  • FIGS. 2A through 2D are fragmentary cross sectional elevation views illustrative of trench isolations in silicon-on-insulator substrates in sequential steps involved in a second conventional method.
  • a silicon-on-insulator substrate 20 is prepared, wherein the silicon-on-insulator substrate 20 comprises first and second silicon substrates 11 and 12 and a buried insulating layer 13 sandwiched between the first and second silicon substrates 11 and 12 .
  • a surface of the first silicon substrate 11 is subjected to a thermal oxidation to form an oxide film 14 .
  • a photo-resist film is applied on the oxide film 14 .
  • the photo-resist film is patterned by a photo-lithography technique to form a photo-resist mask on the oxide film 14 .
  • the photo-resist mask is used as an etching mask for carrying out an anisotropic etching for selectively etching the oxide film 14 , so that a part of the surface of the first silicon substrate 11 is exposed.
  • a reactive ion etching process is then carried out for selectively etching the first silicon substrate 11 to form a trench groove 15 in the first silicon substrate 11 , wherein the trench groove 15 reaches the buried insulating layer 13 .
  • a chemical vapor deposition process is carried out using a TEOS gas to deposit a TEOS-BPSG film 17 both within the trench groove 15 and over the oxide film 14 , whereby the trench groove 15 is completely filled with the TEOS-BPSG film 17 .
  • the TEOS-BPSG film 17 is deposited by the chemical vapor deposition process using the TEOS gas.
  • An upper surface of the TEOS-BPSG film 17 as deposited has a generally V-shaped hollow portion which is positioned over the trench groove 15 . Further, it is possible that a void 19 is formed in the TEOS-BPSG film 17 in the trench groove 15 .
  • a heat treatment is carried out at about 900° C. to cause a re-flow of the TEOS-BPSG film 17 for the purpose of planarizing the generally V-shaped hollow portion on the surface of the TEOS-BPSG film 17 .
  • the re-flow of the TEOS-BPSG film 17 also causes a size reduction of the void 19 , even the void 19 does not disappear.
  • the TEOS-BPSG film 17 is then subjected to an etch-back so that the thickness of the TEOS-BPSG film 17 over the oxide film 14 becomes a predetermined thickness “Z”.
  • the etch-back may be made until the surface of the oxide film 14 is exposed and the TEOS-BPSG film 17 remains only within the trench groove 15 .
  • the etch-back may be made until the surface of the first silicon substrate 11 is exposed and the TEOS-BPSG film 17 remains only within the trench groove 15 .
  • the TEOS-BPSG film 17 is deposited by the chemical vapor deposition process using the TEOS gas.
  • This TEOS-BPSG film 17 has a small surface migration and a low surface coverage.
  • the TEOS-BPSG film 17 is deposited without keeping a thickness uniformity on side walls and a bottom of the trench groove 15 and over the oxide film 14 .
  • the thickness of the TEOS-BPSG film 17 adjacent to an opening edge of the trench groove 15 is larger than the other portions thereof. This may cause the void 19 in the TEOS-BPSG film 17 in the trench groove 15 .
  • the void 19 deteriorates the trench isolation. Further, a residual gas in the void 19 may be expanded in the later heat treatment, whereby it is possible that the trench isolation is broken.
  • the present invention provides a method of forming a trench isolation in a substrate, which comprises the steps of: forming a trench groove in a substrate; forming a first electrically insulating layer which fills the trench groove and extends over an upper surface of the substrate, wherein the first electrically insulating layer has a first surface migration, and an upper surface of the first electrically insulating layer has a first hollow positioned over the trench groove; and forming a second electrically insulating layer over the first electrically insulating layer, wherein the second electrically insulating layer fills the first hollow, and an upper surface of the second electrically insulating layer has a second hollow positioned over the trench groove, and the second electrically insulating layer has a second surface migration smaller than the first surface migration.
  • FIGS. 1A through 1D are fragmentary cross sectional elevation views illustrative of trench isolations in silicon-on-insulator substrates in sequential steps involved in a first conventional method.
  • FIGS. 2A through 2E are fragmentary cross sectional elevation views illustrative of trench isolations in silicon-on-insulator substrates in sequential steps involved in a second conventional method.
  • FIGS. 3A through 3H are fragmentary cross sectional elevation views illustrative of trench isolations in silicon-on-insulator substrates in sequential steps involved in a first novel method in a first embodiment in accordance with the present invention.
  • FIGS. 4A through 4H are fragmentary cross sectional elevation views illustrative of trench isolations in silicon-on-insulator substrates in sequential steps involved in a second novel method in a second embodiment in accordance with the present invention.
  • a first aspect of the present invention is a method of forming a trench isolation in a substrate.
  • the method comprises the steps of: forming a trench groove in a substrate; forming a first electrically insulating layer which fills the trench groove and extends over an upper surface of the substrate, wherein the first electrically insulating layer has a first surface migration, and an upper surface of the first electrically insulating layer has a first hollow positioned over the trench groove; and forming a second electrically insulating layer over the first electrically insulating layer, wherein the second electrically insulating layer fills the first hollow, and an upper surface of the second electrically insulating layer has a second hollow positioned over the trench groove, and the second electrically insulating layer has a second surface migration smaller than the first surface migration.
  • a taper angle of the second hollow after the etch back is not more than 20 degrees.
  • a thickness of the first electrically insulating layer over the upper surface of the substrate is almost equal to a distance between the first hollow and an opening edge of the trench groove.
  • a thickness of the first electrically insulating layer over the upper surface of the substrate is larger than a half of an opening diameter of the trench groove.
  • the first electrically insulating layer comprises a non-doped silicate glass film.
  • the non-doped silicate glass film is formed by a low pressure chemical vapor deposition using a tetra ethyl ortho silicate gas.
  • the second electrically insulating layer comprises a boro-phospho silicate glass film.
  • the boro-phospho silicate glass film is formed by a low pressure chemical vapor deposition using a tetra ethyl ortho silicate gas.
  • the boro-phospho silicate glass film is formed by a normal pressure chemical vapor deposition using a tetra ethyl ortho silicate gas.
  • the boro-phospho silicate glass film is formed by a normal pressure chemical vapor deposition using silane (SiH 4 ), phosphine (PH 3 ), diborane (B 2 H 6 ), and oxygen (O 2 ).
  • the first electrically insulating layer has a first re-flowablity
  • the second electrically insulating layer has a second re-flowablity larger than the first re-flowablity
  • the first electrically insulating layer has a first surface coverage
  • the second electrically insulating layer has a second surface coverage smaller than the first surface coverage
  • a second aspect of the present invention is a method of forming a trench isolation in a substrate. The method comprises the steps of:
  • a taper angle of the second hollow after the etch back is not more than 20 degrees.
  • a thickness of the first electrically insulating layer over the upper surface of the substrate is almost equal to a distance between the first hollow and an opening edge of the trench groove.
  • a thickness of the first electrically insulating layer over the upper surface of the substrate is larger than a half of an opening diameter of the trench groove.
  • the first electrically insulating layer comprises a non-doped silicate glass film.
  • the non-doped silicate glass film is formed by a low pressure chemical vapor deposition using a tetra ethyl ortho silicate gas.
  • the second electrically insulating layer comprises a boro-phospho silicate glass film.
  • the boro-phospho silicate glass film is formed by a low pressure chemical vapor deposition using a tetra ethyl ortho silicate gas.
  • the boro-phospho silicate glass film is formed by a normal pressure chemical vapor deposition using a tetra ethyl ortho silicate gas.
  • the boro-phospho silicate glass film is formed by a normal pressure chemical vapor deposition using silane (SiH 4 ), phosphine (PH 3 ), diborane (B 2 H 6 ), and oxygen (O 2 ).
  • the first electrically insulating layer has a first re-flowablity
  • the second electrically insulating layer has a second re-flowablity larger than the first re-flowablity
  • the first electrically insulating layer has a first surface migration
  • the second electrically insulating layer has a second surface migration smaller than the first surface migration
  • FIGS. 3A through 3H are fragmentary cross sectional elevation views illustrative of trench isolations in silicon-on-insulator substrates in sequential steps involved in a first novel method in a first embodiment in accordance with the present invention.
  • a silicon-on-insulator substrate 10 is prepared, wherein the silicon-on-insulator substrate 10 comprises first and second silicon substrates 1 and 2 and a buried insulating layer 3 sandwiched between the first and second silicon substrates 1 and 2 .
  • the silicon-on-insulator substrate 10 may be formed as follows.
  • a surface of the first silicon substrate 1 is subjected to a thermal oxidation to form a buried insulating layer 3 on the surface of the first silicon substrate 1 .
  • the second silicon substrate 2 is combined with the buried insulating layer 3 on the first silicon substrate 1 .
  • a surface of the first silicon substrate 1 is then polished to form a planarized main face of the silicon-on-insulator substrate 10 .
  • a thickness, a conductivity type and a resistivity of the first silicon substrate 1 may be decided depending on semiconductor devices with high withstand voltages, for examples, MOS transistors and bipolar transistors.
  • the thickness may be 5 micrometers
  • the conductivity type may be p-type
  • the resistivity may be ranged from 10-20 ohms cm.
  • the second silicon substrate 2 serves as a supporting substrate.
  • the thickness of the second silicon substrate 2 is preferably thicker than the first silicon substrate 1 .
  • the thickness of the second silicon substrate 2 may be ranged from 600-700 micrometers.
  • a conductivity type and a resistivity of the second silicon substrate 2 may be decided independent from semiconductor devices with high withstand voltages, for examples, MOS transistors and bipolar transistors.
  • the conductivity type may be p-type, and the resistivity may be ranged from 1-50 ohms cm.
  • the buried insulating layer 3 is provided not only for allowing isolation but also for allowing high withstand voltage.
  • the increase in thickness of the buried insulating layer 3 increases the withstand voltage for high voltage semiconductor devices.
  • the buried insulating layer 3 may generally comprise an SiO 2 layer formed by a thermal oxidation.
  • a preferable thickness of the buried insulating layer 3 may be about 1 micrometer.
  • a preferable thickness of the buried insulating layer 3 may be about 2 micrometers.
  • an oxide film 4 is formed on the planarized surface of the first silicon substrate 1 by either a thermal oxidation or a chemical vapor deposition.
  • a thickness of the oxide film 4 may be about 5 micrometers.
  • a photo-resist film is applied on the oxide film 4 .
  • the photo-resist film is patterned by a photo-lithography technique to form a photo-resist mask on the oxide film 4 .
  • the photo-resist mask is used as an etching mask for carrying out an anisotropic etching for selectively etching the oxide film 4 at a predetermined pattern width “W”, so that a part of the surface of the first silicon substrate 1 is exposed.
  • a reactive ion etching process is then carried out using the oxide film 4 as a mask for selectively etching the first silicon substrate 1 to form a trench groove 5 in the first silicon substrate 1 , wherein the trench groove 5 reaches the buried insulating layer 3 .
  • An incline gradient of the trench groove 5 may vary depending on combinations of used etching gases and flow rates. A generally available incline gradient of the trench groove 5 may be ranged from about 80 degrees to about 90 degrees.
  • the trench groove 5 has an opening width “W” defined by the opening width “W” of the oxide film 4 . A bottom width of the trench groove 5 depends on the incline gradient.
  • a preferable opening width “W” of the oxide film 4 may be ranged from about 1 micrometer to about 2 micrometers.
  • a low pressure chemical vapor deposition process is carried out using a TEOS (Tetra Etyl Ortho Silicate) gas to deposit a TEOS-NSG (Non-doped Silicate Glass) film 6 both within the trench groove 5 and over the oxide film 4 , whereby the trench groove 5 is completely filled with the TEOS-NSG film 6 .
  • TEOS Tetra Etyl Ortho Silicate
  • NSG Non-doped Silicate Glass
  • the low pressure chemical vapor deposition process is suitable for a low deposition rate of not more than 30 nm/min for completely filling the TEOS-NSG film 6 within the trench groove 5 having a width of 1-2 micrometers and a depth of 5 micrometers.
  • This TEOS-NSG film 6 has a large surface migration and a good surface coverage.
  • the TEOS-NSG film 6 is deposited with substantially keeping a thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 .
  • the thickness of the TEOS-NSG film 6 is increased with keeping the thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 .
  • an upper surface of the TEOS-NSG film 6 as deposited has a generally V-shaped hollow portion which is positioned over the trench groove 5 .
  • a thickness “X 1 ” of the TEOS-NSG film 6 over the oxide film 4 is almost equal to a distance “X 2 ” between the opening edge of the oxide film 4 to the generally V-shaped hollow portion because of the large surface migration of the TEOS-NSG film 6 and the slow deposition by the low pressure chemical vapor deposition. It is preferable that the thickness “X 1 ” of the TEOS-NSG film 6 over the oxide film 4 is not less than a half of the opening width “W” of the oxide film 4 .
  • a heat treatment is then carried out at 900° C. for 10 minutes in a nitrogen atmosphere for stabilizing the film quality of the TEOS-NSG film 6 .
  • another low pressure chemical vapor deposition process is carried out using a TEOS (Tetra Etyl Ortho Silicate) gas to deposit a TEOS-BPSG (boro-phospho-silicate glass) film 7 over the TEOS-NSG film 6 for completely filling the generally V-shaped hollow portion of the TEOS-NSG film 6 with the TEOS-BPSG film 7 .
  • TEOS-BPSG boro-phospho-silicate glass
  • a normal pressure chemical vapor deposition process with a higher deposition rate than the low pressure chemical vapor deposition process may be available by use of the TEOS gas, provided that the generally V-shaped hollow portion of the TEOS-NSG film 6 is completely filled with the TEOS-BPSG film 7 .
  • the TEOS gas trimethylphosphate (P(OCH 3 ) 3 ), triethylborate (B(OC 2 H 5 ) 3 ), and either oxygen (O 2 ) or ozone (O 3 ) are used as additives.
  • Another generally V-shaped hollow portion is formed on the surface of the TEOS-BPSG film 7 .
  • a normal pressure chemical vapor deposition process with a higher deposition rate than the low pressure chemical vapor deposition process may also be available without using the TEOS gas to deposit a BPSG film 7 , provided that the generally V-shaped hollow portion of the TEOS-NSG film 6 is completely filled with the BPSG film 7 .
  • the TEOS gas silane (SiH 4 ), phosphine (PH 3 ), diborane (B 2 H 6 ), and oxygen (O 2 ) are used.
  • Another generally V-shaped hollow portion is formed on the surface of the BPSG film 7 .
  • a heat treatment is carried out at about 800-900° C. for about 10 minutes in a nitrogen atmosphere to cause a surface re-flow of the BPSG film 7 whereby the generally V-shaped hollow portion on the surface of the BPSG film 7 is reduced in size. Namely, a slight and smooth hollow resides on the surface of the BPSG film 7 .
  • the BPSG film 7 and the TEOS-NSG film 6 are then subjected to an etch-back so that the thickness of the TEOS-NSG film 6 over the oxide film 4 becomes a predetermined value “Z”, wherein the BPSG film 7 remains only within the generally V-shaped hollow portion of the TEOS-NSG film 6 .
  • the etch-back may be made until the surface of the oxide film 4 is exposed and the TEOS-NSG film 6 remains only within the trench groove 5 .
  • the etch-back may be made until the surface of the first silicon substrate 1 is exposed and the TEOS-NSG film 6 remains only within the trench groove 5 .
  • the trench groove 5 is completely filled with the NSG film 6 .
  • This NSG film 6 has a large surface migration and a good surface coverage, for which reason no void is formed in the NSG film 6 .
  • the NSG film 6 is deposited with substantially keeping a thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 .
  • the thickness of the NSG film 6 is increased with keeping the thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 .
  • an upper surface of the NSG film 6 as deposited has a generally V-shaped hollow portion which is positioned over the trench groove 5 . As shown in FIG.
  • the generally V-shaped hollow portion of the NSG film 6 is completely filled with the BPSG film 7 .
  • the BPSG film 7 shows a surface re-flow upon receipt of a heat, for which reason the surface re-flow of the BPSG film 7 is caused by the post heat treatment.
  • the reduction in size of the generally V-shaped hollow is also caused to have a small taper angle of not more than 20 degrees, and an imperfect planarization to the surface of the BPSG film 7 can be obtained. Namely, a slight or small hollow remains on the surface of the BPSG film 7 .
  • the desirable generally planarized surface can be obtained, wherein the generally planarized surface comprises the surface of the NSG film 6 having the generally V-shaped hollow and the BPSG film 7 remaining in the generally V-shaped hollow.
  • the etch-back is made to the oxide film 4 , then almost the same generally planarized surface can be obtained because the BPSG film 7 has the generally planarized surface after the heat treatment and before the etch-back. If no step is present on the top surface, the etch-back to thee oxide layer causes almost uniform etching rate over the entirety of the etched-surface.
  • the generally planarized surface after etch-back process provides the following advantages.
  • a metal interconnection layer is once entirely formed over the generally planarized surface, and then the metal interconnection layer is patterned or selectively removed to form an interconnection extending over the generally planarized surface. It is possible to avoid that the metal interconnection layer resides over the generally planarized surface. No metal over the generally planarized surface causes no short circuit between interconnections.
  • the NSG film 6 fills the trench groove 5 . Since the NSG film 6 has a large surface migration and a high surface coverage, in the chemical vapor deposition process, the NSG film 6 is deposited with keeping a thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 . Namely, in the chemical vapor deposition process, the thickness of the NSG film 6 adjacent to an opening edge of the trench groove 5 is substantially equal to the other portions thereof. This may cause no void in the NSG film 6 in the trench groove 5 . No void causes no deterioration of the trench isolation.
  • the NSG film 6 having the large surface migration and the high surface coverage is suitable for avoiding the void formation even allowing the generally V-shaped hollow on its surface.
  • the BPSG film 7 showing the surface re-flow upon heat treatment is deposited over the NSG film 6 for obtaining the generally planarized surface, whereby the etch-backed surface is the generally planarized surface which is suitable for forming integrated circuits.
  • FIGS. 4A through 4H are fragmentary cross sectional elevation views illustrative of trench isolations in silicon-on-insulator substrates in sequential steps involved in a second novel method in a second embodiment in accordance with the present invention.
  • a silicon-on-insulator substrate 10 is prepared, wherein the silicon-on-insulator substrate 10 comprises first and second silicon substrates 1 and 2 and a buried insulating layer 3 sandwiched between the first and second silicon substrates 1 and 2 .
  • the silicon-on-insulator substrate 10 may be formed as follows.
  • a surface of the first silicon substrate 1 is subjected to a thermal oxidation to form a buried insulating layer 3 on the surface of the first silicon substrate 1 .
  • the second silicon substrate 2 is combined with the buried insulating layer 3 on the first silicon substrate 1 .
  • a surface of the first silicon substrate 1 is then polished to form a planarized main face of the silicon-on-insulator substrate 10 .
  • a thickness, a conductivity type and a resistivity of the first silicon substrate 1 may be decided depending on semiconductor devices with high withstand voltages, for examples, MOS transistors and bipolar transistors.
  • the thickness may be 5 micrometers
  • the conductivity type may be p-type
  • the resistivity may be ranged from 10-20 ohms cm.
  • the second silicon substrate 2 serves as a supporting substrate.
  • the thickness of the second silicon substrate 2 is preferably thicker than the first silicon substrate 1 .
  • the thickness of the second silicon substrate 2 may be ranged from 600-700 micrometers.
  • a conductivity type and a resistivity of the second silicon substrate 2 may be decided independent from semiconductor devices with high withstand voltages, for examples, MOS transistors and bipolar transistors.
  • the conductivity type may be p-type, and the resistivity may be ranged from 1-50 ohms cm.
  • the buried insulating layer 3 is provided not only for allowing isolation but also for allowing high withstand voltage.
  • the increase in thickness of the buried insulating layer 3 increases the withstand voltage for high voltage semiconductor devices.
  • the buried insulating layer 3 may generally comprise an SiO 2 layer formed by a thermal oxidation.
  • a preferable thickness of the buried insulating layer 3 may be about 1 micrometer.
  • a preferable thickness of the buried insulating layer 3 may be about 2 micrometers.
  • an oxide film 4 is formed on the planarized surface of the first silicon substrate 1 by either a thermal oxidation or a chemical vapor deposition.
  • a thickness of the oxide film 4 may be about 5 micrometers.
  • a photo-resist film is applied on the oxide film 4 .
  • the photo-resist film is patterned by a photo-lithography technique to form a photo-resist mask on the oxide film 4 .
  • the photo-resist mask is used as an etching mask for carrying out an anisotropic etching for selectively etching the oxide film 4 at a predetermined pattern width “W”, so that a part of the surface of the first silicon substrate 1 is exposed.
  • a reactive ion etching process is then carried out using the oxide film 4 as a mask for selectively etching the first silicon substrate 1 to form a trench groove 5 in the first silicon substrate 1 , wherein the trench groove 5 reaches the buried insulating layer 3 .
  • An incline gradient of the trench groove 5 may vary depending on combinations of used etching gases and flow rates. A generally available incline gradient of the trench groove 5 may be ranged from about 80 degrees to about 90 degrees.
  • the trench groove 5 has an opening width “W” defined by the opening width “W” of the oxide film 4 . A bottom width of the trench groove 5 depends on the incline gradient.
  • a preferable opening width “W” of the oxide film 4 may be ranged from about 1 micrometer to about 2 micrometers.
  • a low pressure chemical vapor deposition process is carried out using a TEOS (Tetra Etyl Ortho Silicate) gas to deposit a TEOS-NSG (Non-doped Silicate Glass) film 6 both within the trench groove 5 and over the oxide film 4 , whereby the trench groove 5 is completely filled with the TEOS-NSG film 6 .
  • TEOS Tetra Etyl Ortho Silicate
  • NSG Non-doped Silicate Glass
  • the low pressure chemical vapor deposition process is suitable for a low deposition rate of not more than 30 nm/min for completely filling the TEOS-NSG film 6 within the trench groove 5 having a width of 1-2 micrometers and a depth of 5 micrometers.
  • This TEOS-NSG film 6 has a large surface migration and a good surface coverage.
  • the TEOS-NSG film 6 is deposited with substantially keeping a thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 .
  • the thickness of the TEOS-NSG film 6 is increased with keeping the thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 .
  • an upper surface of the TEOS-NSG film 6 as deposited has a generally V-shaped hollow portion which is positioned over the trench groove 5 .
  • a heat treatment is then carried out at 900° C. for 10 minutes in a nitrogen atmosphere for stabilizing the film quality of the TEOS-NSG film 6 .
  • a thickness “X 3 ” of the TEOS-NSG film 6 over the oxide film 4 is sufficiently larger than a predetermined thickness value “Z”.
  • the TEOS-NSG film 6 is subjected to an etch-back to reduce the above thickness “X 3 ” to a thickness “X 4 ” which is smaller than the predetermined thickness value “Z”.
  • This etch-back process reduces the size of the generally V-shaped hollow portion.
  • another low pressure chemical vapor deposition process is carried out using a TEOS (Tetra Etyl Ortho Silicate) gas to deposit a TEOS-BPSG (boro-phospho-silicate glass) film 7 over the TEOS-NSG film 6 for completely filling the size-reduced generally V-shaped hollow portion of the TEOS-NSG film 6 with the TEOS-BPSG film 7 .
  • TEOS-BPSG boro-phospho-silicate glass
  • Another small size generally V-shaped hollow portion is formed on the surface of the TEOS-BPSG film 7 . Since the size of the generally V-shaped hollow portion of the TEOS-NSG film 6 is reduced, the generally V-shaped hollow portion of the TEOS-BPSG film 7 has a small size.
  • a total thickness of the TEOS-BPSG film 7 and the TEOS-NSG film 6 over the oxide film 4 is larger than the predetermined thickness value “Z”.
  • no heat treatment for further size reduction of the generally V-shaped hollow portion of the TEOS-BPSG film 7 may be carried out.
  • a heat treatment may be carried out at about 800-900° C. for about 10 minutes in a nitrogen atmosphere to cause a surface re-flow of the BPSG film 7 , whereby the small size generally V-shaped hollow portion on the surface of the BPSG film 7 is further reduced in size. Namely, a slight and smooth hollow resides on the surface of the BPSG film 7 .
  • a normal pressure chemical vapor deposition process with a higher deposition rate than the low pressure chemical vapor deposition process may be available by use of the TEOS gas, provided that the generally V-shaped hollow portion of the TEOS-NSG film 6 is completely filled with the TEOS-BPSG film 7 .
  • the TEOS gas trimethylphosphate (P(OCH 3 ) 3 ), triethylborate (B(OC 2 H 5 ) 3 ), and either oxygen (O 2 ) or ozone (O 3 ) are used as additives.
  • Another generally V-shaped hollow portion is formed on the surface of the TEOS-BPSG film 7 .
  • a normal pressure chemical vapor deposition process with a higher deposition rate than the low pressure chemical vapor deposition process may also be available without using the TEOS gas to deposit a BPSG film 7 , provided that the generally V-shaped hollow portion of the TEOS-NSG film 6 is completely filled with the BPSG film 7 .
  • the TEOS gas silane (SiH 4 ), phosphine (PH 3 ), diborane (B 2 H 6 ), and oxygen (O 2 ) are used.
  • Another generally V-shaped hollow portion is formed on the surface of the BPSG film 7 .
  • the BPSG film 7 is then subjected to an etch-back so that the total thickness of the TEOS-NSG film 6 and the BPSG film 7 over the oxide film 4 becomes the predetermined thickness value “Z”, wherein the BPSG film 7 remains not only within the small size generally V-shaped hollow portion of the TEOS-NSG film 6 but also over the surface of the TEOS-NSG film 6 .
  • the trench groove 5 is completely filled with the NSG film 6 .
  • This NSG film 6 has a large surface migration and a good surface coverage, for which reason no void is formed in the NSG film 6 .
  • the NSG film 6 is deposited with substantially keeping a thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 . Namely, in the chemical vapor deposition process, the thickness of the NSG film 6 is increased with keeping the thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 . For this reason, an upper surface of the NSG film 6 as deposited has a generally V-shaped hollow portion which is positioned over the trench groove 5 .
  • the NSG film 6 is then etched back, thereby reducing the size of the generally V-shaped hollow portion, before the small size generally V-shaped hollow portion of the NSG film 6 is then completely filled with the BPSG film 7 .
  • the BPSG film 7 shows a surface re-flow upon receipt of a heat, for which reason the surface re-flow of the BPSG film 7 is caused by the post heat treatment.
  • the further reduction in size of the generally V-shaped hollow is also caused to have a small taper angle of less than 20 degrees, and an imperfect planarization to the surface of the BPSG film 7 can be obtained. Namely, a slight or small hollow remains on the surface of the BPSG film 7 .
  • the desirable generally planarized surface of the BPSG film 7 can be obtained.
  • the two separate etch-back processes are made for the NSG film 6 and the BPSG film 7 , respectively for the purpose of the planarizations of the respective surfaces of the NSG film 6 and the BPSG film 7 .
  • the etch-back to the same material or the same film is suitable for obtaining the uniform etching rate and desirable more plane surface.
  • the etch-back is made to the oxide film 4 , then almost the same generally planarized surface can be obtained because the BPSG film 7 has the generally planarized surface after the heat treatment and before the etch-back. If no step is present on the top surface, the etch-back to thee oxide layer causes almost uniform etching rate over the entirety of the etched-surface.
  • the generally planarized surface after etch-back process provides the following advantages.
  • a metal interconnection layer is once entirely formed over the generally planarized surface, and then the metal interconnection layer is patterned or selectively removed to form an interconnection extending over the generally planarized surface. It is possible to avoid that the metal interconnection layer resides over the generally planarized surface. No metal over the generally planarized surface causes no short circuit between interconnections.
  • the NSG film 6 fills the trench groove 5 . Since the NSG film 6 has a large surface migration and a high surface coverage, in the chemical vapor deposition process, the NSG film 6 is deposited with keeping a thickness uniformity on side walls and a bottom of the trench groove 5 and over the oxide film 4 . Namely, in the chemical vapor deposition process, the thickness of the NSG film 6 adjacent to an opening edge of the trench groove 5 is substantially equal to the other portions thereof. This may cause no void in the NSG film 6 in the trench groove 5 . No void causes no deterioration of the trench isolation.
  • the NSG film 6 having the large surface migration and the high surface coverage is suitable for avoiding the void formation even allowing the generally V-shaped hollow on its surface.
  • the BPSG film 7 showing the surface re-flow upon heat treatment is deposited over the NSG film 6 for obtaining the generally planarized surface, whereby the etch-backed surface is the generally planarized surface which is suitable for forming integrated circuits.
  • first and second novel methods of the first and second embodiments are applicable to the formation of the trench isolation in substrates of any types, for example, elemental semiconductor substrates such as a silicon substrate, compound semiconductor substrates, semi-insulating substrates, insulating substrates and silicon-on-insulator substrates.
  • elemental semiconductor substrates such as a silicon substrate, compound semiconductor substrates, semi-insulating substrates, insulating substrates and silicon-on-insulator substrates.

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