US6064101A - Read-only memory cell arrangement - Google Patents

Read-only memory cell arrangement Download PDF

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Publication number
US6064101A
US6064101A US09/077,268 US7726898A US6064101A US 6064101 A US6064101 A US 6064101A US 7726898 A US7726898 A US 7726898A US 6064101 A US6064101 A US 6064101A
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memory cell
read
longitudinal trenches
cell arrangement
rows
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US09/077,268
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Wolfgang Krautschneider
Frank Lau
Franz Hofmann
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Infineon Technologies AG
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Siemens AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/50—ROM only having transistors on different levels, e.g. 3D ROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Definitions

  • the present invention relates to a semiconductor-based read-only memory cell arrangement which can be produced with both a small number of production steps and a high yield and which exhibits increased storage density.
  • Memories to which data are written permanently are required for many electronic systems. Such memories are referred to, inter alia, as read-only memories.
  • Plastic disks coated with aluminum are in wide-spread use as read-only memories for very large volumes of data. These plastic disks have two different kinds of point-like depressions in coating which are respectively assigned to the logic values zero and one. The information is stored digitally in the arrangement of these depressions. Such disks are referred to as compact disks and are widely used for the digital storage of music.
  • the disk In order to read the data which are stored on a compact disk, the disk is rotated mechanically using a reading apparatus.
  • the point-like depressions are scanned by means of a laser diode and a photocell.
  • Typical scanning rates in this case are 2 ⁇ 40 kHz. 5 Gbits of information can be stored on one compact disk.
  • the reading apparatus has moving parts which are subjected to mechanical wear, require a comparatively large volume and allow only slow data access.
  • the reading apparatus is furthermore sensitive to vibrations and can thus be used only to a limited extent in mobile systems.
  • Semiconductor-based read-only memories are known for the storage of smaller volumes of data. These memories are often formed as a planar integrated silicon circuit in which MOS transistors are used.
  • the MOS transistors are respectively selected via the gate electrode connected to the word line.
  • the input of the MOS transistor is connected to a reference line while the output is connected to a bit line.
  • An assessment is carried out during the reading operation to determine whether or not a current is flowing through the transistor.
  • the stored information is assigned accordingly.
  • the storage of the information is usually effected by the MOS transistors having different threshold voltages as a result of different implantation in the channel region.
  • semiconductor-based memories allow random access to stored information.
  • the electrical power required to read the information is distinctly less than in a reading apparatus having a mechanical drive. Since a mechanical drive is not required to read the information, the mechanical wear and the sensitivity to vibrations are obviated.
  • Semiconductor-based read-only memories can therefore be used for mobile systems as well.
  • MOS transistors In order to increase the storage density in planar silicon memories, it has been proposed to arrange the MOS transistors in rows. In each row, the MOS transistors are connected in series. The MOS transistors are read out by row-by-row driving in the sense of a NAND or NOR architecture. This requires only two terminals per row wherein the MOS transistors arranged in the row are connected in series between the terminals. Source/drain regions, connected to one another, of neighboring MOS transistors can then be formed as a coherent doped region. This enables the area requirement per memory cell to be reduced to a theoretical value of 4F 2 (F-smallest structure size that can be produced using the respective technology). Such a memory cell arrangement is disclosed, for example, in H. Kawagoe and N. Tsuji, IEEE J. Solid-State Circ., vol. SC-11, P. 360 (1976).
  • the present invention is directed to a semiconductor-based read-only memory cell arrangement in which an increased storage density is achieved and which can be produced with both a small number of production steps and a high yield.
  • the present invention is further directed to a method for producing such a memory cell arrangement.
  • the read-only memory cell arrangement of the present invention includes a multiplicity of individual memory cells in a semiconductor substrate which is preferably made of monocrystalline silicon.
  • the memory cells each include at least one MOS transistor.
  • the memory cells are each arranged in rows which are substantially parallel. Longitudinal trenches, which run substantially parallel to the rows, are provided in a main area of the semiconductor substrate. The rows are alternately arranged on the main area between neighboring longitudinal trenches and on the bottom of the longitudinal trenches.
  • Bit lines run transversely with respect to the rows and are each connected to source/drain regions of MOS transistors arranged along different rows.
  • Word lines are arranged above the rows and are each connected to the gate electrodes of MOS transistors arranged along a row.
  • doped layers in the semiconductor substrate between neighboring longitudinal trenches. Such doped layers act as a channel stopper.
  • the read-only memory cell arrangement can be formed with an area requirement per memory cell of 2F 2 (F-minimum structure size in the respective technology).
  • the MOS transistors of memory cells arranged along a row are connected in series.
  • Source/drain regions, connected to one another, of neighboring MOS transistors along a row are correspondingly designed as a coherent doped region in the semiconductor substrate.
  • Source/drain regions which are connected along a bit line, or transversely with respect to the longitudinal trenches, are connected to one another via doped regions in the semiconductor substrate.
  • the doped regions are arranged in each of the side walls of the longitudinal trenches.
  • the bit lines are respectively formed by both the source/drain regions and the doped regions in the side walls of the longitudinal trenches.
  • the longitudinal trenches are formed with a trench width of F and at a distance F, and if the extend of the coherent doped regions respectively acting as source/drain regions, connected to one another, of two MOS transistors amounts to F, and if the extent of the channel region amounts to F, then the resulting space requirement per memory cell is 2F 2 because each of the coherent doped regions belongs to two neighboring memory cells and because neighboring rows of memory cells are arranged directly next to one another. Insulation between neighboring rows of memory cells is ensured by the arrangement on the bottom of the longitudinal trench and on the main area of the semiconductor substrate between neighboring longitudinal trenches.
  • the MOS transistors have different threshold voltages depending on the information stored in the respective memory cell. In order to store data in a digital form, the MOS transistors have two different threshold voltages. If the read-only memory cell arrangement is to be used for multivalue logic, then the MOS transistors have more than two different threshold voltages depending on the stored information. It also lies within the scope of the present invention to realize different threshold voltages of the MOS transistors through different channel dopings of the MOS transistors.
  • the MOS transistors have a dielectric multilayer coating as gate dielectric.
  • the dielectric multilayer coating is provided with at lest one layer which has an increased electron capture cross-section compared with at lest one further layer in the multilayer coating.
  • the dielectric multilayer coating preferably includes an SiO 2 layer, an Si 3 N 4 layer and an SiO 2 layer (so-called ONO).
  • This embodiment of the read-only memory cell arrangement is one-time programmable by injecting electrons from the channel region of the MOS transistors into the multilayer coating. The injected electrons are retained by traps in the depletion layer between SiO 2 and Si 3 N 4 and increase the threshold voltage of the MOS transistor. In this way, the threshold voltage of the respective MOS transistor is varied in a targeted manner depending on the information to be stored in the respective memory cell.
  • the read-only memory cell arrangement is preferably produced using self-aligning process steps wherein the space requirement per memory cell can be reduced.
  • longitudinal trenches running substantially parallel are etched in a main area of a semiconductor substrate.
  • a multiplicity of memory cells which are arranged in rows, and which each include at least one MOS transistor, are produced wherein the rows are arranged alternately on the main area between neighboring longitudinal trenches and on the bottom of the longitudinal trenches.
  • the source/drain regions of the MOS transistors are produced by implantation wherein a source/drain mask is used which defines the arrangement of the source/drain regions of the memory cells.
  • doped regions are subsequently formed by angled implantation in the side walls of the longitudinal trenches. Such doped regions connect together source/drain regions arranged along different rows.
  • Word lines which are each connected to the gate electrodes of MOS transistors arranged along a row, are produced above the rows.
  • the source/drain regions which are connected to one another via doped regions in the side walls of the longitudinal trenches, and which are arranged along different rows, form bit lines in the read-only memory cell arrangement.
  • Such doped layer is etched through during the etching of the longitudinal trenches and acts as a channel stopper in the read-only memory cell arrangement.
  • FIG. 1 shows a silicon substrate after a first channel implantation.
  • FIG. 2 shows the silicon substrate of FIG. 1 after trench etching and a second channel implantation.
  • FIG. 3 shows a plan view of the silicon substrate of FIG. 2 with a source/drain mask after an implantation for the purpose of forming the source/drain regions, and an angled implantation for the purpose of forming doped regions in the side walls of the longitudinal trenches.
  • FIG. 4 shows the section through the silicon substrate which is designated by IV--IV in FIG. 3.
  • FIG. 5 shows the section through the silicon substrate which is designated by V--V in FIG. 3.
  • FIG. 6 shows a section through the silicon substrate of FIG. 3 after the formation of a gate dielectric and the deposition of both a conductive layer and an Si 3 N 4 layer.
  • FIG. 7 shows a section through the silicon substrate of FIG. 6 after the formation of Si 3 N 4 spacers and an oxide mask for structuring the conductive layer.
  • FIG. 8 shows a section through the silicon substrate of FIG. 7 after the formation of word lines by structuring of the conductive layer.
  • FIG. 9 shows the section designated by IX--IX in FIG. 8.
  • FIG. 10 shows the section designated by X--X in FIG. 8.
  • FIG. 11 shows a circuit diagram of the read-only memory cell arrangement.
  • a read-only memory cell arrangement in a substrate 1 made of, for example, monocrystalline silicon an insulation structure which defines the region of the read-only memory cell arrangement (not illustrated) and and which may define active regions for a peripheral area of the read-only memory cell arrangement is produced on a main area 2 of the substrate 1.
  • the insulation structure is formed, for example, in a LOCOS process or in a shallow trench insulation process.
  • the substrate 1 is, for example, p-doped with a dopant concentration of 5 ⁇ 10 15 cm -3 .
  • Implantation with boron is subsequently carried out in order to form a channel stop layer 3.
  • the boron implantation is carried out with, for example, a dose of 6 ⁇ 10 13 cm -2 and an energy of 120 keV.
  • the channel stop layer 3 is produced at a depth of 0.3 ⁇ m, for example, below the main area 2 with a thickness of 0.3 ⁇ m (see FIG. 1).
  • a photolithographic process is then used to define regions for the depletion channels of MOS transistors.
  • the depletion channels 4 are formed with the aid of a first channel implantation using arsenic with an energy of 50 keV and a dose of 4 ⁇ 10 13 cm -2 , for example.
  • the extent of the depletion channels 4 parallel to the main area 2 is 0.6 ⁇ m ⁇ 0.6 ⁇ m, for example, if a 0.4 ⁇ m technology is used.
  • a trench mask 5 is formed by structuring the SiO 2 layer with the aid of photolithographic processes (see FIG. 2).
  • Longitudinal trenches 6 are etched by anisotropic etching with Cl 2 , for example, using the trench mask 5 as an etching mask.
  • the longitudinal trenches 6 have a depth of 0.6 ⁇ m, for example.
  • the longitudinal trenches 6 reach down into the substrate 1 and cut through the channel stop layer 3.
  • the width of the depletion channels 4 is set during the etching of the longitudinal trenches 6. For this reason, the alignment of the trench mask 5 relative to the depletion channels 4 is not critical.
  • Spacers 7 made of SiO 2 are formed on the side walls of the longitudinal trenches 6 by depositing a further SiO 2 layer using a TEOS process and subsequent anisotropic etching. A photolithographic process is subsequently used to define regions for the depletion channels for MOS transistors which are subsequently produced on the bottom of the longitudinal trenches 6.
  • Depletion channels 8 are produced on the bottom of the longitudinal trenches 6 by means of a second channel implantation with, for example, arsenic and an energy of 50 keV and a dose of 4 ⁇ 10 13 cm -2 .
  • the regions between neighboring longitudinal trenches 6 are masked in the process by the trench mask 5 and the spacers 7. Therefore, alignment during the definition of the depletion channels 8 is not critical.
  • the second channel implantation is self-aligned with regard to the side walls of the longitudinal trenches 6.
  • the trench mask 5 is subsequently removed wet-chemically using NH 4 F/HF, for example.
  • the spacers 7 are removed at the same time.
  • a thin SiO 2 layer 9 is grown to a thickness of 20 nm, for example, on the silicon surface.
  • the thin SiO 2 layer 9 improves the silicon surface in the sense of a sacrificial oxide.
  • a polysilicon layer is subsequently deposited over the whole area.
  • the polysilicon layer is produced with a thickness of 500 nm, for example and is intrinsically doped.
  • a source/drain mask 10 is formed by structuring the polysilicon layer (see FIG. 3, FIG. 4, FIG. 5).
  • the source/drain mask 10 defines the arrangement of source/drain regions to be produced afterwards.
  • the source/drain mask 10 has polysilicon strips which cover the silicon surface in each of the regions in which channel regions for MOS transistors are subsequently produced.
  • upper source/drain regions 11a are respectively formed in the region of the main area 2 between neighboring longitudinal trenches 6 and lower source/drain regions 11b are respectively formed on the bottom of the longitudinal trenches 6.
  • the implantation is carried out substantially perpendicularly with respect to the main area 2 (see FIG. 3 and FIG. 5).
  • Doped regions 12 are formed in the side walls of the longitudinal trenches 6 by ion implantation with an angle of inclination of 40°, for example, such doped regions respectively connect an upper source/drain region 11a to a lower source/drain region 11b (see FIG. 5).
  • the angled implantation is carried out, for example, using arsenic with an energy of 5 ⁇ 10 15 cm -2 and a dose of 5 ⁇ 10 15 cm -2 .
  • the source/drain mask 10 is subsequently removed by dry or wet etching which attacks polysilicon selectively with respect to SiO 2 . Accordingly, the thin SiO 2 layer 9 acts as an etching stop.
  • the source/drain mask 10 is removed, for example, by wet etching using polysilicon etchant (HF/HNO 3 /H 2 O) or by dry etching using HBr and Cl 2 .
  • the thin SiO 2 layer 9 is subsequently removed using hydrofluoric acid (HF), for example.
  • HF hydrofluoric acid
  • SiO 2 spacers 13 are formed on the side walls of the longitudinal trenches 6 by deposition of an SiO 2 layer in a TEOS process and subsequent anisotropic etching (see FIG. 6).
  • a gate dielectric 14 made of SiO 2 is formed to a thickness of 10 nm, for example, by thermal oxidation.
  • An oxidation conductive layer 15 is subsequently produced over the whole area to a thickness of approximately 100 to 200 nm.
  • the oxidizable conductive layer 15 is preferably formed from doped polysilicon.
  • the oxidizable conductive layer 15 may be formed of a metal silicide or a combination of doped polysilicon and silicide.
  • Si 3 N 4 layer 16 is deposited over the whole area to a thickness of 30 to 80 nm, for example. Planar parts of the Si 3 N 4 layer 16 are removed by anisotropic etching and Si 3 N 4 spacers 17 are formed. In the process, the surface of the oxidizable conductive layer 15 is uncovered in planar regions. The Si 3 N 4 spacers 17 cover the oxidizable conductive layer 15 in the region of the side walls of the longitudinal trenches 6 (see FIG. 7).
  • Uncovered regions of the oxidizable conductive layer 15 are subsequently oxidized.
  • the Si 3 N 4 spacers 17 act as an oxidation mask and allow selective oxidation in the planar regions of the oxidizable conductive layer 15.
  • an oxide mask 18 is formed which covers the planar regions of the oxidizable conductive layer 15.
  • the Si 3 N 4 spacers 17 are subsequently removed.
  • the oxidizable conductive layer 15 is structures in an etching process which attacks the oxidizable conductive layer 15 selectively with respect to the oxide mask 18.
  • Word lines 19 running parallel to the longitudinal trenches 6 are produced in the process on the bottom of the longitudinal trenches 6 and also between neighboring longitudinal trenches 6 (see FIG. 8, FIG. 9 and FIG. 10).
  • the selective oxidation for forming the oxide mask 18 makes it possible to structure the word lines 19 in a self-aligned manner with respect to the course of the longitudinal trenches 6.
  • the width of such word lines 19 is less than the minimum structure size F-particularly on the bottom of the longitudinal trenches 6.
  • the read-only memory cell arrangement is wired up in a NOR configuration (see FIG. 11).
  • This circuit architecture enables access to each individual memory cell within short time constants.
  • the word lines are designated by WL and the bit lines by BL.
  • the read-only memory cell arrangement is completed by deposition of an intermediate oxide. Contact holes are subsequently etched wherein the side walls of the contact holes are provided with insulating spacers and wherein the contact holes are filled with tungsten, for example. Finally, a metallization plane is produced by depositing a metal layer and structuring the metal layer (not illustrated).
  • the gate dielectric 14 may alternatively be formed from a layer sequence SiO 2 , Si 3 N 4 and SiO 2 (ONO).
  • the read-only memory cell arrangement is one-time programmable by electron injection from the channel region of the MOS transistors into the gate dielectric. Electrons captured in the gate dielectric increase the threshold voltage of the MOS transistor. Accordingly, the two channel implantations for setting different threshold voltages are omitted.
  • a suitable choice of the voltage conditions during the injection of electrons makes it possible to set different threshold voltages in order to represent a plurality of logic values.

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Applications Claiming Priority (3)

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DE19545903 1995-12-08
DE19545903A DE19545903C2 (de) 1995-12-08 1995-12-08 Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung
PCT/DE1996/002328 WO1997022139A2 (de) 1995-12-08 1996-12-05 Festwertspeicherzellenanordnung und verfahren zu deren herstellung

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US (1) US6064101A (ko)
EP (1) EP0865667B1 (ko)
JP (1) JP2000501886A (ko)
KR (1) KR100404239B1 (ko)
DE (2) DE19545903C2 (ko)
WO (1) WO1997022139A2 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303436B1 (en) * 1999-09-21 2001-10-16 Mosel Vitelic, Inc. Method for fabricating a type of trench mask ROM cell
US9012318B2 (en) 2012-09-21 2015-04-21 Micron Technology, Inc. Etching polysilicon

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2247441C2 (ru) 2000-08-11 2005-02-27 Инфинеон Текнолоджиз Аг Устройство памяти и способ изготовления
DE10039441A1 (de) * 2000-08-11 2002-02-28 Infineon Technologies Ag Speicherzelle, Speicherzellenanordnung und Herstellungsverfahren
GB0101695D0 (en) * 2001-01-23 2001-03-07 Koninkl Philips Electronics Nv Manufacture of trench-gate semiconductor devices
DE10129958B4 (de) 2001-06-21 2006-07-13 Infineon Technologies Ag Speicherzellenanordnung und Herstellungsverfahren
JP2003017590A (ja) 2001-06-29 2003-01-17 Toshiba Corp 半導体装置及びその製造方法
DE202011109765U1 (de) 2011-05-12 2012-05-08 Marc Wronka Gewichtsgesteuertes Winddruckentlastungssystem

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02106966A (ja) * 1988-10-17 1990-04-19 Seiko Epson Corp 半導体記憶装置
JPH03190165A (ja) * 1989-12-20 1991-08-20 Sony Corp 読み出し専用メモリ装置及びその製造方法
JPH04226071A (ja) * 1990-05-16 1992-08-14 Ricoh Co Ltd 半導体メモリ装置
JPH05308135A (ja) * 1992-04-30 1993-11-19 Ricoh Co Ltd 半導体メモリ装置とその製造方法
US5300804A (en) * 1991-05-31 1994-04-05 Mitsubishi Denki Kabushiki Kaisha Mask ROM device having highly integrated memory cell structure
US5306941A (en) * 1991-10-09 1994-04-26 Ricoh Company, Ltd. Semiconductor memory device and production process thereof
US5453637A (en) * 1994-05-18 1995-09-26 United Microelectronics Corp. Read-only memory cell configuration with steep trenches
DE19510042A1 (de) * 1995-03-20 1996-09-26 Siemens Ag Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung
US5747856A (en) * 1994-11-01 1998-05-05 Taiwan Semiconductor Manufacturing Company Ltd. Vertical channel masked ROM memory cell with epitaxy
US5751040A (en) * 1996-09-16 1998-05-12 Taiwan Semiconductor Manufacturing Company Ltd. Self-aligned source/drain mask ROM memory cell using trench etched channel

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02106966A (ja) * 1988-10-17 1990-04-19 Seiko Epson Corp 半導体記憶装置
JPH03190165A (ja) * 1989-12-20 1991-08-20 Sony Corp 読み出し専用メモリ装置及びその製造方法
JPH04226071A (ja) * 1990-05-16 1992-08-14 Ricoh Co Ltd 半導体メモリ装置
US5300804A (en) * 1991-05-31 1994-04-05 Mitsubishi Denki Kabushiki Kaisha Mask ROM device having highly integrated memory cell structure
US5306941A (en) * 1991-10-09 1994-04-26 Ricoh Company, Ltd. Semiconductor memory device and production process thereof
JPH05308135A (ja) * 1992-04-30 1993-11-19 Ricoh Co Ltd 半導体メモリ装置とその製造方法
US5453637A (en) * 1994-05-18 1995-09-26 United Microelectronics Corp. Read-only memory cell configuration with steep trenches
US5747856A (en) * 1994-11-01 1998-05-05 Taiwan Semiconductor Manufacturing Company Ltd. Vertical channel masked ROM memory cell with epitaxy
DE19510042A1 (de) * 1995-03-20 1996-09-26 Siemens Ag Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung
US5751040A (en) * 1996-09-16 1998-05-12 Taiwan Semiconductor Manufacturing Company Ltd. Self-aligned source/drain mask ROM memory cell using trench etched channel

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303436B1 (en) * 1999-09-21 2001-10-16 Mosel Vitelic, Inc. Method for fabricating a type of trench mask ROM cell
US9012318B2 (en) 2012-09-21 2015-04-21 Micron Technology, Inc. Etching polysilicon
US9650570B2 (en) 2012-09-21 2017-05-16 Micron Technology, Inc. Compositions for etching polysilicon
US10113113B2 (en) 2012-09-21 2018-10-30 Micron Technology, Inc. Removing polysilicon
US10479938B2 (en) 2012-09-21 2019-11-19 Micron Technology, Inc. Removing polysilicon

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DE19545903C2 (de) 1997-09-18
EP0865667A2 (de) 1998-09-23
WO1997022139A3 (de) 1997-08-21
KR19990071849A (ko) 1999-09-27
DE19545903A1 (de) 1997-06-12
KR100404239B1 (ko) 2003-12-18
JP2000501886A (ja) 2000-02-15
DE59603599D1 (de) 1999-12-09
EP0865667B1 (de) 1999-11-03
WO1997022139A2 (de) 1997-06-19

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