US5790439A - Reduced test time finite impulse response digital filter - Google Patents

Reduced test time finite impulse response digital filter Download PDF

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US5790439A
US5790439A US08/751,165 US75116596A US5790439A US 5790439 A US5790439 A US 5790439A US 75116596 A US75116596 A US 75116596A US 5790439 A US5790439 A US 5790439A
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multiply
accumulation operation
scan
output
operation unit
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Kazuya Yamanaka
Shuji Murakami
Nobuhiro Miyoshi
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Mitsubishi Electric Engineering Co Ltd
Mitsubishi Electric Corp
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Mitsubishi Electric Engineering Co Ltd
Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters

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  • the present invention relates to a digital filter, and particularly to a digital filter of a finite impulse response type circuit having operation units connected in a cascade for performing multiply-accumulation operation using multipliers and adders.
  • Typical semiconductor integrated circuits having a multiply-accumulation operation circuit constructed using multipliers and adders include digital filters.
  • digital filters With development of digital signal processing technology, the digital filters are increasingly replacing analogue filters in the fields of communication and people's death.
  • FIG. 12 is a block diagram showing general structure of a digital filter 100 of a finite impulse response (FIR) type circuit having cascaded multiply-accumulation operation units (taps) performing multiply-accumulation operation.
  • the digital filter 100 includes n multiply-accumulation operation units 15 0 -15 n-1 cascaded between first and second data inputs DATA1, DATA2 and a data output DOUT and a register (illustrated as a flip-flop in the figure) 8 n .
  • a first aspect of the present invention is directed to a digital filter comprising a cascade connection of 0-th to (n-1)-th multiply-accumulation operation units (n: a natural number of 2 or larger).
  • the 0-th multiply-accumulation operation unit includes a multiplier performing a multiplication of data to be processed by the digital filter and a 0-th coefficient
  • each s-th (1 ⁇ s ⁇ (n-1)) multiply-accumulation operation unit includes a multiplier performing a multiplication of the data and an i-th coefficient, a scan register selectively outputting a data input which is an output of the (s-1)-th multiply-accumulation operation unit and a scan input according to a control signal on the basis of a first clock signal, and an adder performing an addition of an output of the multiplier and an output of the scan register and outputting the result to a next stage.
  • the scan registers of the first through (n-1)-th multiply-accumulation operation units form a scan path, and a result of filter
  • each i-th (0 ⁇ i ⁇ (n-1)) multiply-accumulation operation unit further includes a shift register providing the i-th coefficient to the multiplier.
  • the shift registers of the 0-th to (n-1)-th multiply-accumulation operation units are connected in series with each other.
  • the shift registers of the 0-th to (n-1)-th multiply-accumulation operation units can make input/output with the number of bits required for the i-th coefficient.
  • the shift registers of the 0-th to (n-1)-th multiply-accumulation operation units can make input/output with 1 bit, and are connected in series to each other and connected to the scan path.
  • each i-th (0 ⁇ i ⁇ (n-1)) multiply-accumulation operation unit further includes a register providing the i-th coefficient to the multiplier.
  • the registers of the 0-th to (n-1)-th multiply-accumulation operation units are connected in series with each other and connected to the scan path.
  • the register of the i-th multiply-accumulation operation unit is a shift register which can make input/output with 1 bit.
  • the register of the i-th multiply-accumulation operation unit is a scan register operating on the basis of a second clock signal and serving as a component of the scan path, which selectively outputs a data input and a scan input according to the control signal, and at least the i-th coefficient is supplied as the data input to the scan register.
  • An eighth aspect of the present invention is directed to a digital filter comprising a cascade connection of 0-th to (n-1)-th multiply-accumulation operation units (n:a natural number of 2 or larger), wherein the 0-th multiply-accumulation operation unit includes a multiplier performing a multiplication of data to be processed by the digital filter and a 0-th coefficient.
  • Each s-th (1 ⁇ s ⁇ (n-1)) multiply-accumulation operation unit includes a multiplier performing multiplication of the data and an i-th coefficient, a first selector having a first input end receiving an output of the (s-1)-th multiply-accumulation operation unit and a second input end, for selectively outputting signals applied to the first input end and the second input end according to a control signal, a first shift register transmitting an output of the first selector on the basis of a first clock signal, and an adder performing an addition of an output of the multiplier and an output of the first shift register of its own and outputting its result to a next stage.
  • the second input ends of the first selectors of the first to (n-1)-th multiply-accumulation operation units are connected in common and supplied with first test data, and a result of filtering processing to the data input is obtained from the output of the (n-1)-th multiply-accumulation operation unit.
  • each i-th (0 ⁇ i ⁇ (n-1)) multiply-accumulation operation unit further includes a second shift register applying the i-th coefficient to the multiplier and operating on the basis of a second clock signal.
  • Each s-th multiply-accumulation operation unit further includes a second selector having a first input end receiving an output of the second shift register of the (s-1)-th multiply-accumulation operation unit and a second input end for selectively outputting signals applied to the first input end and the second input end according to the control signal, wherein the second input ends of the second selectors of the first to (n-1)-th multiply-accumulation operation units are connected in common and supplied with second test data.
  • the digital filter grasps the output of the (n-1)-th multiply-accumulation operation unit collectively for every certain bits as output groups, wherein whether the digital filter is good or bad is determined according to agreement/disagreement of the output groups adjacently outputted.
  • the test can be conducted with reduced test vectors and test time.
  • test for the registers holding coefficients multiplied to data subjected to filter processing by the digital filter can be conducted separately from test to the multipliers and adders. Furthermore, it does not require a long time to store the coefficients for multiplication in the shift registers.
  • a test with suppressed test vectors can be realized with a simple structure. It can be applied also to the case where data applied as coefficient from an external interface is of serial type.
  • the first test data for test of multiply-accumulation operation can be supplied to the first shift registers all at once in respective multiply-accumulation operation units through the first selectors.
  • the time required to store the first test data can be reduced and tests with the same contents can be conducted at the same time separately for each multiply-accumulation operation unit with reduced test vectors in a reduced test time.
  • the second test data for testing the registers holding coefficients used in multiplication can be provided to the second shift registers all at once in respective multiply-accumulation operation units through the second selectors. Hence, the time required for storage of the second test data is reduced and the test of the registers holding the coefficients can be made separately from, and in parallel with, the test for multiply-accumulation operation.
  • the digital filter of the tenth aspect of the present invention it can be determined whether the digital filter is good or bad without requiring large-scale test apparatus and test vectors.
  • the present invention has been made to solve the problems described above, and it is an object of the present invention to provide technique which enables a test of a digital filter with a smaller number of test vectors.
  • FIG. 1 is a block diagram showing the structure of a digital filter 101 according to a first preferred embodiment.
  • FIG. 2 is a timing chart showing operation of the first preferred embodiment.
  • FIG. 3 is a block diagram showing the structure of a digital filter 102 according to a second preferred embodiment.
  • FIG. 4 is a timing chart showing operation of the second preferred embodiment.
  • FIG. 5 is a block diagram showing the structure of a digital filter 103 according to a third preferred embodiment.
  • FIG. 6 is a timing chart showing operation of the third preferred embodiment.
  • FIG. 7 is a block diagram showing the structure of a digital filter 104 according to a fourth preferred embodiment.
  • FIG. 8 is a timing chart showing operation of the fourth preferred embodiment.
  • FIG. 9 is a block diagram showing the structure of a digital filter 105 according to a fifth preferred embodiment.
  • FIG. 10 is a circuit diagram illustrating the structure of the demultiplexer 19.
  • FIG. 11 is a timing chart showing operation of the fifth preferred embodiment.
  • FIG. 12 is a block diagram showing the structure of a conventional digital filter 100.
  • FIG. 13 is a block diagram illustrating a scan path.
  • FIG. 14 is a block diagram illustrating the structure of the scan register.
  • FIG. 13 is a block diagram showing an example of insertion of a scan path.
  • the route shown by the broken lines in the figure is the scan path.
  • the interconnections shown by broken lines are also actually provided interconnections.
  • the broken lines are used only to show that those are scan paths, which are the same as interconnections shown by solid lines in other respects.
  • the (p+1) data DATA 0 -DATA p are provided as inputs to a logic circuit 14 and the data DOUT 0 -DOUT q are provided as outputs from the logic circuit 14.
  • Scan registers (shown as scan flip-flops in the figure) are interposed between inputs and outputs of the data (in the data paths).
  • FIG. 14 is a block diagram showing the structure of the scan register.
  • the scan register has two inputs, a data input and a scan input, which are applied by a selector 11 to a flip-flop 8 in an alternative way on the basis of a control signal SELECT.
  • the flip-flop 8 outputs its hold content in synchronization with a clock signal CLK.
  • An output of a scan register becomes a scan input to an adjacent scan register, the scan registers being connected in series to form the scan path from a scan-in signal SIN to a scan-out signal SOUT.
  • the control signal it is possible by switching the control signal to use the scan registers as ordinary registers in normal operation of the circuit and to form the scan path in test.
  • the scan path allows a register in an arbitrary position to be set to an arbitrary value in testing and also allows values of the registers after operation to be directly observed, providing the effect of enabling easy production of test vectors and expected values.
  • a scan register is provided for each multiply-accumulation operation unit with a scan path passing through all the multiply-accumulation operation units so that a test can be conducted with a small number of test vectors.
  • FIG. 1 is a block diagram showing the structure of a digital filter 101 according to this preferred embodiment.
  • the multiplier 2 i performs multiplication of the m-bit first data input DATA1 and the k-bit coefficient C i and applies its result to the adder 3 i .
  • the adder 3 i performs addition of j bits, which adds the output from the multiplier 2 i and the output of the scan flip-flop 22 i and transmits it to the next stage.
  • the scan flip-flops 21 i , 22 i process k-bit data and j-bit data, respectively, and both make input/output of a scan signal with 1 bit.
  • the scan flip-flops 21 i , 22 i operate in synchronization with clock signals CLIK2, CLK1, respectively.
  • a control signal SELECT is provided in common to all scan flip-flops 21 i , 22 i and the selection operation of the selector 11 shown in FIG. 14 is changed all at once.
  • the k-bit data input and the 1-bit scan input of the scan flip-flop 21 i of the multiply-accumulation operation unit 4 i receive the k-bit data output and the 1-bit scan output of the scan flip-flop 21 j-1 of the multiply-accumulation operation unit 4 j-1 in the previous stage, respectively.
  • the j-bit data input and the 1-bit scan input of the scan flip-flop 22 i receive the j-bit data output of the adder 3 i-1 of the multiply-accumulation operation unit 4 i-1 in the previous stage and the 1-bit scan output of the scan flip-flop 22 i+1 in the next stage, respectively.
  • the k-bit data input and the 1-bit scan input of the scan flip-flop 21 0 of the first stage multiply-accumulation operation unit 4 0 receive a k-bit coefficient input COEF and a scan-in signal SIN, respectively.
  • the second data input DATA2 is given as the j-bit data input to the scan flip-flop 22 0 and its 1-bit scan output is provided as a scan-out signal SOUT of the digital filter 101.
  • the scan flip-flop 22 0 is provided in the first stage multiply-accumulation operation unit 4 0 .
  • the scan flip-flop 22 0 can be eliminated when the digital filter 101 is used alone or when a plurality are connected in a cascade if it is determined to be located in the head, because then there is no need to receive an output of an adder from the previous stage.
  • the second data input DATA2 is not necessary in this case, and the scan output of the scan flip-flop 22 1 of the multiply-accumulation operation unit 4 1 is outputted from the digital filter 101 as the scan-out signal SOUT.
  • the 1-bit scan output of the scan flip-flop 21 n-1 of the final stage multiply-accumulation operation unit 4 n-1 is given as the scan input to the scan flip-flop 22 n and the 1-bit scan input of the scan flip-flop 22 n-1 receives the scan output of the scan flip-flop 22 n .
  • the scan flip-flop 22 n transmits its j-bit output as an output DOUT of the digital filter 101.
  • control signal SELECT performs control so that the scan flip-flops 21 0 , 21 1 , . . . , 21 n-1 , 22 0 , 22 1 , . . . , 22 n selectively receive the data inputs.
  • coefficients C n-1 , . . . , C 1 , C 0 are sequentially given from the coefficient input COEF to the scan flip-flop 21 0 .
  • These coefficients are transmitted sequentially to the scan flip-flops 21 0 , 21 1 , . . . , 21 n-1 in synchronization with the clock signal CLK2 and then the coefficients C 0 , C 1 , . . . , C n-1 are stored in the scan flip-flops 21 0 , 21 1 , . . . , 21 n-1 , respectively.
  • each multiply-accumulation operation unit 4 i multiplication of the coefficient C i and the first data input DATA1 is carried out in the multiplier 2 i , and its result is given as one input to the adder 3 i .
  • the clock signal CLK2 is stopped and transition of the clock signal CLK1 is started, and then an output of the adder 3 i-1 of the previous stage multiply-accumulation operation unit 4 i-1 is provided as the other input to the adder 3 i through the flip-flop 22 i in each multiply-accumulation operation unit 4 i .
  • the second data input DATA2 is provided as the other input to the adder 3 0 of the first stage multiply-accumulation operation unit 4 0 .
  • the scan flip-flop 22 i outputs its hold value at the timing of transition of the clock signal CLK1 from “L” to "H” (rise) and newly holds input. Accordingly, the clock signal CLK1 rises (n+1) times corresponding to the number of scan flip-flops 22 0 -22 n and then the filter processed output DOUT of the digital filter 101 is obtained from the scan flip-flop 22 n .
  • Such operation based on the clock signal CLK1 is the same as the normal operation of the conventional digital filter 100 shown in FIG. 12, which is not inferior to it.
  • FIG. 2 is a timing chart showing waveforms of the clock signals CLK1, CLK2, the control signal SELECT and the scan-out signal SOUT in test operation of the digital filter 101.
  • control signal SELECT performs control so that the scan flip-flops 21 0 , 21 1 , . . . , 21 n-1 , 22 0 , 22 1 , . . . , 22 n selectively receive the scan inputs.
  • the value for causing scan input is "H” and the value for causing data input is "L”.
  • the clock signals CLK1, CLK2 exhibit waveforms making the same transitions.
  • Test data is sequentially applied bit by bit to the scan-in signal SIN, which are sequentially transmitted to the scan flip-flops 21 0 , 21.sub., . . . , 21 n-1 , 22 n , . . . , 21 1 , 22 0 through the scan path in synchronization with transitions of the clock signals CLK1, CLK2. It is necessary in order to carry out a test to cause the scan flip-flops 21 0 -21 n-1 to store k-bit data and the scan flip-flops 22 0 -22 n to store j-bit data. Therefore ⁇ j ⁇ (n+1)+k ⁇ n ⁇ rises of the clock signals CLK1 and CLK2 are required to store the test data.
  • a value D1 is given as first data DATA1 for one period of the clock signals CLK1, CLK2 after the ⁇ j ⁇ (n+1)+k n ⁇ -th rise. Then the value D1 of the first data DATA1 is multiplied by the k-bit test data stored in each of the scan flip-flops 21 0 , 21 1 , . . . , 21 n-1 , results of which are added with the j-bit test data stored in the scan flip-flops 22 0 -22 n-1 in the adders 3 0 -3 n-1 , respectively.
  • the control signal SELECT is caused to make transition so that it takes the value "L” at the ⁇ j ⁇ (n+1)+k ⁇ n+1 ⁇ -th rise of the clock signals CLK1, CLK2.
  • outputs of the adders 3 0 -3 n-1 are stored in the scan flip-flops 22 1 -22 n , respectively.
  • the control signal SELECT is caused to make transition so that it again takes the value "H" at and after the ⁇ j ⁇ (n+1)+k ⁇ n+2 ⁇ -th clock signals CLK1, CLK2.
  • data is obtained as the scan-out signal SOUT through the scan path.
  • the first j bits of the scan-out signal SOUT are data stored in the scan flip-fop 22 0 and examining this value allows determination as to whether the test data has been correctly transmitted through the scan path.
  • the j ⁇ n bits of the scan-out signal SOUT obtained thereafter are values stored in the scan flip-flops 22 1 -22 n , which respectively show operation results of the multiply-accumulation operation units 4 0 -4 n-1 . Therefore conditions of all multiply-accumulation operation units can be determined by examining them.
  • the following k ⁇ n bits are values stored in the scan flip-flops 21 n-1 -21 1 and examining them allows determination as to whether the test data has been correctly transmitted through the scan path.
  • test data if the first j ⁇ (n+1) bits are set to the same values for every j bits and the next k ⁇ n bits are set to the same values for every k bits, then operation results of all multiply-accumulation operation units can be equal when the digital filter 101 is normal.
  • the digital filter 101 normally operates, data for j ⁇ n bits after the j-th bit in the scan-out signal SOUT provide the same values for every j bits and the k ⁇ n bits after that provide the same values for every k bits. Accordingly, whether the digital filter 101 is good or bad can be determined by comparing the scan-out signal SOUT with expected values.
  • Testing in this way allows tests with the same contents to be performed at the same time separately for each multiply-accumulation operation unit, which permits reduction in test vectors and test time.
  • the scan flip-flop 22 0 can be omitted in the first stage multiply-accumulation operation unit 4 0 .
  • the number of clocks required for storage of test data can be only (j+k) ⁇ n.
  • evaluation of the scan-out signal SOUT it can be evaluated whether operation results of the multiply-accumulation operation units 4 0 -4 n-1 are correct or not by checking the j ⁇ n bits and it can be evaluated whether the test data has been correctly transmitted through the scan path by checking the following k ⁇ n bits.
  • the number of clocks shown in FIG. 2 is replaced by (j+k) n.
  • FIG. 3 is a block diagram showing the structure of a digital filter 102 according to this preferred embodiment.
  • An output of the shift register 6 i-1 of the multiply-accumulation operation unit 5 i-1 on the previous stage is given to the input to the shift register 6 i of the multiply-accumulation operation unit 5 i , which is transmitted to the next stage in synchronization with the clock signal CLK2.
  • the shift register 6 i provides its hold value to the adder 2 i . Note that the input of the shift register 6 0 of the multiply-accumulation operation unit 5 0 in the first stage receives the data bit by bit from the coefficient input COEF.
  • the scan flip-flop 22 i receives the same signals as those in the digital filter 101 as its j-bit data input and 1-bit scan input, but the scan flip-flop 22 n receives the output of the shift register 6 n-1 as its 1-bit scan input.
  • the digital filter 102 constructed as explained above performs normal operation and test operation as follows.
  • the control signal SELECT performs control so that the scan flip-flops 22 0 , 22 1 , . . . , 22 n selectively receive the data input.
  • the coefficients C n-1 , . . . , C 1 , C 0 are sequentially provided to the shift register 6 0 bit by bit from the coefficient input COEF in synchronization with the clock signal CLK2. These coefficients are sequentially transmitted through the shift registers 6 0 , 6 1 , . . . , 6 n-1 in synchronization with the clock signal CLK2 and then the coefficients C 0 , C 1 , . . .
  • FIG. 4 is a timing chart showing waveforms of the clock signals CLK1, CLK2, the control signal SELECT and the scan-out signal SOUT in test operation of the digital filter 102.
  • control signal SELECT takes the value "H" to control the scan flip-flops 22 0 , 22 1 , . . . , 22 n so that they selectively receive the scan input.
  • the clock signals CLK1, CLK2 make a certain number of transitions in synchronization with each other.
  • Test data is sequentially provided from the coefficient input COEF bit by bit, which are sequentially transmitted through the scan path to the shift registers 6 0 , 6 1 , . . . , 6 n-1 , 22 n , . . . , 22 1 , 22 0 in synchronization with transitions of the clock signals CLK1, CLK2.
  • the arrows sequentially directed from the coefficient input COEF to the shift registers 6 0 , 6 1 , . . . , 6 n-1 are used not only in normal operation but also in test operation, which form a route connected in series to the scan path.
  • a value D1 is given as the first data DATA1 for one period of the clock signals CLK1, CLK2 after the ⁇ j ⁇ (n+1)+k ⁇ n ⁇ -th rise. Then the value D1 of the first data DATA1 is multiplied by the k-bit test data stored in each shift register 6 0 , 6 1 , . . . , 6 n-1 , and the results are added with the j-bit test data stored in the scan flip-flops 22 0 -22 n-1 in the adders 3 0 -3 n-1 , respectively.
  • the clock signal CLK1 makes the ⁇ j ⁇ (n+1)+k ⁇ n+2 ⁇ -th rise and so on. From this time on, the clock signal CLK2 makes transitions in synchronization with the clock signal CLK1 again. At the ⁇ j ⁇ (n+1)+k ⁇ n+2 ⁇ -th and later rises of the clock signal CLK1, the control signal SELECT is caused to make transition to take the value "H" again. Examining the scan-out signal SOUT obtained in this way allows determination as to whether the digital filter 102 is good or bad, similarly to the first preferred embodiment.
  • the second preferred embodiment produces the effect of realizing the test above with simpler structure of reduced circuit scale because part of the scan flip-flops are replaced by the shift registers. It is also advantageous in that it can be applied to the case where data of serial type are provided as the coefficient COEF from an external interface.
  • the scan flip-flop 22 0 can be omitted in the first stage multiply-accumulation operation unit 5 0 as has been stated in the first preferred embodiment.
  • the number of clocks shown in FIG. 4 is replaced by (j+k) ⁇ n.
  • FIG. 5 is a block diagram showing the structure of a digital filter 103 according to this preferred embodiment.
  • An output of the shift register 8 i-1 in the multiply-accumulation operation unit 7 i-1 in the previous state is provided to an input of the shift register 8 i of the multiply-accumulation operation unit 7 i , which is transmitted to the next stage in synchronization with the clock signal CLK2.
  • the shift register 8 i provides its hold value to the adder 2 i .
  • the input of the shift register 8 0 of the multiply-accumulation operation unit 7 0 in the first stage receives the data of k bits at a time (k-bit data) from the coefficient input COEF.
  • the output of the shift register 8 n-1 of the multiply-accumulation operation unit 7 n-1 in the final stage is subjected to a test as a coefficient output COEFOUT, as will be described later.
  • Data input of j bits of the scan flip-flop 22 i is the same as those in the first and second preferred embodiments but the scan path is formed only of the scan flip-flops 22 0 , 22 1 , . . . , 22 n .
  • the flow of the scan signal is opposite to that in the first and second preferred embodiments. That is to say, the 1-bit scan-in signal SIN is first provided as a scan input to the scan flip-flop 22 0 of the multiply-accumulation operation unit 7 0 in the first stage and then sequentially transmitted to the scan flip-flops 22 1 , . . . , 22 n-1 , 22 n in synchronization with the clock signal CLK1. Output of the scan flip-flop 22 n is subject to test as the scan-out signal SOUT, as will be described later.
  • the normal operation where only the shift registers 6 i are replaced by the shift registers 8 i in the normal operation in the second preferred embodiment, is the same as the normal operation in the second preferred embodiment except that the coefficient C i sequentially provided from the coefficient input COEF is transmitted by k-bit. That is, the same multiply-accumulation operation as the first preferred embodiment is carried out in each multiply-accumulation operation unit 7 i , and an output DOUT of the digital filter 103 is obtained by stopping the clock signal CLK2 and starting transition of the clock signal CLK1.
  • FIG. 6 is a timing chart showing waveforms of the clock signals CLK1, CLK2, the control signal SELECT and the scan-out signal SOUT in test operation of the digital filter 103.
  • the control signal SELECT makes control so that the scan flip-flops 22 0 -22 n selectively receive the scan input. While the scan-in signal SIN is provided bit by bit to the scan path formed of the scan flip-flops 22 0 -22 n-1 , it is necessary to cause these scan flip-flops 22 0 -22 n-1 to store j-bit data. In order to cause them to store the test data, the clock signal CLK1 must rise j ⁇ n times.
  • Test data is sequentially given k bits at a time (k-bit data) from the coefficient input COEF independently of storage of the test data in the scan flip-flops 22 0 -22 n , which are sequentially transmitted to the shift registers 8 0 , 8 1 , . . . , 8 n-1 in synchronization with transitions of the clock signal CLK2.
  • the clock signal CLK2 must rise n times. While FIG.
  • the value D1 is provided as the first data DATA1 for only one period of the clock signal CLK1.
  • the value D1 of the first data DATA1 is thus multiplied by the k-bit test data stored in each shift register 8 0 , 8 1 , . . . , 8 n-1 , and the results are added in the adders 3 0 -3 n-1 with the j-bit test data stored in the scan flip-flops 22 0 -22 n-1 , respectively.
  • the control signal SELECT is caused to make a transition to take the value "L” at this time.
  • the clock signal CLK2 does not rise at this time.
  • Outputs of the adders 3 0 -3 n-1 are stored in the scan flop-flops 22 1 -22 n , respectively.
  • the control signal SELECT is controlled to take the value "H” at rises of the clock signal CLK1 thereafter.
  • the data stored in the scan flip-flops 22 1 -22 n can be sequentially read out as the scan-out signal SOUT as the clock signal CLK1 further rises j ⁇ n times. Independently of it, the data transmitted through the shift registers 8 0 -8 n-1 can be read as the coefficient output COEFOUT as the clock signal CLK2 further rises n times. Similarly to the storage of the test data, the coefficient output COEFOUT can be read while the scan-out signal SOUT is being read.
  • Comparison of the scan-out signal SOUT and the coefficient output COEFOUT with certain expected values allows determination as to whether operation results of the multiply-accumulation operation units 7 i and the shift registers 8 i are good or bad.
  • data which takes the same values for every j bits is provided as the scan-in signal SIN and data which takes the same values for every k bits is provided as the test data as the coefficient.
  • the third preferred embodiment provides the effect of realizing the test with simpler structure having reduced circuit scale because part of the scan flip-flops are replaced by the shift registers. Furthermore, the scan path is shortened and conditions of the shift registers 8 i for holding the coefficient C i can be determined independently of determination of conditions of the scan flop-flops 22 i using the coefficient output COEFOUT, and also the times required to store the test data and read the data subject to test can be reduced.
  • the scan flip-flop 22 0 can be omitted in the multiply-accumulation operation unit 7 0 on the first stage as has been stated in the first preferred embodiment.
  • the flow of the scan path can be opposite to the direction shown in FIG. 5.
  • a second invention of this application relates to technique which allows a test with a reduced number of test vectors without using scan registers.
  • FIG. 7 is a block diagram showing the structure of a digital filter 104 according to this preferred embodiment.
  • the scan registers 21 0 , 22 0 in the multiply-accumulation operation unit 4 0 are replaced by shift register 8 0 which makes input/output with k bits and hold data with k bits and shift register 9 0 which makes input/output with j bits and hold data with j bits, respectively.
  • the scan register 21 s in the multiply-accumulation operation unit 4 s is replaced by a 2-input 1-output selector 11 s and a shift register 8 s making input/output with k bits and holding data with k bits
  • the scan register 22 s is replaced by a 2-input 1-output selector 12 s and a shift register 9 s making input/output with k bits and holding data with k bits.
  • the input of the shift register 8 0 of the multiply-accumulation operation unit 10 0 on the first stage receives data k bits at a time from the coefficient input COEF.
  • the k-bit data from the coefficient input COEF are received at the second input ends of the selectors 11 s in common.
  • the selector 11 s selectively outputs the data applied to its first input end and second input end to the shift register 8 s in response to "L", "H" of the control signal SELECT.
  • the shift register 8 i transmits its hold value to the multiplier 2 i and to the next stage in synchronization with the clock signal CLK2.
  • Output of the shift register 8 n-1 of the multiply-accumulation operation unit 10 n-1 in the final stage is subjected to a test as a coefficient output COEFOUT, as will be described later.
  • the input of the shift register 9 0 of the first stage multiply-accumulation operation unit 10 0 receives data by j bits from the second data input DATA2.
  • the selectors 12 s receive the j-bit data in common at their respective second input ends from the second data input DATA2.
  • the selector 12 s selectively outputs the data applied to its first input end and second input end to the shift register 9 s according to the control signal SELECT taking "L", "H”.
  • the shift register 9 i transfers its hold value to the adder 3 i in synchronization with the clock signal CLK1.
  • the output of the adder 3 n-1 of the final stage multiply-accumulation operation unit 10 n-1 via the shift register 9 n operating in synchronization with the clock signal CLK1 functions as an output DOUT which serves both as a normal operation filter processing result and as an object of test as will be described later.
  • the digital filter 104 configured as stated above performs normal operation and test operation as follows.
  • control signal SELECT is set to "L" and the selectors 11 s and 12 s function to output the data given to their respective first input ends.
  • coefficients C n-1 , . . . , C 1 , C 0 are provided sequentially by k-bit to the shift register 8 0 from the coefficient input COEF. These coefficients are sequentially transmitted through the shift registers 8 0 , 8 1 . . . , 8 n-1 in synchronization with the clock signal CLK2 so that the shift registers 8 0 , 8 1 , . . . , 8 n-1 can store the coefficients C 0 , C 1 , . . . , C n-1 respectively.
  • each multiply-accumulation operation unit 10 i multiplication of the coefficient C i and the first data input DATA1 is made in the multiplier 2 i and its result is provided as one input to the adder 3 i .
  • the clock signal CLK2 is stopped and transition of the clock signal CLK1 is started, and then, in each multiply-accumulation operation unit 10 s , the output of the adder 3 s-1 of the previous stage multiply-accumulation operation unit 10 s-1 is provided as the other input of the adder 3 s through the selector 12 s and the shift register 9 s .
  • the second data input DATA2 is provided as the other input to the adder 3 0 of the first stage multiply-accumulation operation unit 10 0 via the shift register 9 0 .
  • the clock signal CLK1 continuously makes transitions, and the output DOUT of the digital filter 104 is thus finally obtained similarly to the first preferred embodiment.
  • FIG. 8 is a timing chart showing waveforms of the clock signals CLK1, CLK2, the control signal SELECT, and the output DOUT in test operation of the digital filter 104.
  • test data C1 of k-bit is provided from the coefficient input COEF and test data D2 of j-bit is provided as the second data input DATA2, respectively. This allows the test data C1 to be applied to the shift register 8 i and the test data D2 to be applied to the shift register 9 i prior to the first rises of the clock signals CLK1 and CLK2.
  • the first rises of the clock signals CLK1, CLK2 cause the test data C1 applied to the shift register 8 i to be transmitted to the multiplier 2 i and the test data D2 applied to the shift register 9 i to be transmitted to the adder 3 i .
  • an operation result of the multiply-accumulation operation unit 10 i is obtained as an output of the adder 3 i with j bits of (C1 ⁇ D1+D2).
  • the control signal SELECT makes a transition to "H” before only the clock signal CLK1 rises (at this time, the first data input DATAL is at "0") and the selectors 12 1 -12 n-1 output the data applied to their respective second input ends to the shift registers 9 1 -9 n-1 .
  • the clock signal CLK1 rises alone under such a condition, the operation results of the multiply-accumulation operation units 10 i are outputted from the shift registers 9 1 -9 n . That is, one of j-bit data is obtained as the output DOUT from the shift register 9 n .
  • the clock signals CLK1, CLK2 are both caused to make transitions (n-1) times and n data C1 of k-bit and n data of j-bit are thus obtained as the coefficient output COEFOUT and the output DOUT, respectively. It is desirable to set the first data input DATA1 to "0" so that information of the output DOUT is not hurt.
  • the coefficient output COEFOUT and the output DOUT thus obtained repeat the same data of k-bit and j-bit for each clock, respectively, if the digital filter 104 normally operates. Hence, it is possible to determine whether the digital filter 104 is good or bad by examining the data.
  • the same effects as the first preferred embodiment are obtained. Furthermore, it is possible to determine whether the shift register 8 i for holding the coefficient C i is good or bad using the coefficient output COEFOUT apart from the determination as to whether the shift register 9 i is good or bad. Moreover, times required to store the test data and read data subjected to test can be reduced.
  • the test data can be stored with 1 clock and the output DOUT can be read with n clocks as well as the coefficient output COEFOUT.
  • the determination of condition is made using the output DOUT also in test operation, which depends on whether the value is the same for every j-bit or not. Whether the same value is obtained for every j-bit can be observed by comparing the output DOUT outputted for every j-bit with values outputted before or after it.
  • FIG. 9 is a block diagram showing the structure of a digital filter 105 according to this preferred embodiment.
  • the digital filter 105 includes the digital filter 104, a demultiplexer 19 receiving the output DOUT of the digital filter 104 and processing j-bit data with 1 input and 2 outputs, flip-flops 20a, 20b respectively receiving two j-bit outputs of the demultiplexer 19 and an EXOR gate 13 for obtaining an exclusive OR of the two outputs of the flip-flops 20a, 20b.
  • FIG. 10 is a circuit diagram showing an example of the structure of the demultiplexer 19, which includes an inverter INV3 receiving the output DOUT, two transmission gates T1, T2 receiving output of the inverter INV3, and inverters INV1, INV2 receiving respective outputs of the transmission gates T1, T2 for outputting respective data MUXa, MUXb.
  • the transmission gates T1, T2 complementarily open and close with complementary clock signals ⁇ , ⁇ . While FIG. 10 shows the structure only for one bit, a plurality thereof are provided for j bits to be used in FIG. 9.
  • FIG. 11 is a timing chart showing the interrelation among the clock signals CLK1, ⁇ , the data MUXa, MUXb and outputs of the flip-flops 20a, 20b.
  • the clock signal ⁇ has its period two times that of the clock signal CLK1 without phase shift. Such a clock signal ⁇ can be obtained easily by dividing the clock signal CLK1.
  • Transition of the clock signal ⁇ to "H” causes the transmission gate T1 to become conductive and the transmission gate T2 to become non-conductive and the value d1 of the output DOUT outputted in synchronization with the "H” of the clock signal CLK1 shown by 1 is outputted as the data MUXa.
  • the transition of the clock signal ⁇ to “L” causes the transmission gate T2 to become conductive and the transmission gate T1 to become non-conductive and the value d2 of the output DOUT outputted in synchronization with the "H” of the clock signal CLK1 shown by 2 is outputted as the data MUXb.
  • Making the flip-flops 20a, 20b operate respectively in synchronization with falls of the clock signal ⁇ (rises of the clock signal ⁇ ) and in synchronization with rises of the clock signal ⁇ allows the values d1, d2, d3, . . . to be held for one period of the clock signal ⁇ , i.e., for two periods of the clock signal CLK1.
  • Evaluating the output DOUT in this way makes it possible to determine whether the digital filter 104 is good or bad without requiring a large-scaled test device and test vectors.
  • a digital filter which outputs the same value for every j-bit in test results when it is normal can be used instead of the digital filter 104 in this preferred embodiment.
  • the demultiplexer 19 it is not essential to incorporate the demultiplexer 19, the flip-flops 20a, 20b and the EXOR gate 13 as a part of the digital filter like the digital filter 105, but these components may be provided separately from the digital filter 104.

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US6101517A (en) * 1995-11-09 2000-08-08 Siemens Aktiengesellschaft Circuit and method for the multiple use of a digital transversal filter
EP1085334A2 (de) * 1999-07-21 2001-03-21 Infineon Technologies AG Prüfanordnung und Verfahren zum Testen eines digitalen elektronischen Filters
US6275081B1 (en) * 1999-06-02 2001-08-14 Adaptec, Inc. Gated clock flip-flops
US6393592B1 (en) * 1999-05-21 2002-05-21 Adaptec, Inc. Scan flop circuitry and methods for making the same
US20030014460A1 (en) * 2000-12-07 2003-01-16 Yukio Koyanagi Analog filter
US20030027120A1 (en) * 2001-08-02 2003-02-06 Charles Jean System and apparatus for a karaoke entertainment center
US6581081B1 (en) * 2000-01-24 2003-06-17 3Com Corporation Adaptive size filter for efficient computation of wavelet packet trees
US6938063B2 (en) * 2000-07-29 2005-08-30 Micronas Gmbh Programmable filter architecture
US7080108B1 (en) * 1999-11-02 2006-07-18 Intel Corporation Discrete filter having a tap selection circuit
US20060190520A1 (en) * 2000-12-07 2006-08-24 Yasue Sakai Analog filter

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JPH04266281A (ja) * 1991-02-21 1992-09-22 Seiko Epson Corp 内挿用デジタルフィルタのハードウェア構成
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JPH03196712A (ja) * 1989-12-26 1991-08-28 Sony Corp ディジタル演算回路
JPH04266281A (ja) * 1991-02-21 1992-09-22 Seiko Epson Corp 内挿用デジタルフィルタのハードウェア構成
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6101517A (en) * 1995-11-09 2000-08-08 Siemens Aktiengesellschaft Circuit and method for the multiple use of a digital transversal filter
US6393592B1 (en) * 1999-05-21 2002-05-21 Adaptec, Inc. Scan flop circuitry and methods for making the same
US6275081B1 (en) * 1999-06-02 2001-08-14 Adaptec, Inc. Gated clock flip-flops
EP1085334A2 (de) * 1999-07-21 2001-03-21 Infineon Technologies AG Prüfanordnung und Verfahren zum Testen eines digitalen elektronischen Filters
EP1085334A3 (de) * 1999-07-21 2002-01-16 Infineon Technologies AG Prüfanordnung und Verfahren zum Testen eines digitalen elektronischen Filters
US7080108B1 (en) * 1999-11-02 2006-07-18 Intel Corporation Discrete filter having a tap selection circuit
US6581081B1 (en) * 2000-01-24 2003-06-17 3Com Corporation Adaptive size filter for efficient computation of wavelet packet trees
US6938063B2 (en) * 2000-07-29 2005-08-30 Micronas Gmbh Programmable filter architecture
US20030014460A1 (en) * 2000-12-07 2003-01-16 Yukio Koyanagi Analog filter
US7085799B2 (en) * 2000-12-07 2006-08-01 Yasue Sakai Analog filter suitable for smoothing a ΔΣ-modulated signal
US20060190520A1 (en) * 2000-12-07 2006-08-24 Yasue Sakai Analog filter
US20030027120A1 (en) * 2001-08-02 2003-02-06 Charles Jean System and apparatus for a karaoke entertainment center

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JPH09307403A (ja) 1997-11-28
DE19701779A1 (de) 1997-11-20
KR970077987A (ko) 1997-12-12
KR100188819B1 (ko) 1999-06-01
DE19701779C2 (de) 2000-10-05

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