US5166670A - Column electrode driving circuit for a display apparatus - Google Patents

Column electrode driving circuit for a display apparatus Download PDF

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Publication number
US5166670A
US5166670A US07/634,591 US63459190A US5166670A US 5166670 A US5166670 A US 5166670A US 63459190 A US63459190 A US 63459190A US 5166670 A US5166670 A US 5166670A
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United States
Prior art keywords
column electrode
electrode driving
signal
driving circuit
allocated
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Expired - Lifetime
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US07/634,591
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English (en)
Inventor
Shiro Takeda
Takafumi Kawaguchi
Makoto Takeda
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Sharp Corp
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Sharp Corp
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Assigned to SHARP KABUSHIKI KAISHA reassignment SHARP KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: KAWAGUCHI, TAKAFUMI, TAKEDA, MAKOTO, TAKEDA, SHIRO
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning

Definitions

  • This invention relates to a column electrode driving circuit for a display apparatus, and more particularly to a column electrode driving circuit for a matrix type display apparatus.
  • FIG. 6 As a typical example of a matrix type display device, a matrix type liquid crystal display (LCD) apparatus is shown in FIG. 6.
  • the LCD apparatus of FIG. 6 comprises an LCD panel 61 having: a plurality of row electrodes 61a which are disposed on a substrate parallel to one another; and a plurality of column electrodes 61b which intersect the row electrodes 61a.
  • a picture element (pixel) electrode 61c and a thin film transistor. (TFT) 61d which functions as a switching element, pair is disposed at each crossing of the row electrodes 61a and the column electrodes 61b.
  • the LCD panel 61 is driven by a row electrode driving circuit 62 and column electrode driving circuit 63.
  • the row electrode driving circuit 62 produces scanning pulses which are in turn supplied to the row electrodes 61a to sequentially turn on each row of the switching transistors 61d.
  • the column electrode driving circuit 63 produces voltage signals which are applied to the pixel electrodes 61c through the column electrodes 61b.
  • a control circuit 64 controls the operations of the row electrode driving circuit 62 and the column electrode driving circuit 63.
  • the column electrode driving circuit 63 comprises a shift register circuit 71, a sample and hold circuit 72, and a buffer circuit 73.
  • the shift register circuit 71 shifts a sample signal D in accordance with clock pulses ⁇ and sequentially outputs the sample signal to lines q 1 , q 2 , . . . , q n .
  • the sample and hold circuit 72 samples and holds a video signal V in accordance with sample signals output to the lines q 1 , q 2 , . . . , q n .
  • the buffer circuit 73 simulataneously outputs the voltage signals held in the sample and hold circuit 72 to the column electrodes 61b, as voltage signals Q 1 , Q 2 , . . . , Q n , at the time when an output timing signal T is input.
  • sample signals are sequentially output to the lines q 1 , q 2 , . . . , q j , . . . from the shift register circuit 71.
  • the sample and hold circuit 72 samples instantaneous voltages V i1 , . . . , V ij , . . . of the video signal V in accordance with these sample signals.
  • the output timing signal T is input, and the buffer circuit 73 operates.
  • the column electrode driving circuit 63 is usually comprised of a plurality of partial column electrode driving circuits 90, each corresponding to a portion of the column electrodes 61b, as shown in FIG. 9.
  • Each of the partial column electrode driving circuits 90 is integrated in one LSI chip, and is provided with a shift register circuit 91, a sample and hold circuit 92, and a buffer circuit 93.
  • the shift register circuit 91, sample and hold circuit 92 and buffer circuit 93 may have the same structure as the shift register circuit 71, sample and hold circuit 72 and buffer circuit 73, respectively, except that the number of column electrodes to drive is different.
  • counter measures can be considered such as digital signals, which undergo changes in level, being used as little as possible within the column electrode drive circuit during the period when sampling is performed.
  • a circuit for eliminating the high frequency components of the signal can be provided in a location as close as possible to the supply terminal of the digital signal for the column electrode driving circuit.
  • the column electrode driving circuit of this invention which overcomes the above-discussed and numerous other disadvantages and deficiencies of the prior art, comprises a plurality of partial column electrode driving circuits which respectively drive groups of column electrodes of said display apparatus.
  • Each of said partial column electrode driving circuits is allocated with a number, and comprises: shift register means for shifting a sample signal to sequentially output said sample signal from a plurality of outputs, the shifting direction being changeable in accordance with a shift direction control signal; count means for counting clock pulses, and for producing a count signal at each time when a predetermined number of clock pulses have been counted; switch means for, when said shift direction is set to a first direction, producing a signal indicating said allocated number, and for, when said shift direction is set to a second direction which is opposite to said first direction, producing a signal indicating a number which is obtained by subtracting said allocated number from a specified number; sample signal output means for, when said number output from said switch means and the number of said count signals satisfy a predetermined relationship, outputting said
  • said display apparatus is a matrix type liquid crystal display apparatus.
  • the predetermined number of clock pulses is equal to the number of steps of said shift register means.
  • the allocated number of one of the partial column electrode driving circuits corresponding to the position of said partial column electrode driving circuit in the arrangement of the partial column electrode driving circuits.
  • the specified number relates to the number of the partial column electrode driving circuits.
  • FIG. 1 is a block diagram illustrating a partial column electrode driving circuit used in a column electrode driving circuit according to the invention.
  • FIG. 2 is a block diagram illustrating the column electrode driving circuit according to the invention.
  • FIGS. 3 and 4 are timing charts illustrating the operation of the column electrode driving circuit of FIG. 2.
  • FIG. 5 is a circuit diagram of the partial column electrode driving circuit of FIG. 1.
  • FIG. 6 diagrammatically illustrates an LCD apparatus.
  • FIG. 7 is a block diagram illustrating a column electrode driving circuit of the prior art.
  • FIG. 8 is a timing chart illustrating the operation of a partial column electrode driving circuit used in the circuit of FIG. 7.
  • FIG. 9 is a block diagram illustrating partial column electrode driving circuit used in the circuit of FIG. 7.
  • FIG. 2 illustrates a column electrode driving circuit according to the invention.
  • the circuit of FIG. 2 can drive the LCD apparatus shown in FIG. 6, and includes four partial column electrode driving circuits 10, each of which corresponds to k number of column electrodes in the LCD apparatus.
  • the number of partial column electrode driving circuits 10, and the number of column electrodes which correspond to one of the partial column electrode driving circuit 10 are not restricted to the above, and can be selected arbitrarily.
  • Each of the partial column electrode driving circuits 10 is integrated into one LSI chip, and includes a shift register circuit 11, a sample and hold circuit 12, a buffer circuit 13 and a shift register control circuit 14.
  • Clock pulses ⁇ and shift direction control signal R/L are commonly supplied to the shift register circuits 11 and shift register control circuits 14 in all of the partial column electrode driving circuits 10.
  • a start signal S is further supplied to the shift register control circuits 14.
  • a video signal V and an output timing signal T are input respectively to the sample and hold circuits 12 and buffer circuits 13 in the partial column electrode driving circuits 10.
  • FIG. 1 shows one of the partial column electrode driving circuits 10 in more detail.
  • the sample and hold circuit 12 and buffer circuit 13 are constructed in the same manner as those used in the prior art.
  • the shift register circuit 11 is structured so that the shift direction reverses in response to the shift direction control signal R/L.
  • the shift direction control signal R/L is right (R)
  • the shifting operation toward the right (normal shifting) is performed, and the sample signals are sequentially output from the lines q 1 , q 2 , . . . , in this order.
  • the shift direction control signal R/L is left (L)
  • the shifting operation toward the left (reverse shifting) is performed, and the sample signals are sequentially output from the lines q k , q k-1 , . . . , in this order.
  • the sample signal D which is input to the shift register circuit 11, is supplied from outside of the partial column electrode driving circuit 10.
  • the sample signal D is generated by the shift register control circuit 14.
  • the shift register control circuit 14 includes a count circuit 15, a timing selection circuit 16, and a switching circuit 17.
  • the count circuit 15 supplies a count signal C to the timing selection circuit 16 immediately after receiving the start signal S, and every time k clock pulses ⁇ (k is the number of steps in the shift register circuit 11) are counted after the input of the start signal S.
  • the switching circuit 17 supplies externally established data l, when the shift direction control signal R/L is R, and data (n-1-l), when the shift direction control signal R/L is L, to the timing selection circuit 16.
  • l is a value assigned to each of the partial column electrode driving circuits 10, based upon the arrangement order in which the partial column electrode driving circuits 10 are disposed.
  • Data supplied from the switching circuit 17 to the timing selection circuit 16 is indicated by l' in FIG. 1.
  • l' l
  • l' (n-1-l).
  • the timing selection circuit 16 outputs the sample signal D to the shift register circuit 11 when the number of count signals C which have been input is equal to, l'. wherein the first count signal produced upon receipt of the start signal S is equal to the zeroth count signal and the next count signal output is equal to the first.
  • FIG. 3 is the timing chart for a case in which the shift direction control signal R/l is R.
  • the count circuit 15 Immediately after receiving the start signal S ((b) of FIG. 3) which directs the commencement of the sampling operation, the count circuit 15 generates one count signal C ((c) of FIG. 3). Following this, one count signal C is generated every time k number of clock pulses ⁇ ((a) of FIG. 3) are input.
  • the time interval t k for generating the count signal C is equal to the period of time required for shifting the sample signal D through all of the steps of the shift register circuit 11.
  • subscripts 0 to 3 are added to the sample signal D in accordance with the values (0 to 3) of the data l which are assigned to the partial column electrode driving circuits 10, in the same way as in FIG. 2.
  • the shift register control circuit 14 can generate the sample signal D which is directed to the shift register circuit 11 within the same partial column electrode driving circuit 10, with proper timing based upon the data l.
  • the sample signals D 1 , d 2 and D 3 are generated with the same timing as the digital signals transmitted between partial column electrode driving circuits in the prior art. Therefore, the digital signals which are transmitted between the partical column electrode driving circuits in a column electrode driving circuit of the prior art are not necessary, and thus it is possible to avoid image disturbance due to noises from the digital signals.
  • the level of the start signal S changes outside of the sampling period, and the start signal S can be generated outside of the LSI which contains the partial column electrode driving circuit 10. Hence, it is possible to easily add a circuit as a noise countermeasure, so that the start signal S does not become a source of image disturbance.
  • FIG. 4 illustrates the operation of this embodiment in the case where the shift direction control signal R/L is L.
  • a circuit diagram of the shift register control circuit 14 is shown in FIG. 5.
  • the value K is set to 64
  • data l is expressed with two bits (l 1 , l 0 ).
  • the shift direction control signal R/L is R
  • it has the value of "0”.
  • the shift direction control signal R/L is L
  • it has the value of "1”.
  • the count signal C which is generated immediately after the input of the start signal S is output from a D flip-flop 152.
  • a 1/64 counter 151 counts the clock pulses ⁇ .
  • the count signal C is output from an OR gate 154 as the count signal C.
  • the count signal C which is output from the OR gate 154 is counted by a 1/4 counter 161.
  • the count signal C is output from the D flip-flop 152 or the OR gate 154, it is determined by the combination or NOR gates 162-165 whether or not the data l' expressed by two bits (l' 1 , l' 0 ) and supplied from the switching circuit 17 coincide with the output of the 1/4 counter 161. IF yes, the sample signal D is output from an OR gate 166.
  • the sequence of driving column electrodes in a display apparatus can be easily reversed by controlling the shift direction control signal.
US07/634,591 1989-12-27 1990-12-27 Column electrode driving circuit for a display apparatus Expired - Lifetime US5166670A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1342119A JPH03198087A (ja) 1989-12-27 1989-12-27 表示装置の列電極駆動回路
JP1-342119 1989-12-27

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US07/634,591 Expired - Lifetime US5166670A (en) 1989-12-27 1990-12-27 Column electrode driving circuit for a display apparatus

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US (1) US5166670A (de)
EP (1) EP0435661B1 (de)
JP (1) JPH03198087A (de)
KR (1) KR940003425B1 (de)
DE (1) DE69021533T2 (de)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418547A (en) * 1993-02-22 1995-05-23 Sharp Kabushiki Kaisha Driving circuit for display devices
US5682176A (en) * 1993-12-28 1997-10-28 International Business Machines Corporation Apparatus and method for driving liquid crystal
US6025835A (en) * 1995-05-15 2000-02-15 Kabushiki Kaisha Toshiba Driving circuit for display apparatus with paired sample-hold circuits sampling positive and negative phase picture signal components for column electrode driving
US6049320A (en) * 1996-07-27 2000-04-11 Lg Electronics Inc. Data driver for use in liquid crystal display
US6061046A (en) * 1996-09-16 2000-05-09 Lg Semicon Co., Ltd. LCD panel driving circuit
US6075510A (en) * 1997-10-28 2000-06-13 Nortel Networks Corporation Low power refreshing (smart display multiplexing)
US6177920B1 (en) * 1994-10-03 2001-01-23 Semiconductor Energy Laboratory Co., Ltd. Active matrix display with synchronous up/down counter and address decoder used to change the forward or backward direction of selecting the signal or scanning lines
US6292162B1 (en) * 1996-06-07 2001-09-18 Nec Corporation Driving circuit capable of making a liquid crystal display panel display and expanded picture without special signal processor
US6657622B2 (en) * 2000-07-18 2003-12-02 Samsung Electronics Co., Ltd. Flat panel display with an enhanced data transmission
CN100369075C (zh) * 2002-09-27 2008-02-13 三洋电机株式会社 信号传输电路和显示设备

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04168477A (ja) * 1990-10-31 1992-06-16 Sharp Corp 表示装置の行電極駆動回路
FR2872331B1 (fr) * 2004-06-25 2006-10-27 Centre Nat Rech Scient Cnrse Echantillonneur analogique rapide pour enregistrement et lecture continus et systeme de conversion numerique

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3348069A (en) * 1965-05-07 1967-10-17 Fabri Tek Inc Reversible shift register with simultaneous reception and transfer of information byeach stage
US3378876A (en) * 1965-08-23 1968-04-23 Procter & Gamble Adjustable doctor blade assembly for yankee dryers and like machines
JPS5368514A (en) * 1976-11-30 1978-06-19 Matsushita Electric Ind Co Ltd Driving system for matrix panel
US4365242A (en) * 1980-02-25 1982-12-21 Sharp Kabushiki Kaisha Driving technique for matrix liquid crystal display panel for displaying characters and a cursor
US4799057A (en) * 1984-07-23 1989-01-17 Sharp Kabushiki Kaisha Circuit for driving a matrix display device with a plurality of isolated driving blocks
US4801933A (en) * 1985-03-23 1989-01-31 Sharp Kabushiki Kaisha Liquid crystal matrix device having separate driving circuits with diverse driving voltages
US4825202A (en) * 1985-09-16 1989-04-25 Commissariat A L'energie Atomique Control means for an integrated memory matrix display and its control process
JPH01150197A (ja) * 1987-12-07 1989-06-13 Sharp Corp マトリクス型液晶表示装置の列電極駆動回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875195A (ja) * 1981-10-29 1983-05-06 株式会社東芝 表示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3348069A (en) * 1965-05-07 1967-10-17 Fabri Tek Inc Reversible shift register with simultaneous reception and transfer of information byeach stage
US3378876A (en) * 1965-08-23 1968-04-23 Procter & Gamble Adjustable doctor blade assembly for yankee dryers and like machines
JPS5368514A (en) * 1976-11-30 1978-06-19 Matsushita Electric Ind Co Ltd Driving system for matrix panel
US4365242A (en) * 1980-02-25 1982-12-21 Sharp Kabushiki Kaisha Driving technique for matrix liquid crystal display panel for displaying characters and a cursor
US4799057A (en) * 1984-07-23 1989-01-17 Sharp Kabushiki Kaisha Circuit for driving a matrix display device with a plurality of isolated driving blocks
US4801933A (en) * 1985-03-23 1989-01-31 Sharp Kabushiki Kaisha Liquid crystal matrix device having separate driving circuits with diverse driving voltages
US4825202A (en) * 1985-09-16 1989-04-25 Commissariat A L'energie Atomique Control means for an integrated memory matrix display and its control process
JPH01150197A (ja) * 1987-12-07 1989-06-13 Sharp Corp マトリクス型液晶表示装置の列電極駆動回路

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418547A (en) * 1993-02-22 1995-05-23 Sharp Kabushiki Kaisha Driving circuit for display devices
US5682176A (en) * 1993-12-28 1997-10-28 International Business Machines Corporation Apparatus and method for driving liquid crystal
US6177920B1 (en) * 1994-10-03 2001-01-23 Semiconductor Energy Laboratory Co., Ltd. Active matrix display with synchronous up/down counter and address decoder used to change the forward or backward direction of selecting the signal or scanning lines
US6025835A (en) * 1995-05-15 2000-02-15 Kabushiki Kaisha Toshiba Driving circuit for display apparatus with paired sample-hold circuits sampling positive and negative phase picture signal components for column electrode driving
US6292162B1 (en) * 1996-06-07 2001-09-18 Nec Corporation Driving circuit capable of making a liquid crystal display panel display and expanded picture without special signal processor
US6049320A (en) * 1996-07-27 2000-04-11 Lg Electronics Inc. Data driver for use in liquid crystal display
US6489943B1 (en) 1996-07-27 2002-12-03 Lg Electronics Inc. Data driver for use in liquid crystal display
US6061046A (en) * 1996-09-16 2000-05-09 Lg Semicon Co., Ltd. LCD panel driving circuit
US6075510A (en) * 1997-10-28 2000-06-13 Nortel Networks Corporation Low power refreshing (smart display multiplexing)
US6657622B2 (en) * 2000-07-18 2003-12-02 Samsung Electronics Co., Ltd. Flat panel display with an enhanced data transmission
CN100369075C (zh) * 2002-09-27 2008-02-13 三洋电机株式会社 信号传输电路和显示设备

Also Published As

Publication number Publication date
KR940003425B1 (ko) 1994-04-22
DE69021533D1 (de) 1995-09-14
DE69021533T2 (de) 1996-02-22
JPH03198087A (ja) 1991-08-29
EP0435661B1 (de) 1995-08-09
EP0435661A2 (de) 1991-07-03
EP0435661A3 (en) 1992-10-14
KR910013038A (ko) 1991-08-08

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