EP0544427A2 - Steuerschaltung für eine Anzeigeeinheit mit digitaler Sourcesteuerung zur Erzeugung von Mehrfachpegelsteuerspannungen aus einer einzelnen externen Energiequelle - Google Patents

Steuerschaltung für eine Anzeigeeinheit mit digitaler Sourcesteuerung zur Erzeugung von Mehrfachpegelsteuerspannungen aus einer einzelnen externen Energiequelle Download PDF

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Publication number
EP0544427A2
EP0544427A2 EP92310381A EP92310381A EP0544427A2 EP 0544427 A2 EP0544427 A2 EP 0544427A2 EP 92310381 A EP92310381 A EP 92310381A EP 92310381 A EP92310381 A EP 92310381A EP 0544427 A2 EP0544427 A2 EP 0544427A2
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European Patent Office
Prior art keywords
voltage
signal
circuit
output
external power
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Application number
EP92310381A
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English (en)
French (fr)
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EP0544427B1 (de
EP0544427A3 (en
Inventor
Kaoru Nakanishi
Kouichirou Seihara
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Sharp Corp
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Sharp Corp
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Publication of EP0544427A3 publication Critical patent/EP0544427A3/en
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Publication of EP0544427B1 publication Critical patent/EP0544427B1/de
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present invention relates to a display module drive circuit having a gate driver and a source driver, and more particularly to a digital source driver for outputting multi-level drive voltages for display of a multi-density-level image based on an input digital video signal of a specified number of bits.
  • Fig. 13 schematically shows a conventional matrix type liquid crystal display module.
  • the matrix type liquid crystal display module employs a TFT (Thin Film Transistor) as a switching element for driving pixel electrodes.
  • a TFT liquid crystal display panel 300 includes m signal electrodes 302 (Nos. O1 through Om) arranged in parallel with each other and i scanning electrodes 301 (Nos. 1 through i) arranged in parallel with each other and perpendicularly to the signal electrodes 302.
  • a TFT 304 In proximity to the intersecting point between each scanning electrode 301 and each signal electrode 302 is provided a TFT 304 for driving a corresponding pixel electrode 303.
  • One horizontal scanning line is composed of m pixel electrodes 303 connected to one scanning electrode 301.
  • the TFT liquid crystal panel 300 is driven by an LCD module drive circuit 200 including a source driver 201 and a gate driver 202.
  • the source driver 201 and the gate driver 202 are connected respectively to the signal electrodes 302 and the scanning electrodes 301.
  • the source driver 201 samples and holds an input digital image signal or a video signal to supply the signal to the signal electrodes 302.
  • the gate driver 202 successively outputs scanning pulses to the scanning electrodes 301.
  • the gate driver 202 and the source driver 201 receive control signals such as a clock signal from a control circuit 203.
  • An external power voltage generating circuit 204 generates a plurality of external power voltages of different levels (for example, eight) from an input power voltage and supplies them to the source driver 201.
  • Fig. 14 shows in detail the construction of the source driver 201 shown in Fig. 13.
  • the source driver 201 includes a shift register 101, a sampling memory 102, a hold memory 103, a decoder 104, and an output voltage selecting circuit 105.
  • the source driver 201 has m signal systems corresponding to the m signal electrodes.
  • Fig. 15 shows the construction of an n th (1 ⁇ n ⁇ m ) signal system of the source driver 201.
  • part belonging to the nth signal system of the output voltage selecting circuit 105 is composed of eight analog switches ASW0 through ASW7.
  • the shift register 101 shown in Figs. 13 and 14 outputs a SAMPLING pulse Tsmpn for the n th pixel.
  • externally input video signals D0, D1, and D2 are taken into the sampling memory 102 and held in three D-flip-flops 121, 122, and 123 belonging to the nth signal system of the sampling memory 102.
  • an OUTPUT pulse OE is input to the hold memory 103.
  • the video signals D0, D1, and D2 held in the sampling memory 102 are transferred to the hold memory 103 (three D-flip-flops 131, 132, and 133) and then to the decoder 104.
  • the decoder 104 decodes the input video signals D0, D1, and D2 and outputs eight enabling signals Y0 through Y7 (only one of these signals is at a high (H) level and the others are at a low (L) level).
  • one of analog switches ASW0 through ASW7 in the output voltage selecting circuit 105 becomes conductive. Therefore, from among the eight external power voltages V0 through V7 transmitted from the external power voltage generating circuit 204 to the output voltage selecting circuit 105, one voltage which has been applied to the analog switch made conductive is output to the signal electrode (source line) On (1 ⁇ n ⁇ m). In this way, the external power voltages V0 through V7 having multiple levels or gradations can be supplied as drive voltages to the TFT liquid crystal panel 300 in accordance with the contents of the video signal D0, D1, and D2.
  • the above-mentioned conventional drive circuit is accompanied by a problem of requiring an increased number of external power voltages which serve as density-scale reference voltages.
  • the object of the present invention is therefore to provide a display module drive circuit having a source driver which solves the above problems and which is capable of supplying multi-level drive voltages corresponding to multiple density levels of an image to be displayed, without increasing the number of the external power sources.
  • the present invention provides a display module drive circuit including a gate driver to be connected with scanning electrodes of a display module for supplying scanning pulses to the scanning electrodes and a source driver to be connected with signal electrodes of the display module for outputting drive voltages of multiple levels for display of an image having multiple density levels to the signal electrodes based on an input digital video signal represented by a specific number of bits
  • the source driver comprising: a timing signal generating circuit for generating a specified number of timing signals having different pulse widths based on clock pulses in each of horizontal periods, the number of the timing signals corresponding to the number of the density levels of the image; a voltage control circuit for, upon receipt of the digital video signal and the timing signals, selecting one of the timing signals based on the contents of the digital video signal in each horizontal period to output a control signal at a specified level for a time corresponding to the pulse width of the selected timing signal; and an output voltage generating circuit for generating a drive voltage, including a capacitor and first switch means, said capacitor receiving an input digital video signal represented by
  • the source driver in the display module drive circuit in accordance with an embodiment of the present invention operates as follows. First, the timing signal generating circuit generates the timing signals having different pulse widths in each horizontal period. The number of the timing signals (for example, 8) depends on the density levels of the image to be displayed. One of the timing signals is always held at a H level. Then the voltage control circuit receives video signals and the timing signals and selects one of the timing signals based on the contents of the video signals in each horizontal period. Fig. 9 shows an example of selection of the timing signal for generation of the control signal. As shown in Fig. 9, when the video signals indicated by D0, D1, and D2 represent the levels L, L, and L respectively, the timing signal T0 is selected.
  • the timing signal T1 When the video signals D0, D1, and D2 represent the levels H, L, and L respectively, the timing signal T1 is selected. When the video signals D0, D1, and D2 represent the levels H, H, and H respectively, the timing signal T7 is selected. Then the voltage control circuit outputs a control signal at a high level for a period corresponding to the pulse width of the selected timing signal.
  • the capacitor receives the external power voltage from an external power source through the first switch means during the time when the control signal is output in each horizontal period so that a drive voltage is generated in each horizontal period.
  • the level of the drive voltage is controllable in accordance with the pulse width of the selected timing signal so that drive voltages of multiple levels can be generated.
  • the display module drive circuit drive voltages of multiple levels can be generated from a single external power source.
  • the timing signal generating circuit generates an increased number of timing signals according to the amount of gradations.
  • the number of the drive voltages increases accordingly.
  • the above arrangement obviates any increase in number of the external power sources.
  • the multi-level drive voltages can be generated without increasing the external power source. Accordingly, the following advantages are produced.
  • the two capacitors are switched by output-switching signals which are generated by the timing signal generating circuit.
  • the output-switching signals are at opposite levels from each other in their essential parts and respectively inverted every horizontal period.
  • Fig. 1 is a block diagram of a matrix type liquid crystal display module which uses a drive circuit 200 including a gate driver 202 which is the same as that of Fig. 13 and a source driver 7 in accordance with an embodiment of the present invention.
  • a drive circuit 200 including a gate driver 202 which is the same as that of Fig. 13 and a source driver 7 in accordance with an embodiment of the present invention.
  • the same components as those in Fig. 13 showing the conventional matrix type liquid crystal display module are denoted by the same numerals, and no detailed description on those components is provided here.
  • the liquid crystal display module of Fig. 1 has no circuit for generating a plurality of external power voltages of multiple levels such as the external power voltage generating circuit 204 shown in Fig. 13.
  • Fig. 2 shows the construction of the entire source driver 7 shown in Fig. 1.
  • Fig. 3 shows a part processing the n th (1 ⁇ n ⁇ m) one of the m signal groups (each one represented by three bits) of the source driver 7.
  • the m signal groups correspond to the m pixels.
  • the source driver 7 includes a shift register 1, a sampling memory 2, a hold memory 3, a timing signal generating circuit 4, a voltage control circuit 5, and an output voltage generating circuit 6.
  • the shift register 1, sampling memory 2, and hold memory 3 are the same as the shift register 101, sampling memory 102, and hold memory 103 shown in Fig. 13-15 respectively.
  • the timing signal generating circuit 4 is composed of two parts 4A and 4B as shown in Fig. 4.
  • the part 4A is composed of D-flip-flop circuits 41, 42, and 43, an AND circuit 44, a NOR circuit 45, and a NAND circuit 47.
  • the part 4A of the timing signal generating circuit 4 when receiving clock pulses CLK and a pulse signal OE input once a horizontal period, the part 4A of the timing signal generating circuit 4 generates output-switching signals OE1 and OE2, which are at opposite levels from each other in their essential parts and inverted respectively every horizontal period, as well as a clear signal CLR1 obtained by inverting most part of the pulse signal OE.
  • signals OEA and OEB in Fig. 5 are outputs of the D-flip-flop circuits 42 and 43 respectively.
  • the part 4B of the timing signal generating circuit 4 is composed of a 6-bit counter 46, an inverter 48, and D-flip-flop circuits 49 through 55, as shown in Fig. 4.
  • the part 4B When receiving the clock pulses CLK, the part 4B first generates a signal 64 CK representing 64 clock pulses as shown in Fig. 6. Then, eight kinds (corresponding to the number of density levels of an image) of timing signals T0, T1, ..., T7 having different pulse widths are generated in one horizontal period based on the signal 64 CK. (Note that the timing signal T0 is maintained at H level.)
  • the voltage control circuit 5 more specifically part thereof processing the n th signal group shown in Fig. 3, receives video signals HnD0, HnD1, and HnD2 from the hold memory 3, the timing signals T0, T1, ..., T7, and the output-switching signals OE1 and OE2 from the timing signal generating circuit 4. Then the voltage control circuit 5 outputs control signals CON1 and CON2 at specific levels every horizontal period, as shown in Fig. 7, according to the contents of the received signals and output-switching signals.
  • the control signal CON1 is held at H level for a period corresponding to the pulse width of the timing signal T0, T1, ..., or T7 selected according to the contents of the video signals HnD0, HnD1, and HnD2. Meanwhile, the control signal CON2 is maintained at L level, irrespective of the contents of the video signals HnD0, HnD1, and HnD2.
  • the control signal CON1 assumes L level irrespective of the contents of the video signals HnD0, HnD1, and HnD2. Meanwhile, the control signal CON2 is held at H level for a period corresponding to the pulse width of the timing signal T0, T1, ..., or T7 selected according to the contents of the video signals HnD0, HnD1, and HnD2.
  • the control signals CON1 and CON2 are switched to "L” level whatever the contents of the video signals HnD0, HnD1, and HnD2 are. It is noted that there is no case where both the signals OE1 and OE2 represent logic "1" as apparent from Fig. 5.
  • the output voltage generating circuit 6 (more specifically part thereof processing the n th signal group) is composed of wirings L1 and L2 connecting an external power source (voltage V) to a source line (signal electrode) On, capacitors C1 and C2 connected between each of the wirings L1 and L2 and the ground, and analog switches ASW1, ASW2, ASW3, and ASW4.
  • the analog switches ASW1 and ASW3 are arranged on the wiring L1 and on opposite sides of the capacitor C1 toward the external power source and the source line On, respectively.
  • These analog switches ASW1 and ASW3 are turned on and off respectively by the control signal CON1 from the voltage control circuit 5 and the output-switching signal OE2 from the timing signal generating circuit 4 (the switches are turned on when each control signal is at H level and turned off when each control signal is at L level).
  • the analog switches ASW2 and ASW4 are arranged on the wiring L2 and toward the external power source and the source line (signal electrode) On from the capacitor C2, respectively. These switches ASW2 and ASW4 are turned on and off respectively by the control signal CON2 from the voltage control circuit 5 and the output-switching signal OE1 from the timing signal generating circuit 4 (the switches are turned on when each control signal is at H level and turned off when each control signal is at L level).
  • the above-mentioned source driver 7 operates as follows. First, when the shift register 1 outputs a sampling pulse Tsmpn for the n th pixel, the externally input video signals D0, D1, and D2 are taken into the sampling memory 2 at the leading edge of the sampling pulse Tsmpn. Then those sampled video signals are held as video signals SnD0, SnD1, and SnD2 in the three D-flip-flops 21, 22, and 23 of the sampling memory 2 (part processing the n th signal group). When the sampling operation in one horizontal period is completed, the pulse signal OE is input to the hold memory 3.
  • the video signals SnD0, SnD1, and SnD2 held in the sampling memory 2 are received by the hold memory 3 (three D-flip-flops 31, 32, and 33) to be then transferred as video signals HnD0, HnD1, and HnD2 to the voltage control circuit 5.
  • the voltage control circuit 5 outputs the control signal CON1 or CON2 of H level for the period corresponding to the pulse width of the timing signal T0, T1, ..., or T7 selected in each horizontal period based on the contents of the video signals HnD0, HnD1, and HnD2, as described hereinbefore.
  • the output-switching signal OE1 is at H level and the output-switching signal OE2 is at L level in a specified horizontal period.
  • the control signal CON1 is turned to H level and the control signal CON2 is turned to L level. Consequently, in the output voltage generating circuit 6, the analog switches ASW1 and ASW4 are turned on while the analog switches ASW2 and ASW3 are turned off. Therefore, the capacitor C1 is charged with the external power voltage V through the analog switch ASW1 for the period corresponding to the pulse width of the timing signal T0, T1, ..., or T7 selected by the voltage control circuit 5. At this time, by supplying the external power voltage V from an external power source having a potential which gets higher with time as shown in Fig.
  • a drive voltage corresponding to the contents of the video signals D0, D1, and D2 is formed across the electrodes of the capacitor C1.
  • a voltage having been charged to the capacitor C2 in the preceding horizontal period is output therefrom by way of the analog switch ASW4 to the source line (signal electrode) On.
  • the output-switching signals OE1, OE2 serve to determine which of the capacitors C1, C2 should be charged with the external power voltage and which of the voltages charged in the capacitors C1, C2 should be supplied to the source line On.
  • the output-switching signal OE1 is switched to L level and the output-switching signal OE2 is switched to H level.
  • the control signal CON1 is switched to L level and the control signal CON2 is switched to H level.
  • the analog switches ASW1 and ASW4 are turned off while the analog switches ASW2 and ASW3 are turned on in the output voltage generating circuit 6. Therefore, the capacitor C2 is charged with the external power voltage V by way of the analog switch ASW2 for the period corresponding to the pulse width of the timing signal T0, T1, ..., or T7 selected by the voltage control circuit 5.
  • the external power voltage V is supplied from the external power source having a potential which gets higher with time as shown in Fig.
  • a drive voltage of a level corresponding to the contents of the video signals D0, D1, and D2 is formed across the electrodes of the capacitors C2.
  • the voltage (drive voltage) having been charged in the previous horizontal period is output from the capacitor C1 by way of the analog switch ASW3 to the source line On.
  • the other capacitor can output a drive voltage, so that drive voltages of multiple levels are continuously output from the output voltage generating circuit 6.
  • the source driver 7 can generate multi-level drive voltages from only a single external power source.
  • the timing signal generating circuit 4 When increasing the number of bits of the video signal to increase the number of density levels of an image, the timing signal generating circuit 4 generates an increased number of timing signals according to the number of the density levels to enable generation of multi-level drive voltages based on the timing signals. In this way, multi-level drive signals can be offered without increasing the number of the external power sources.
  • the light transmissivity varies in the medium voltage region and is saturated in the low and high voltage regions as shown in Fig. 11. Since digital one bit display system has only the on and off status, a high contrast can be obtained so long as the display panel is driven at voltages in the low and high voltage regions.
  • the characteristic curve (voltage-time characteristic) of the external power voltage shown in Fig. 10 is corrected as shown in Fig. 12 to provide the voltage levels or gradations with a linear characteristic.
  • transmissivity varies in the medium voltage region at the present time as shown in Fig. 11, the transmissivity needs to change in the low voltage region in the future because a liquid crystal display device using a low drive voltage such as 3V, for example, can be used then.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP92310381A 1991-11-27 1992-11-13 Steuerschaltung für eine Anzeigeeinheit mit digitaler Sourcesteuerung zur Erzeugung von Mehrfachpegelsteuerspannungen aus einer einzelnen externen Energiequelle Expired - Lifetime EP0544427B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP312319/91 1991-11-27
JP3312319A JPH05150737A (ja) 1991-11-27 1991-11-27 表示装置用駆動回路

Publications (3)

Publication Number Publication Date
EP0544427A2 true EP0544427A2 (de) 1993-06-02
EP0544427A3 EP0544427A3 (en) 1993-07-21
EP0544427B1 EP0544427B1 (de) 1997-01-15

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EP92310381A Expired - Lifetime EP0544427B1 (de) 1991-11-27 1992-11-13 Steuerschaltung für eine Anzeigeeinheit mit digitaler Sourcesteuerung zur Erzeugung von Mehrfachpegelsteuerspannungen aus einer einzelnen externen Energiequelle

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EP (1) EP0544427B1 (de)
JP (1) JPH05150737A (de)
KR (1) KR960016342B1 (de)
DE (1) DE69216785T2 (de)

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EP0644522A1 (de) * 1993-09-13 1995-03-22 Kabushiki Kaisha Toshiba Datenauswahleinrichtung
EP1041535A1 (de) * 1999-03-30 2000-10-04 EM Microelectronic-Marin SA Anzeigetreiber für Flüssigkristallanzeige mit mindestens einer Farbstufe
US7443371B2 (en) * 2003-06-20 2008-10-28 Seiko Epson Corporation Electro-optic apparatus, driving method for the same, and electronic appliance
CN102842278A (zh) * 2012-08-06 2012-12-26 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示器

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CN115128573B (zh) * 2022-08-30 2022-12-06 北京摩尔芯光半导体技术有限公司 用于光学相控阵的驱动电路、驱动方法及激光雷达装置

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EP0298255A1 (de) * 1987-06-04 1989-01-11 Seiko Epson Corporation Ansteuerschaltung für eine Flüssigkristallanzeige
EP0347720A2 (de) * 1988-06-18 1989-12-27 Hitachi, Ltd. Methode und Vorrichtung für Bildschirm mit Grauwert-Anzeige
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EP0298255A1 (de) * 1987-06-04 1989-01-11 Seiko Epson Corporation Ansteuerschaltung für eine Flüssigkristallanzeige
EP0347720A2 (de) * 1988-06-18 1989-12-27 Hitachi, Ltd. Methode und Vorrichtung für Bildschirm mit Grauwert-Anzeige
EP0417578A2 (de) * 1989-09-11 1991-03-20 Deutsche Thomson-Brandt Gmbh Ansteuerschaltung für eine Flüssigkristallanzeige

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644522A1 (de) * 1993-09-13 1995-03-22 Kabushiki Kaisha Toshiba Datenauswahleinrichtung
US5508715A (en) * 1993-09-13 1996-04-16 Kabushiki Kaisha Toshiba Data selection circuit
EP1041535A1 (de) * 1999-03-30 2000-10-04 EM Microelectronic-Marin SA Anzeigetreiber für Flüssigkristallanzeige mit mindestens einer Farbstufe
US7443371B2 (en) * 2003-06-20 2008-10-28 Seiko Epson Corporation Electro-optic apparatus, driving method for the same, and electronic appliance
CN102842278A (zh) * 2012-08-06 2012-12-26 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示器

Also Published As

Publication number Publication date
DE69216785D1 (de) 1997-02-27
EP0544427B1 (de) 1997-01-15
KR930010837A (ko) 1993-06-23
JPH05150737A (ja) 1993-06-18
EP0544427A3 (en) 1993-07-21
DE69216785T2 (de) 1997-07-24
KR960016342B1 (ko) 1996-12-09

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