EP1041535A1 - Anzeigetreiber für Flüssigkristallanzeige mit mindestens einer Farbstufe - Google Patents

Anzeigetreiber für Flüssigkristallanzeige mit mindestens einer Farbstufe Download PDF

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Publication number
EP1041535A1
EP1041535A1 EP99106457A EP99106457A EP1041535A1 EP 1041535 A1 EP1041535 A1 EP 1041535A1 EP 99106457 A EP99106457 A EP 99106457A EP 99106457 A EP99106457 A EP 99106457A EP 1041535 A1 EP1041535 A1 EP 1041535A1
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EP
European Patent Office
Prior art keywords
control
signal
signals
binary
block
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99106457A
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English (en)
French (fr)
Inventor
Ulrich Maas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EM Microelectronic Marin SA
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EM Microelectronic Marin SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EM Microelectronic Marin SA filed Critical EM Microelectronic Marin SA
Priority to EP99106457A priority Critical patent/EP1041535A1/de
Publication of EP1041535A1 publication Critical patent/EP1041535A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present invention relates to the technical field of devices for control of liquid crystal display (LCD) devices having at least one color level.
  • LCD liquid crystal display
  • a display device with liquid crystal will be designated by the LCD reference (acronym from English “Liquid Crystal Device”).
  • a “level of color” will designate: a color in the case where the LCD device allows display information with one or more colors; and a gray level in the case where the LCD device makes it possible to display information with one or several levels of gray.
  • an LCD device typically includes a matrix row and column electrodes, each of intersections of this matrix being connected to a contact pad intended to be connected to a control device.
  • control device 1 connected to an LCD device 3 of the aforementioned type.
  • the control device 1 includes switching means 5, a control block 9 and connection lines 7.
  • each contact pad is connected, on the one hand, to four electrodes of the LCD device 3 and, on the other hand, to one of the switching means 5 which are themselves connected to the block of command 9, via connection lines 7.
  • the block of control can thus provide a specific voltage to control sequentially the four electrodes, via this switching means, this contact pad and these connection lines.
  • Such a control voltage comprises four phases associated with four electrodes and, for each of the phases, is equal to a high level VON (respectively at a low VOFF level) during an activation period (respectively during a deactivation period).
  • the control device 1 implements the so-called FRC technique (acronym from English "Frame Rate Control”) which is widely known in the prior art, in particular in US patent 5,774,101.
  • FRC Frequency Control
  • This technique consists in carrying out the display of a desired gray level, by providing a control voltage comprising several frames having a predetermined duty cycle, so this voltage has a value VRMS average corresponding to the desired gray level.
  • the number of frames depends on the number of gray levels associated with the LCD device 3.
  • FIG. 2A of this invention the document GB 2.186.414 describes a control block 10 which can provide a command for an LCD device with several gray levels, depending on the FRC technique, and during four multiplexing phases.
  • the block of control 10 includes a counter 11, a pulse generator 13, a memory 15, four doors AND 17, an OR door 19 and a door transmission 18.
  • FIG. 2B of the present description represents 21 timing diagrams of signals associated with the control unit 10.
  • the counter 11 is controlled by a clock signal CLK (shown in Figure 2B) to provide four binary signals Q0 to Q3.
  • CLK shown in Figure 2B
  • the reference T designates a predetermined period corresponding to sixteen clock pulses of the CLK signal, so that sixteen screens are used to display a shade of gray depending on the FRC technique.
  • the pulse generator 13 controlled by the signals Q0 to Q3 for supply four signals P0 to P3 (represented in FIG. 2B) whose ratios cyclic values are equal to T / 16, T / 8, T / 4 and T / 2 respectively.
  • the memory 15 contains digital data converted from analog data representing a gray level, and provides four binary output signals M0 to M3, these four signals can represent sixteen distinct values (represented in FIG. 2B) corresponding to sixteen different gray levels.
  • the AND gates 17 receive, on the one hand, the signals M0 to M3 respectively and, on the other hand, the signals P0 to P3 respectively, and provide signals to the OR gate 19.
  • the latter thus provides a signal output selected from sixteen signals with duty cycles different from each other (as shown in Figure 2B), depending data contained in memory 15.
  • the transmission gate 18 receives VON and VOFF signals and the OR gate output signal 19, and provides a control voltage D equal to VON or VOFF depending on the output signal from the OR gate 19, this voltage D being intended to control the desired display.
  • control unit 10 A disadvantage of the control unit 10 is that it is necessary, for obtain a desired gray level with sufficient resolution, to provide a higher number of frames, which implies that the frequency of the system LCD should be higher. This results in high power consumption electric, which therefore goes against the constraints of certain applications such as low-voltage applications used in particular in the watch industry.
  • control unit 10 Another disadvantage of the control unit 10 is that the supply of an eight-frame control voltage leads to the supply of eight VRMS values which are substantially equidistant from each other. Now the VRMS value of one of the gray levels can be between two values consecutive, so the display of this level requires greater resolution, which leads to increasing the number of frames, that is to say the consumption of electrical power.
  • control block 10 Another disadvantage of the control block 10 is that the value VRMS varies due to temperature. Thus the supply of the voltage of orders with the same duty cycle, but at two temperatures different, does not display the same gray level.
  • control unit 10 Another disadvantage of the control unit 10 is that it is necessary to modify the content of memory 15 at the start of each frame, which implies a additional electrical power consumption.
  • An object of the present invention is to provide a device for control of an LCD device with several color levels, this device overcoming the aforementioned drawbacks, in particular being able to control the display of a gray level causing a low consumption of electric power.
  • Another object of the present invention is to provide such a device control adaptable to an LCD device comprising electrodes in shape of segments and / or symbols.
  • Another object of the present invention is to provide a device for command that can be carried out in a watch application (i.e. a device operating at a voltage of the order of 1.5V).
  • control device is to provide the device LCD with several color levels, a control voltage having a average value equal to the VRMS value of the desired color level display, during a single multiplexing phase, and not after a series of several phases using the classic FRC technique. This results in a significant reduction in electrical power consumption.
  • control device Another advantage of the control device is to provide the display the desired color level with high resolution, the latter can be increased by increasing the number of bits in the memory block, not by increasing the number of frames according to the technique Classic FRC.
  • An advantage of the memory block is to allow the provision of a global definition of color levels, which makes it easy to achieve a change in the level of colors displayed.
  • control block registers In the case the permanent display of an image, the contents of these registers are unchanged over time (and not changed periodically depending on the classic FRC technique). It also results in a reduction in the consumption of electrical power.
  • control block registers For display a new image, just change the contents of these registers to modify the allocations of the color levels to the different electrodes of the LCD device. It results from such modification of the contents of these registers the immediate display of the new image.
  • a control device 30 is intended to control an LCD device 32 comprising at least one color level.
  • the LCD device 32 includes first electrodes and second electrodes (or substrate electrodes) arranged opposite the each other, as is known per se. Note that the command of substrate electrodes of the LCD device 32 is produced in a conventional manner.
  • the LCD device 32 makes it possible to display information with one or four colors (it will be noted that the control device 30 can be adapted for an LCD device with M levels of color, M being an integer greater than or equal to 1).
  • the LCD device 32 is formed by that sold by the company Wintek under the reference ECB 582.901 VO1 EMU968A.
  • the VRMS values of the control voltages associated with the colors that can be displayed by such an LCD device are reported in table 1 below.
  • the LCD device 32 can preferably be arranged to can be ordered multiplexed.
  • the multiplexing rate is equal to 4.
  • the control device 30 comprises a processing unit 44 and a control block 40.
  • the processing unit 44 can supply the memory block 34, via a bus peripheral link, data D0a to D4d associated with the colors and representing the average values of an OUTPUT1 control voltage at provide to the LCD device 32 to control the display of one of the colors.
  • the processing unit 44 can also supply the control unit 40, via a peripheral link bus, binary data B0 to B7 relating to a information to display.
  • the processing unit 44 can in addition to providing a CLK clock signal, a SYN synchronization signal, a basic signal FR and four multiplexing signals ⁇ 1 to ⁇ 4.
  • the basic signal FR has the form of a square signal having a period T so that during the second half period of a cycle of the FR signal, the polarities of the control voltages supplied to the LCD device 32 are reversed compared to those of the voltages supplied during the first half period of this cycle.
  • the four multiplexing signals ⁇ 1 to ⁇ 4 have the form of four square signals with a period equal to T / 2, and phase shifted by T / 8 between them. So, signals ⁇ 1 to ⁇ 4 correspond respectively to the four phases successive of a complete multiplexing cycle.
  • the control device 30 also includes a source supply 42 capable of supplying four constant voltages V0 (voltage of reference), V1, V2 and V3. We note that the number of constant voltages provided depends on the multiplex rate.
  • the control block 40 can, in response to the binary data B0 to B7 of the processing unit 44, supply the LCD device 32 with the OUTPUT1 command to display said information with the desired color.
  • control device 30 further comprises a block of color level control 33 which may, in response to the data binary D0a to D4d, provide four analog signals VON0 to VON3 including the mean values are equal to those represented by the data D0a to D4d.
  • control block 40 can, in response to the binary data B0 to B7 and analog signals VON0 to VON3, provide one of the signals analog VON0 to VON3 in the form of the control voltage OUTPUT1, to control the display of said information with the color corresponding to this signal.
  • the color level control block 33 comprises, connected in series, a memory block 34, a modulation block 36, a conversion block 38 and a control block 40.
  • the memory block 34 can receive the binary data D0a to D4d from the processing unit 44, contain them, and supply them to the modulation block 36. These numerical data represent the VRMS values corresponding to available colors that can be displayed on the LCD 32.
  • the memory block 34 comprises four memory sub-blocks 34a to 34d which are each formed of a five-bit register which can contain the binary data representing the VRMS value of a color .
  • the memory sub-block 34a (34b, 34c, 34d, respectively) contains the five binary data D0a to D4a (D0b to D4b, D0c to D4c, D0d to D4d, respectively) representing the VRMS value of a first (second, third, fourth, respectively) color, this value being designated VRMSa (VRMSb, VRMSc, VRMSd, respectively) in the following description.
  • the values VRMSa, VRMSb, VRMSc, VRMSd are defined with a resolution of 32 bits (that is to say 25 ). It goes without saying that the number of colors (that is to say the number of registers) and that the number of bits of each register are cited only by way of example only.
  • the modulation block 36 can, in response to the clock signal CLK and to data D0a to D4d of memory block 34, supply four binary signals modulated EO to E3 having duty cycles representative of the values means associated with the four respective colors.
  • the modulation block 36 can receive signals D0a to D4d of memory block 34, as well as the clock signal CLK and the signal of SYN synchronization of the processing unit 44.
  • the block of modulation 36 can supply binary signals E0 to E3 to the conversion block 38, so that the signals E0 to E3 have periods equal to that of a multiplexing phase, and corresponding duty cycles respectively to the values VRMSa to VRMSd. It goes without saying that the number of signals provided by modulation block 36 is equal to the number of colors available whose VRMS values are represented in the memory block 34.
  • the modulation block 36 includes four modulation sub-blocks 36a to 36d capable of receiving the signals SYN, CLK and D0a to D4d, and respectively supply the signals E0 to E3, using the PWM pulse width modulation technique (acronym from English “Pulse-Width Modulation”).
  • FIG. 5B shows in more detail the sub-block of 36a modulation which includes, connected in series, a five-bit counter 60 controlled by signal CLK and signal SYN, and a digital comparator 61 receiving the data D0a to D4a.
  • a five-bit counter 60 controlled by signal CLK and signal SYN
  • a digital comparator 61 receiving the data D0a to D4a.
  • the counter 60 is initialized by a negative edge of the SYN signal, so that the modulation sub-block 36a operates cyclically and that the start of a modulation cycle corresponds to the start of a multiplexing cycle (i.e. the rising edge of the multiplexing signal ⁇ 1).
  • the state of counter 60 is then compared with the value coming from the sub-block memory 34a. Below this value (respectively above this value), comparator 61 supplies the voltage E0 equal to a high state "1" (respectively in a low state "0").
  • the converter block 38 may, in response to binary signals modulated E0 to E3 and at supply voltages V0 to V3, supply the signals analog V0N0 to V0N3 associated with the four respective colors.
  • the conversion block 38 can receive the digital signals E0 to E3 of the modulation block 36, as well as the voltages supply voltage V0 (reference voltage), V1, V2 and V3 power supply 42.
  • the conversion block 38 can supply the block control 40 the analog signals VON0 to VON3 having values means representing respectively the four VRMS values contained in memory block 34 and periods equal to that of the signal FR (it goes from the number of signals supplied by the conversion block 38 is equal to the number of colors available whose VRMS values are represented in memory block 34).
  • the conversion block 38 includes four conversion sub-blocks 38a to 38d which can: receive each the signals FR, V0 to V3, and respectively the signals E0 to E3; and supply the signals VON0 to VON3 respectively.
  • FIG. 6B shows in more detail the conversion sub-block 38a which comprises: two level shifting means 63 and 64; a NAND gate 65; a NOR gate 66; two AND gates 67 and 68; and two inverters "a” and “b” each comprising a PMOS transistor 69a and 69b, respectively, and an NMOS transistor 70a and 720b, respectively.
  • the level shifting means 63 can receive the signal FR and supply a voltage Q1 to the gates 65, 66 and 67, and a voltage Q 1 at gate 68.
  • the level shifting means 64 can receive the signal E0 and supplies a voltage Q2 to gates 65, 66 and 68, and a voltage Q 2 at door 67.
  • Doors 65 to 68 respectively control the transistors 69b, 69a, 70a and 70b.
  • the inverter “a” is connected between the voltages V1 and V2
  • the inverter “b” is connected between the voltages V0 and V3.
  • the connection point between the transistors 69a and 70a is connected to the connection point between the transistors 69b and 70b, and supplies the voltage VON0.
  • control unit 40 receives the four analog signals VON0 to VON3 and in response provides control voltages capable of controlling the LCD device 32, i.e. activating and deactivating each segment of the device LCD 32 to display the desired color.
  • the block of control 40 comprises a plurality of control sub-blocks 401, each sub-block being connected to one of the contact pads of the device LCD 32.
  • FIG. 7 represents in detail one of the sub-blocks of command 401 associated with the contact pad SEG1, and comprising two electronic switches 72 and 73, and four pairs of registers with two bits 75 to 78 (it goes without saying that the number of bits in registers 75 to 78 corresponds to the maximum number of colors available whose values VRMS are contained in memory block 34).
  • the voltage of OUTPUT1 command is associated with the contact area SEG1.
  • registers 75 to 78 are respectively associated with the four electrodes of the contact pad SEG1 (the multiplexing rate being equal to 4 in this example).
  • Register 75 (76, 77 and 78 respectively) can contain the binary data B0 and B1 (B2 and B3, B4 and B5, B6 and B7 respectively) validating, among the four colors available, the color to be displayed for the four electrodes the contact area SEG1.
  • B0 and B1 B2 and B3, B4 and B5, B6 and B7 respectively
  • Bi (i 0, 2, 4, 6)
  • Switch 73 can receive the four multiplexing signals ⁇ 1 to ⁇ 4 as a control signal and, in response, supply the contents of four registers 75 to 78 in the form of an S signal, during the four respective multiplexing phases.
  • the switch 72 can receive the four signals VON0 to VON3, thus the signal S as a control signal and, in response, providing the OUTPUT1 voltage via terminal SEG1.
  • the switch 72 includes four transmission doors which can respectively receive signals VON0 to VON3, be controlled by signal S and, in response, supply the OUTPUT1 voltage.
  • control sub-block 401 We will briefly describe the operation of the control sub-block 401.
  • two different data bits can be selected from registers 75 to 78, and this data in turn select one of the four signals VON0 to VON3. So, one any of the four signals VON0 to VON3 can be provided during any of the four multiplexing phases, which allows order the display of any of the four colors available at during these phases. For example, if the contents of register 76 is “10”, the color corresponding to the VRMS value contained in the form numeric in memory sub-block 34c is displayed during the second multiplexing phase. We note that such a correspondence is linked to the structure of switch 72
  • FIG. 8 represents fifteen timing diagrams 81 to 95 of the SYN, FR, ⁇ 1 to ⁇ 4, E0 to E3, VON0 to VON3 and OUTPUT1 signals.
  • the processing unit 44 controls the block memory 34 so that the latter contains in numerical form the value VRMS corresponding to four colors.
  • the signal ⁇ 1 goes from a state "0" to a state "1", which begins a cycle of four phases of multiplexing during from which the four segments connected to the SEG1 contact terminal.
  • the first phase of multiplexing is understood between time t0 and time t1
  • the second multiplexing phase is between time t1 and time t2
  • the third phase of multiplexing is between time t2 and time t3
  • the fourth multiplexing phase is between time t3 and time t4.
  • the signal FR goes from state “0” to state "1", which begins a modulation cycle.
  • the modulation block 36 supplies the conversion block 38 with the voltages E0 to E3, so that these are equal to the state “0” or “1” with specific duty reports representing the VRMS values of the four respective colors.
  • the reports cyclic voltages E0 to E3 are respectively 80%, 50%, 20% and 0%.
  • the conversion block 38 provides the control block 40 the analog voltages VON0 to VON3, so that the latter have duty cycles equal to those of voltages E0 to E3, respectively.
  • the value of the control voltage OUTPUT1 depends on the values contained in the registers 75 to 78 of the control block 40.
  • the binary data B0 and B1 contained in the register 75 are worth respectively (0, 0), so that during the first phase of multiplexing, the control voltage OUTPUT1 is then equal to the voltage VON0 whose average value is equal to VRMSa. So during the first multiplexing phase, the color displayed by the first segment corresponds to the first color.
  • the color displayed by the second segment corresponds to the second color
  • the color displayed by the third segment corresponds to the third color
  • the color displayed by the fourth segment corresponds to the fourth color
  • FIG. 9 represents such an improvement of the device for control 30 further comprising a measurement means 100. It is noted that objects represented in FIG. 9 identical to those described in the figures above have been designated by the same references.
  • the measuring means 100 can provide the processing unit 44 with the value of the temperature of the LCD device 32.
  • the unit of processing 44 can control memory block 34 so that the latter can provide a corrected VRMS value taking into account the effect of the temperature on this value, in order to control the display of the color desired regardless of temperature.
  • registers 75 to 78 of the control block 40 can contain three bits each, the number of modulation sub-blocks and the number of conversion sub-blocks must be adapted to the number of desired colors (i.e. equal to 8, using the example above).
  • the number of registers in control block 40 must be adapted to this modification (i.e. to be equal to the modified value of this rate).
EP99106457A 1999-03-30 1999-03-30 Anzeigetreiber für Flüssigkristallanzeige mit mindestens einer Farbstufe Withdrawn EP1041535A1 (de)

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EP99106457A EP1041535A1 (de) 1999-03-30 1999-03-30 Anzeigetreiber für Flüssigkristallanzeige mit mindestens einer Farbstufe

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9170048B2 (en) 2010-03-26 2015-10-27 Linde Aktiengesellschaft Device for the cryogenic separation of air

Citations (4)

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Publication number Priority date Publication date Assignee Title
US5206633A (en) * 1991-08-19 1993-04-27 International Business Machines Corp. Self calibrating brightness controls for digitally operated liquid crystal display system
EP0544427A2 (de) * 1991-11-27 1993-06-02 Sharp Kabushiki Kaisha Steuerschaltung für eine Anzeigeeinheit mit digitaler Sourcesteuerung zur Erzeugung von Mehrfachpegelsteuerspannungen aus einer einzelnen externen Energiequelle
JPH08234175A (ja) * 1995-02-24 1996-09-13 Casio Comput Co Ltd 液晶表示装置及び液晶表示素子の駆動方法
WO1997006482A1 (en) * 1995-08-08 1997-02-20 Casio Computer Co., Ltd. Electrically controlled birifringence liquid crystal display having more display areas and method of driving the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206633A (en) * 1991-08-19 1993-04-27 International Business Machines Corp. Self calibrating brightness controls for digitally operated liquid crystal display system
EP0544427A2 (de) * 1991-11-27 1993-06-02 Sharp Kabushiki Kaisha Steuerschaltung für eine Anzeigeeinheit mit digitaler Sourcesteuerung zur Erzeugung von Mehrfachpegelsteuerspannungen aus einer einzelnen externen Energiequelle
JPH08234175A (ja) * 1995-02-24 1996-09-13 Casio Comput Co Ltd 液晶表示装置及び液晶表示素子の駆動方法
WO1997006482A1 (en) * 1995-08-08 1997-02-20 Casio Computer Co., Ltd. Electrically controlled birifringence liquid crystal display having more display areas and method of driving the same

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Title
PATENT ABSTRACTS OF JAPAN vol. 097, no. 001 31 January 1997 (1997-01-31) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9170048B2 (en) 2010-03-26 2015-10-27 Linde Aktiengesellschaft Device for the cryogenic separation of air

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