EP0391654B1 - Treiberschaltung zum Treiben einer Flüssigkristallvorrichtung - Google Patents

Treiberschaltung zum Treiben einer Flüssigkristallvorrichtung Download PDF

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Publication number
EP0391654B1
EP0391654B1 EP90303539A EP90303539A EP0391654B1 EP 0391654 B1 EP0391654 B1 EP 0391654B1 EP 90303539 A EP90303539 A EP 90303539A EP 90303539 A EP90303539 A EP 90303539A EP 0391654 B1 EP0391654 B1 EP 0391654B1
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EP
European Patent Office
Prior art keywords
signal
electrodes
analogue
drive
drive device
Prior art date
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Expired - Lifetime
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EP90303539A
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English (en)
French (fr)
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EP0391654A3 (de
EP0391654A2 (de
Inventor
Yoshiharu Kanatani
Hirofumi Fukuoka
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Sharp Corp
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Sharp Corp
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Priority claimed from JP1085525A external-priority patent/JP2520168B2/ja
Priority claimed from JP1085524A external-priority patent/JP2520167B2/ja
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Publication of EP0391654A2 publication Critical patent/EP0391654A2/de
Publication of EP0391654A3 publication Critical patent/EP0391654A3/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • This invention relates to a drive device for driving a display apparatus and a display apparatus, and more particularly to a drive device for a display apparatus which is capable of gray-scale display by means of amplitude modulation and also to a display apparatus which is capable of gray-scale display by means of amplitude modulation.
  • a display apparatus using a matrix-type liquid crystal display unit will be described as a typical example of a display apparatus, but this invention can also be applied to drive circuits for other types of display apparatuses such as electroluminescent (EL) display apparatus and plasma display apparatus, and to such display apparatuses.
  • EL electroluminescent
  • FIG. 15 shows a matrix liquid crystal display apparatus of the prior art.
  • the matrix liquid crystal display of Figure 15 employs a TFT liquid crystal panel 100 comprising thin-film transistors (TFT) as the switching elements for driving pixel electrodes 103.
  • the TFT liquid crystal panel 100 further comprises n (numbered from 0 to n-1) scanning electrodes 101 positioned parallel to each other and m (numbered from 0 to m-1) signal electrodes 102 positioned parallel to each other and perpendicularly intersecting the scanning electrodes 101.
  • TFTs 104 for driving the pixel electrodes 103 are located in the vicinity of the intersections of the scanning electrodes 101 and the signal electrodes 102.
  • One horizontal scanning line is composed of m pixel electrodes 103 arranged in a row.
  • Counter electrodes 105 which are respectively opposite to the pixel electrodes 103 are formed.
  • a plurality of counter electrodes are shown in Figure 15, but actually they consist of one conductive layer formed in common to all of the pixel electrodes 103.
  • a fixed voltage v c is impressed on the counter electrodes 105.
  • the TFT liquid crystal panel 100 is driven by a drive device containing a source driver 200 and gate driver 300.
  • the source driver 200 and gate driver 300 are connected to the signal electrodes 102 and the scanning electrodes 101, respectively, of the TFT liquid crystal panel 100.
  • the source driver 200 samples an input analog video signal or video signal, and holds it. The held signal is supplied to the signal electrodes 102.
  • the gate driver 300 outputs scanning pulses to the scanning electrodes 101 in sequence.
  • the timing signal and other signals input to the gate driver 300 and source driver 200 are supplied from a control circuit 400.
  • the source driver 200 comprises a shift register 210, sample and hold circuits 220 and output buffers 230.
  • shift pulses input from the control circuit 400 are shifted in accordance with the shift clock, and sampling pulses are output sequentially to lines B1, B2, ..., B i , ..., B m .
  • analog switches ASW1(1), ..., ASW1(i), ..., ASW1(m) become closed in sequence, and sampling capacitors 221 are charged in sequence up to the instantaneous amplitude v(i, j) of the input analog video signal.
  • v(i, j) is the instantaneous amplitude of an analog video signal to be written to the pixel electrode 103 corresponding to the intersection of the ith signal electrode and jth scanning electrode of the TFT liquid crystal panel 100.
  • an output pulse OE is input, and the video signals are transferred from the sampling capacitors 221 to the holding capacitors 222.
  • the video signal held by the holding capacitors 222 are output to the signal electrodes 102 via the output buffers 230.
  • Figure 17 diagrammatically shows waveforms of the input and output signals in the source driver 200.
  • v(C SPL (i)), v(C H (i)) and v S (i) denote the voltage of the ith sampling capacitor 221, the voltage of the ith holding capacitor 222 and the output voltage of the ith output buffer 230, respectively.
  • the accuracy in the amplitude v(i, j) of a sampled video signal is determined by the time constant established by the on-resistance R ON of the closed analog switch ASW1(i) and the capacitance C SPL of the sampling capacitor 221.
  • the above-mentioned time constant must be selected so that the frequency band of the video signal is not narrowed by the sampling. More specifically, assuming the frequency at which the signal level drops by 3 dB is expressed as f(-3 dB) Hz in the frequency characteristic of the input analog video signal, then the condition in the following equation must be satisfied. 0.35 2.2 x R ON x C SPL >> f(-3 dB)
  • TFT liquid crystal panel 100 As the capacity and resolution of display panels (TFT liquid crystal panel 100) are increased, the frequency band becomes wider, which requires faster sampling, so a low R ON and small C SPL are required to satisfy the equation above.
  • the capacitance C SPL cannot be made very small. As this indicates, there is a limit to the minimization of the capacitance of the sampling capacitors 221, so it is difficult to greatly widen the frequency band of the input video signal. This problem becomes an obstacle to increasing the capacity of a display panel.
  • Analog video signals are supplied to the source driver 200 via the bus line as shown in Figure 16, and as the capacity and resolution of a display panel are increased, the frequency band of the video signal becomes wider and the distribution capacity of the bus line increases. This results in the necessity of a wideband amplifier in the circuit supplying video signals, and increases the cost of production.
  • analog video signals are sampled according to a clock signal and displayed in pixels arranged in a matrix. Because delays in the drive device including delays in the bus lines cannot be avoided, it is extremely difficult to accurately establish the sampling position for the analog video signals. Particularly, when displaying on a matrix display apparatus a computer graphic image in which the relationship between video signals and pixel addresses is clearly defined, though in theory it should be possible to perfectly reproduce computer-generated images on the display panel, shift in the image display position, bleeding of the image, etc., due to delays in the drive system and deterioration of the frequency characteristics cannot be avoided in drive circuits using an analog video signal sampling method of the prior art.
  • a drive device for driving a display apparatus having a display unit, the display unit including a plurality of signal electrodes arranged in juxtaposition and a plurality of scanning electrodes arranged in juxtaposition and crossed with the signal electrodes, the drive device comprising a signal electrode drive means for supplying an analogue signal to one of the signal electrodes.
  • the above reference also discloses a display apparatus, on which the preamble of present claim 5 is based.
  • EP-A-0 254 805 discloses a drive device which uses binary signals to drive a matrix display, to obtain pixel gradation. In order to obtain a N-gradation of the display, it is necessary to drive each picture element N - 1 times in each scanning period.
  • a drive device for driving a display apparatus having a display unit, the display unit including a plurality of signal electrodes arranged in juxtaposition and a plurality of scanning electrodes arranged in juxtaposition and crossed with the signal electrodes, the drive device comprising a signal electrode drive means for supplying an analogue drive signal to one of the signal electrodes;
  • the signal electrode drive means comprises: a memory means for storing an input digital video signal; pulsewidth conversion means for converting the input digital video signal stored in the memory means for a horizontal scanning period into a pulse signal, the width of the pulse signal corresponding to the information contained in the input digital video signal; a pulsewidth-amplitude conversion means for converting the pulse signal into an analogue signal, the amplitude of the analogue signal corresponding to the pulsewidth of the pulse signal; and an output circuit for supplying the analogue drive signal to the one of the signal electrodes, in accordance with the analogue signal.
  • the output circuit comprises a capacitance for holding said analog signal.
  • the memory means stores a plurality of input digial video signals which are required to one horizontal scan.
  • a display apparatus comprises pixel electrodes arranged in a matrix; a plurality of signal electrodes arranged in juxtaposition; a plurality of scanning electrodes arranged in juxtaposition and crossed with the signal electrodes; a drive device for outputting drive signals for driving the pixel electrodes through the signal electrodes, the drive device comprising a signal electrode drive means for supplying an analogue drive signal to one of the signal electrodes; and holding means for holding the analogue drive signal, the holding means being provided at an output portion of the drive device; the display apparatus being characterized in that the signal electrode drive means further comprises; a memory means for storing an input digital video signal; pulsewidth conversion means for converting the input digital video signal stored in the memory means for a horizontal scanning period into a pulse signal, the width of the pulse signal corresponding to the information contained in the input digital video signal; a pulsewidth-amplitude conversion means for converting the pulse signal into an analogue signal, the amplitude of the analogue signal corresponding to the pulsewidth
  • the holding means is a capacitance formed between one of said signal electrodes and a counter electrode which opposes said pixel electrodes.
  • the memory means stores the plurality of input digital video signals which are required for one horizontal scan.
  • Figure 1 is a block diagram of a matrix-type liquid crystal display apparatus in which a drive device of the invention is used.
  • Figure 2 is a block diagram of a source driver of the device shown in Figure 1.
  • Figure 3 illustrates essential portions of a digital data memory and a bit comparison and pulsewidth conversion circuit of the device shown in Figure 1.
  • Figure 4 is a circuit diagram of a BPC circuit of the device shown in Figure 1.
  • Figure 5 illustrates essential portions of a D/A conversion and output circuit of the device shown in Figure 1.
  • Figure 6 is a timing chart showing the operation of the BPC circuit and the D/A conversion and output circuit of the device shown in Figure 1.
  • Figure 7 is a timing chart showing the display drive operation of the source driver of Figure 2.
  • Figure 8 is a block diagram of a matrix-type liquid crystal display apparatus according to the invention.
  • Figure 9 is a block diagram of a source driver of the apparatus of Figure 8.
  • Figure 10 illustrates essential portions of a digital data memory and a bit comparison and pulsewidth conversion circuit of the apparatus of Figure 8.
  • Figure 11 is a circuit diagram of a BPC circuit of the apparatus of Figure 8.
  • Figure 12 illustrates essential portions of a D/A conversion circuit of the apparatus of Figure 8.
  • Figure 13 is a timing chart showing the operation of the BPC circuit and the D/A conversion circuit of the apparatus of Figure 8.
  • Figure 14 is a timing chart showing the display drive operation of the source driver of Figure 9.
  • Figure 15 is a block diagram of a matrix-type liquid crystal display apparatus using a prior art drive device.
  • Figure 16 is a circuit diagram of a source driver of the conventional drive device shown in Figure 15.
  • Figure 17 is a timing chart showing the operation of the source driver of Figure 16.
  • FIG. 1 shows a matrix liquid crystal display apparatus in which a drive device according to the invention is used.
  • the display apparatus of Figure 1 has a TFT liquid crystal panel 100 as a display unit.
  • the TFT liquid crystal panel 100 is driven by a drive device 1 comprising a source driver 2, a gate driver 300, and a control circuit 4.
  • the TFT liquid crystal panel 100 and gate driver 300 have essentially the same configuration as those of the prior art shown in Figure 15, and their detailed description is omitted.
  • the source driver 2 comprises an up-down counter and decoder circuit 20, a digital data memory 30, a bit comparison and pulsewidth conversion circuit 40, a level shifter circuit 60, and a D/A conversion and output circuit 50.
  • the source driver 2 performs digital-analog conversion of input digital video signals, and sends the resulting amplitude-modulated analog signals to the signal electrodes 102 of the TFT liquid crystal panel 100.
  • the various signals required by the source driver 2 are supplied from the control circuit 4.
  • the source driver 2 is illustrated in more detail in Figure 2.
  • the RGB video signals are expressed by 4-bit data R0 - R3, G0 - G3 and B0 - B3, respectively.
  • the up-down counter and decoder circuit 20 has an up-down counter 21 and a decoder 22.
  • the up-down counter 21 receives a U/D signal which specifies counting in the direction of increase or in the direction of decrease, and a clock signal CK which actuates the counter operation in the up-down counter 21.
  • the output of the up-down counter 21 is decoded by the decoder 22.
  • the up-down counter and decoder circuit 20 may be composed of shift registers.
  • the R signals (R0 - R3), G signals (G0 - G3) and B signals (B0 - B3) contained in input digital video signals are latched once by latches 31, 32 and 33, respectively, and, according to the output of the decoder 22, they are then stored in the corresponding memory regions in an R memory 34, a G memory 35 and a B memory 36 which constitute the digital data memory 30.
  • a latch strobe signal LS is input so that the data in the digital data memory 30 are supplied to the bit comparison and pulsewidth conversion circuit 40 over parallel lines.
  • the output of the bit comparison and pulsewidth conversion circuit 40 is supplied to the D/A conversion and output circuit 50 via the level shifter circuit 60.
  • FIG. 3 shows a block diagram of the system which processes the R signals in the R memory 34 and the bit comparison and pulsewidth conversion circuit 40.
  • the R memory 34 comprise memory units 341 which are arranged in a one-to-one correspondence to the signal electrodes 102 of the TFT liquid crystal panel 100. Each memory units 341 have four memory elements R0(i) - R3(i) for storing 4-bit video signals.
  • the bit comparison and pulsewidth conversion circuit 40 has bit pulsewidth converter (BPC) circuits 41 which correspond respectively to the memory units 341. Digital video signals stored in the memory units 341 are transferred to the corresponding BPC circuits 41, in response to a latch strobe signal LS from the control circuit 4.
  • BPC bit pulsewidth converter
  • Each BPC circuit 41 receives a start pulse ST and count signals C0 - C3 from the control circuits 4 in addition to the latch strobe signal LS.
  • video signals input from the memory units 341 are converted into pulses the width of which correspond respectively to the information born in the video signals, and the pulses are then supplied to the level shifter circuit 60 as outputs R PW (i).
  • R PW (i) In order to process G and B signals, systems which are substantially the same as that shown in Figure 3 are provided.
  • the BPC circuits 41 comprises latches L0 - L3, EXNOR gates 411, a NAND gate 412, and an RS flip-flop 413.
  • the latches L0 - L3 latch video signals R0(i) R3(i) in 4 bit R signals.
  • the start pulse ST is input to the set terminal of the RS flip-flop 413 to set the flip-flop, thereby making the signal R PW (i) high.
  • the count signals C0 - C3 gradually increase in the sequence of (0, 0, 0, 0), (0, 0, 0, 1), ...., (1, 1, 1, 1).
  • the EXNOR gates 411 compare bit by bit the latched video signal (R0(i) - R3(i)) with the count signals C0 - C3.
  • the output RC(i) of the NAND gate 412 becomes low.
  • the output RC(i) of low level is input to the reset terminal of the RS flip-flop 413 to return the signal R PW (i) to low level. In this way, input video signals are converted into pulses the width of which correspond respectively to the information born in the video signals.
  • the pulse width of the signal R PW (i) is converted to an amplitude of a voltage signal by the level shifter circuit 60 and the D/A conversion and output circuit 50.
  • the level shifter circuit 60 comprises a level shifter 61
  • the D/A conversion and output circuit 50 comprises an analog gate 52, a hold capacitor 53, and an output buffer 54.
  • the level of the signal R PW (i) is converted to the V CC -V DD power supply systems by the level shifter 61.
  • the signal R PW (i) which has been level shifted is used for operating the analog gate 52.
  • the control circuit 4 supplies to the analog gate 52 a voltage signal AS the level of which increases or decreases stepwise in synchronization with the change of the count signals C0 - C3 ( Figure 6).
  • the analog gate 52 is closed so that the voltage of the hold capacitor 53 varies following the change of the voltage signal AS.
  • the analog gate 52 is opened, thereby fixing the voltage of the hold capacitor 53 to the voltage level which appears at the terminal of the analog gate 52 (i.e., which is the level of the voltage signal AS) immediately before the analog gate 52 becomes opened.
  • the hold capacitor 53 is coupled to the input of the output buffer 54 which then outputs a voltage signal R(i) for driving the signal electrode 102 of the TFT liquid crystal panel 100.
  • the level of the signal R(i) corresponds to that of the hold capacitor 53.
  • Each portions of the level shifter circuit 60 and D/A conversion and output circuit 50 which correspond to the signal electrodes 102 operate in parallel in a similar manner as described above.
  • Figure 6 illustrates the above operation by showing the waveforms of the voltage signal AS, the count signals C0 - C3, the start pulse ST, and the signals RC(i), R PW (i) and R(i) which are obtained when the input video signal (R0(i) - R3(i)) is (0, 1, 1, 1).
  • the start pulse ST is input, the signal R PW (i) becomes high.
  • the count signals C0 - C3 reach (0, 1, 1, 1)
  • the signal R PW (i) returns to the low level, and the output signal R(i) is fixed to the level at this point.
  • the timing of display drive in the source driver 2 is shown in Figure 7.
  • the relationships between the signal G PW (i) and voltage signal G(i) and the video signals G0 - G3, and the signal B PW (i) and voltage signal B(i) and the video signals B0 - B3 are the same as the above-described relationship between the signal R PW (i) and voltage signal R(i) and the video signals R0 - R3.
  • the video signal for the jth horizontal scanning line are D/A-converted by utilizing the entire of the (j+1)th horizontal scanning period following the jth horizontal scanning period, and the obtained analog signals are transferred to the signal electrodes 102. Therefore, the process of storing the input video signals into the digital data memory 30 must be done quickly, but D/A conversion can be done at a slower rate.
  • the TFT liquid crystal panel 100 and other display panels deteriorate more quickly when a DC component is contained in the impressed voltage.
  • the increase and decrease of the level of the signal AS from which the voltages applied to the liquid crystal panel 100 are generated occur alternately as each horizontal scanning period elapses, in order to prevent deterioration of the display panel.
  • FIG 8 shows a display apparatus according to the invention.
  • the embodiment shown in Figure 8 is a matrix-type liquid crystal display apparatus comprising a TFT liquid crystal panel 100 as a display unit, and has a similar configuration as the display apparatus of Figure 1 except that a D/A conversion circuit 55 is provided instead of the D/A conversion and output circuit 50.
  • the configuration of the embodiment will be described regardless of repetition.
  • the TFT liquid crystal panel 100 is driven by a drive device 1 comprising a source driver 2, a gate driver 300 and a control circuit 4.
  • the TFT liquid crystal panel 100 and gate driver 300 have essentially the same configuration as those of the prior art shown in Figure 15.
  • the source driver 2 comprises an up-down counter and decoder circuit 20, a digital data memory 30, a bit comparison and pulsewidth conversion circuit 40, a level shifter circuit 60, and the D/A conversion circuit 55.
  • the various signals required by the source driver 2 are supplied from the control circuit 4.
  • the source driver 2 is illustrated in more detail in Figure 9.
  • the RGB video signals are expressed by 4-bit data R0 - R3, G0 - G3 and B0 - B3, respectively.
  • the up-down counter and decoder circuit 20 has an up-down counter 21 and a decoder 22.
  • the up-down counter 21 receives a U/D signal which specifies counting in the direction of increase or in the direction of decrease, and a clock signal CK which actuates the count operation in the up-down counter 21.
  • the output of the up-down counter 21 is decoded by the decoder 22.
  • the up-down counter and decoder circuit 20 may be composed of shift registers.
  • the R signals (R0 - R3), G signals (G0 - G3) and B signals (B0 - B3) contained in input digital video signals are latched once by latches 31, 32 and 33, respectively, and, according to the output of the decoder 22, they are then stored in the corresponding memory regions in an R memory 34, a G memory 35 and a B memory 36 which constitute the digital data memory 30.
  • a latch strobe signal LS is input so that the data in the digital data memory 30 are supplied to the bit comparison and pulsewidth conversion circuit 40 over parallel lines.
  • the output of the bit comparison and pulsewidth conversion circuit 40 is supplied to the D/A conversion circuit 55 via the level shifter circuit 60.
  • FIG 10 shows a block diagram of the system which processes the R signals in the R memory 34 and the bit comparison and pulsewidth conversion circuit 40.
  • the R memory 34 comprise memory units 341 which are arranged in a one-to-one correspondence to the signal electrodes 102 of the TFT liquid crystal panel 100. Each memory units 341 have four memory elements R0(i) - R3(i) for storing 4-bit video signals.
  • the bit comparison and pulsewidth conversion circuit 40 has bit pulsewidth converter (BPC) circuits 41 which correspond respectively to the memory units 341. Digital video signals stored in the memory units 341 are transferred to the corresponding BPC circuits 41, in response to a latch strobe signal LS from the control circuit 4.
  • BPC bit pulsewidth converter
  • Each BPC circuit 41 receives a start pulse ST and count signals C0 - C3 from the control circuits 4 in addition to the latch strobe signal LS.
  • video signals input from the memory units 341 are converted into pulses the width of which correspond respectively to the information born in the video signals, and the pulses are then supplied to the level shifter circuit 60 as outputs R PW (i).
  • R PW (i) In order to process G and B signals, systems which are substantially the same as that shown in Figure 10 are provided.
  • the BPC circuit 41 comprises latches L0 - L3, EXNOR gates 411, a NAND gate 412, and an RS flip-flop 413.
  • the latches L0 - L3 latch video signals R0(i) - R3(i) in 4-bit R signals.
  • the start pulse ST is input to the set terminal of the RS flip-flop 413 to set the flip-flop, thereby making the signal R PW (i) high.
  • the count signals C0 - C3 gradually increase in the sequence of (0, 0, 0, 0), (0, 0, 0, 1), ...., (1, 1, 1, 1).
  • the EXNOR gate 411 compares bit by bit the latched video signal (R0(i) - R3(i)) with the count signals C0 - C3.
  • the output RC(i) and the NAND gate 412 becomes low.
  • the output RC(i) of low level is input to the reset terminal of the RS flip-flop 413 to return the signal R PW (i) to low level. In this way, input video signals are converted into pulses the width of which correspond respectively to the information born by the video signals.
  • the pulse width of the signal R PW (i) is converted to an amplitude of a voltage signal by the level shifter circuit 60 and the D/A conversion circuit 55.
  • the level shifter circuit 60 comprises a level shifter 61
  • the D/A conversion circuit 55 comprises an analog gate 52.
  • the jth scanning electrode 101, the TFT 104, the pixel electrode 103, and the counter electrode 105 are also shown.
  • the level of the signal R PW (i) is converted to the V CC -V DD power supply systems by the level shifter 61.
  • the signal R PW (i) which has been level-shifted is used for operating the analog gate 52.
  • the control circuit 4 supplies to the analog gate 52 a voltage signal AS the level of which increases or decreases stepwise in synchronization with the change of the count signals C0 - C3 ( Figure 13).
  • the analog gate 52 is closed so that the signal AS is applied to the signal electrode 102, thereby charging or discharging the signal electrode capacitance C SL of the signal electrode 102.
  • the signal electrode capacitance C SL consists mainly of: (1) the capacitance between the signal electrode 102 and the counter electrode 105; (2) the capacitance formed at the intersection of the signal electrode 102 and the scanning electrode 101; and (3) the capacitance between the source electrode and gate electrode of the TFT 104. Among these capacitances (1) to (3), the capacitance (1) is the largest one.
  • Figure 13 illustrates the above operation by showing the waveforms of the voltage signal AS, the count signals C0 C3, the start pulse ST, and the signals RC(i), R PW (i) and R(i) which are obtained when the input video signal (R0(i) - R3(i)) is (0, 1, 1, 1).
  • the start pulse ST is input, the signal R PW (i) becomes high.
  • the count signals C0 - C3 reach (0, 1, 1, 1)
  • the signal R PW (i) returns to the low level, and the output signal R(i) of the analog gate 52 is fixed to the level at this point.
  • the timing of display drive in the source driver 2 is shown in Figure 14.
  • the video signal for the jth horizontal scanning line is D/A-converted by utilizing the entire of the (j+1)th horizontal scanning period following the jth horizontal scanning period, and the obtained analog signals are transferred to the signal electrodes 102. Therefore, the process of storing the input video signals into the digital data memory 30 must be done quickly, but D/A conversion can be done at a slower rate.
  • the TFT liquid crystal panel 100 and other display panels deteriorate more quickly when a DC component is contained in the impressed voltage.
  • the increase and decrease of the level of the signal AS from which the voltages applied to the liquid crystal panel 100 are generated occur alternately as each horizontal scanning period elapses, in order to prevent deterioration of the display panel.
  • improved drive devices for a display apparatus and improved display apparatuses are provided which solve the various problems involved in prior art systems in which the analog video signal sampling method is used.
  • digitized video signals are once stored, and then transferred. Therefore, deterioration of the frequency characteristics of video signals due to the sampling time constant, which is a problem in prior art display systems of the analog video signal sampling type, can be avoided. Further, amplitude attenuation due to charge distribution between the sampling capacitor and the holding capacitor also does not occur.
  • the drive device and the display apparatus of this invention can accommodate display panels with increased capacity by basically speeding up the logic circuits constituting the memory circuit which stores input digital video signals.
  • the video signal memory circuit is capable of storing video signals for at least one horizontal scan, so the D/A conversion of the stored digital video signals can be performed relatively slowly by utilizing the next horizontal scanning period. This not only contributes to lowering the cost of the drive device, but it also improves display accuracy.
  • analog signals which have been obtained by D/A conversion can be stored by utilizing the capacitances formed by the signal electrodes formed in a display unit, thus eliminating the necessity of providing hold capacitors and output buffers in a drive device. According to the invention, therefore, the production cost of a display apparatus can be reduced, and the deterioration of the display quality due to uneven offset values of output buffers can be eliminated.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Claims (8)

  1. Treibervorrichtung (1) zum Treiben einer Anzeigevorrichtung mit einer Anzeigeeinheit (100), wobei die Anzeigeeinheit mehrere nebeneinander angeordnete Signalelektroden (102) und mehrere nebeneinander angeordnete Abrasterelektroden (101), die die Signalelektroden (102) überkreuzen, aufweist, und wobei die Treibervorrichtung (1) eine Signalelektroden-Treibereinrichtung (2) zum Zuführen eines analogen Treibersignals (R(i)) an eine der Signalelektroden (102) aufweist;
    wobei die Treibervorrichtung (1) dadurch gekennzeichnet ist, daß die Signalelektroden-Treibereinrichtung (2) folgendes aufweist:
    - eine Speichereinrichtung (30, 34) zum Abspeichern eines digitalen Eingangsvideosignals;
    - eine Impulsbreitenumsetzeinrichtung (40, 41) zum Umsetzen des in der Speichereinrichtung (30, 34) für eine Horizontalabrasterperiode eingespeicherten digitalen Eingangsvideosignals in ein Impulssignal, dessen Breite der im digitalen Eingangsvideosignal enthaltenen Information entspricht;
    - eine Impulsbreite/Amplitude-Umsetzeinrichtung (50, 55) zum Umsetzen des Impulssignals in ein analoges Signal, dessen Amplitude der Impulsbreite des Impulssignals entspricht; und
    - eine Ausgangsschaltung zum Zuführen des analogen Treibersignals (R(i)) an eine der Signalelektroden, in Übereinstimmung mit dem analogen Signal.
  2. Treibervorrichtung nach Anspruch 1, bei der die Ausgangsschaltung eine Kapazität (53) zum Halten des analogen Signals aufweist.
  3. Treibervorrichtung nach Anspruch 1 oder Anspruch 2, bei der die Speichereinrichtung (30, 34) mehrere digitale Eingangsvideosignale speichert, wie sie für eine Horizontalabrasterperiode erforderlich sind.
  4. Treibervorrichtung nach einem der Ansprüche 1, 2 oder 3, bei der die Impulsbreite/Amplitude-Umsetzeinrichtung (55) das Impulssignal unter Verwendung eines treppenförmigen Spannungssignals in ein analoges Signal umsetzt.
  5. Anzeigevorrichtung mit: in einer Matrix angeordneten Pixelelektroden (103); mehreren nebeneinanderliegend angeordneten Signalelektroden (102); mehreren nebeneinanderliegend angeordneten Abrasterelektroden (101), die die Signalelektroden (102) überkreuzen; einer Treibervorrichtung (1) zum Ausgeben von Treibersignalen zum Ansteuern der Pixelelektroden (103) über die Signalelektroden (102), wobei die Treibervorrichtung eine Signalelektroden-Treibereinrichtung (2) zum Zuführen eines analogen Treibersignals (R(i)) an eine der Signalelektroden (102) aufweist; und einer Halteeinrichtung (53) zum Halten des analogen Treibersignals (R(i)), die in einem Ausgangsteil der Treibervorrichtung (1) vorhanden ist;
    wobei die Anzeigeeinrichtung dadurch gekennzeichnet ist, daß die Signalelektroden-Treibereinrichtung ferner folgendes aufweist:
    - eine Speichereinrichtung (30, 34) zum Abspeichern eines digitalen Eingangsvideosignals;
    - eine Impulsbreitenumsetzeinrichtung (40, 41) zum Umsetzen des in der Speichereinrichtung (30, 34) für eine Horizontalabrasterperiode eingespeicherten digitalen Eingangsvideosignals in ein Impulssignal, dessen Breite der im digitalen Eingangsvideosignal enthaltenen Information entspricht;
    - eine Impulsbreite/Amplitude-Umsetzeinrichtung (50, 55) zum Umsetzen des Impulssignals in ein analoges Signal, dessen Amplitude der Impulsbreite des Impulssignals entspricht; und
    - eine Ausgangsschaltung zum Zuführen des analogen Treibersignals (R(i)) an eine der Signalelektroden, in Übereinstimmung mit dem analogen Signal.
  6. Anzeigevorrichtung nach Anspruch 5, bei der die Halteeinrichtung (53) eine Kapazität ist, die zwischen einer der Signalelektroden (102) und einer Gegenelektrode (105) ausgebildet ist, die den Pixelelektroden (103) gegenübersteht.
  7. Anzeigevorrichtung nach Anspruch 5 oder Anspruch 6, bei der die Speichereinrichtung (30, 34) mehrere digitale Eingangsvideosignale speichert, wie sie für eine horizontale Abrasterperiode erforderlich sind.
  8. Anzeigevorrichtung nach einem der Ansprüche 5, 6 oder 7, bei der die Impulsbreite/Amplitude-Umsetzeinrichtung (50, 55) das Impulssignal unter Verwendung eines treppenförmigen Spannungssignals in das analoge Signal umsetzt.
EP90303539A 1989-04-04 1990-04-03 Treiberschaltung zum Treiben einer Flüssigkristallvorrichtung Expired - Lifetime EP0391654B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1085525A JP2520168B2 (ja) 1989-04-04 1989-04-04 表示装置
JP1085524A JP2520167B2 (ja) 1989-04-04 1989-04-04 表示装置のための駆動回路
JP85524/89 1989-04-04
JP85525/89 1989-04-04

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EP0391654A2 EP0391654A2 (de) 1990-10-10
EP0391654A3 EP0391654A3 (de) 1991-04-10
EP0391654B1 true EP0391654B1 (de) 1994-11-02

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JP2642204B2 (ja) * 1989-12-14 1997-08-20 シャープ株式会社 液晶表示装置の駆動回路
WO1992007352A1 (fr) * 1990-10-19 1992-04-30 Thomson S.A. Circuit de commande pour afficheur de type matriciel et decodeur de signal pour un tel circuit
US5317401A (en) * 1992-06-19 1994-05-31 Thomson Consumer Electronics S.A. Apparatus for providing contrast and/or brightness control of a video signal
GB9217336D0 (en) * 1992-08-14 1992-09-30 Philips Electronics Uk Ltd Active matrix display devices and methods for driving such
GB9223697D0 (en) * 1992-11-12 1992-12-23 Philips Electronics Uk Ltd Active matrix display devices
KR950007126B1 (ko) * 1993-05-07 1995-06-30 삼성전자주식회사 액정 디스플레이 구동장치
JP3329008B2 (ja) * 1993-06-25 2002-09-30 ソニー株式会社 双方向信号伝送回路網及び双方向信号転送シフトレジスタ
JP3102666B2 (ja) * 1993-06-28 2000-10-23 シャープ株式会社 画像表示装置
JP3277056B2 (ja) * 1993-12-09 2002-04-22 シャープ株式会社 信号増幅回路及びこれを用いた画像表示装置
US5734366A (en) * 1993-12-09 1998-03-31 Sharp Kabushiki Kaisha Signal amplifier, signal amplifier circuit, signal line drive circuit and image display device
JPH09230834A (ja) 1996-02-27 1997-09-05 Sony Corp アクティブマトリクス表示装置
KR100311204B1 (ko) * 1998-10-20 2001-11-02 가나이 쓰토무 액정표시장치
JP2002258810A (ja) 2001-03-05 2002-09-11 Hitachi Ltd 液晶表示装置

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GB2205191A (en) * 1987-05-29 1988-11-30 Philips Electronic Associated Active matrix display system
JP2651164B2 (ja) * 1987-11-10 1997-09-10 シチズン時計株式会社 カラー液晶表示装置

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Publication number Publication date
KR930005376B1 (ko) 1993-06-19
KR900016935A (ko) 1990-11-14
EP0391654A3 (de) 1991-04-10
DE69013736T2 (de) 1995-05-04
EP0391654A2 (de) 1990-10-10
DE69013736D1 (de) 1994-12-08

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