US20170177779A1 - Integrated Circuit Implementing Scalable Meta-Data Objects - Google Patents
Integrated Circuit Implementing Scalable Meta-Data Objects Download PDFInfo
- Publication number
- US20170177779A1 US20170177779A1 US15/452,364 US201715452364A US2017177779A1 US 20170177779 A1 US20170177779 A1 US 20170177779A1 US 201715452364 A US201715452364 A US 201715452364A US 2017177779 A1 US2017177779 A1 US 2017177779A1
- Authority
- US
- United States
- Prior art keywords
- metal
- layout
- transistor
- diffusion region
- interconnect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000009792 diffusion process Methods 0.000 claims description 61
- 238000000034 method Methods 0.000 abstract description 45
- 230000008569 process Effects 0.000 abstract description 8
- 238000005389 semiconductor device fabrication Methods 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 description 34
- 238000013461 design Methods 0.000 description 11
- 235000013599 spices Nutrition 0.000 description 8
- 238000007792 addition Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 4
- 230000001419 dependent effect Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004590 computer program Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241000120020 Tela Species 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 235000019988 mead Nutrition 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G06F17/5072—
-
- G06F17/5036—
-
- G06F17/5077—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
-
- G06F2217/12—
Definitions
- IC layout is represented by polygons in standard formats like GDS-II (Graphic Data System) and OASIS (Open Artwork System Interchange Standard). Re-use of IC layout has been desired for many years. Because of technology scaling, re-use of IC layout has been limited or not possible. Therefore, the IC layout polygons need to be redrawn each time a technology changes, for example moving to smaller dimensions.
- GDS-II Graphic Data System
- OASIS Open Artwork System Interchange Standard
- a method for defining an integrated circuit.
- the method includes generating a digital data file that includes both electrical connection information for a number of circuit components and physical topology information for the number of circuit components.
- the method also includes operating a computer to execute a layout generation program.
- the layout generation program reads the electrical connection information and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file.
- the method further includes operating the computer to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.
- a system for defining an integrated circuit includes a computer system including a processor and a memory.
- the system also includes a digital data file stored in the memory.
- the digital data file includes both electrical connection information for a number of circuit components and physical topology information for the number of circuit components.
- the system also includes a layout generation program stored as a set of computer executable instructions in the memory.
- the layout generation program is defined to read the electrical connection information and physical topology information for each of the number of circuit components from the digital data file and automatically create a digital representation of one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file.
- the layout generation program is further defined to store the digital representation of the one or more automatically created layout structures in a digital format on a computer readable medium.
- FIG. 1 shows a topological schematic view of the two input NAND gate of Table 2, in accordance with one embodiment of the present invention.
- FIG. 2 shows a flow chart of a method for generating a physical layout from meta-data input, in accordance with one embodiment of the present invention.
- FIG. 3 shows a plan view of the two input NAND gate of Table 2 and FIG. 1 with the placements of the diffusion ( 345 , 347 , 341 , 343 ) and linear conductive structures ( 351 , 353 ) that form gate electrodes of the four transistors m1, m2, m3, m4, in accordance with one embodiment of the present invention.
- FIG. 4 shows a plan view of the two input NAND gate with the addition of a VSS rail 465 , and a gate connection formed by a gate contact 463 and a metal-1 structure 461 , in accordance with one embodiment of the present invention.
- FIG. 5 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a metal-1 vertical structure 523 and a diffusion contact 525 , in accordance with one embodiment of the present invention.
- FIG. 6 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a diffusion structure 623 and a diffusion contact 625 , in accordance with one embodiment of the present invention.
- FIG. 7 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a local-interconnect structure 723 and a contact structure 725 , in accordance with one embodiment of the present invention.
- FIG. 8 shows a plan view of the two input NAND gate with all the connections made, in accordance with one embodiment of the present invention.
- FIG. 9 shows a plan view of the two input NAND gate with all the connections made, in accordance with another embodiment of the present invention.
- FIG. 10 shows a plan view of an inverter with all connections made, in accordance with one embodiment of the present invention.
- FIG. 11 shows a variation of the plan view of the inverter of FIG. 10 , in accordance with one embodiment of the present invention.
- FIG. 12 shows a flowchart of a method for defining an integrated circuit, in accordance with one embodiment of the present invention.
- FIG. 13 shows a system for defining an integrated circuit, in accordance with one embodiment of the present invention.
- the invention described herein can use the Tela Innovations, Inc., Dynamic Array Architecture (i.e., gridded design style), as described in U.S. Pat. Nos. 7,446,352 and 7,917,879, each of which is incorporated herein by reference in its entirety.
- Dynamic Array Architecture i.e., gridded design style
- CMOS transistors are used in the examples described herein, but it should be understood that other components can be handled in an analogous fashion.
- the Dynamic Array Architecture can be implemented with a coarse grid in the “x” and “y” directions to facilitate identification of the locations of objects like transistors, contacts, and gaps in lines, i.e., linear conductive structures.
- the linear conductive structures can be positioned on and/or according to the grids.
- Table 1 shows a portion of a SPICE netlist, listing the lines needed for a two input NAND gate identified as a sub-circuit. On the first line, a name is specified for the sub-circuit, followed by identification of input, output, and power supply pins. The four transistors used are identified with one in each line.
- the SPICE convention for a MOS transistor is “name Drain Gate Source Bulk Model-name Width Length.” Other parameters can also be included.
- the 4 nodes of the transistor are in the order DGSB.
- the netlist of Table 1 is an example, using MOS transistors.
- Other components like resistors, diodes, bipolar transistors, and MOS transistors with other model names (e.g., to represent transistors with different threshold voltages) can be expected and handled in the same fashion.
- each of the input, output, and power supply pins are connected to nodes of transistors as needed to perform the circuit function.
- n1 there is one internal node, which has no connection outside the sub-circuit.
- the netlist describes a circuit topology that is quite universal. However, having fixed values for the length and width parameters within the netlist circuit topology limits the scalability of the NAND sub-circuit.
- the length and width parameters can be replaced by variable values or expressions which are controlled by global parameters within the complete SPICE deck. Also, a similar Verilog-AMS netlist could be used, since it would contain a representation of the components and the topological connections of the nodes.
- the SPICE netlist is extended to include additional information for generating a physical topology from the circuit topology.
- Table 2 shows an example netlist for the two input NAND gate including possible extensions for generating the physical topology, in accordance with one embodiment of the present invention.
- the initial comments in the netlist explain the new syntax.
- width could be in some other simple unit of metal-1 pitch, for example 1 ⁇ 8 or 1 ⁇ 5 of the metal-1 pitch.
- length could be specified as coded values.
- FIG. 1 shows a topological schematic view of the two input NAND gate of Table 2, in accordance with one embodiment of the present invention.
- Input pin A is 111 .
- Input pin B is 113 .
- Output pin Y is 115 and is connected to internal node n2, which is 121 .
- VDD is 101 .
- VSS is 103 .
- Internal node n1 is 123 .
- Transistor m1 is 135 , and is connected to VSS by connection 109 , and is further connected to internal node n1 123 .
- Transistor m2 is 131 , and is connected to VDD by connection 107 , and is further connected to both internal node n2 121 and output pin Y 115 .
- Transistor m3 is 137 , and is connected to internal node n1 123 , and is further connected to both output pin Y 115 and internal node n2 121 .
- Transistor m4 is 133 , and is connected to VDD by connection 105 , and is further connected to both internal node n2 121 and output pin Y 115 .
- FIG. 2 shows a flow chart of a method for generating a physical layout from meta-data input, in accordance with one embodiment of the present invention.
- the method of FIG. 2 can be implemented by a tool (e.g., computer program) which reads meta-data object input, and combines the meta-data object input with information from a technology file to create a physical layout. Because essentially any circuit is formed by components attached to nodes which are interconnected, the method of FIG. 2 is not limited to CMOS devices. In general, the method of FIG. 2 can be applied to any mapping of a topology of elements, nodes, and interconnect into another representation (e.g., into a physical representation) of the same electrical topology.
- a tool e.g., computer program
- the method includes an operation 201 for reading the meta-data object.
- the method proceeds with an operation 203 for reading the technology description, such as that provided by information within a technology file.
- the method then proceeds with an initialization operation 205 to set a counter variable “J” equal to one.
- an operation 207 the transistor corresponding to the current counter value, i.e., the J-th transistor, is placed in the layout.
- a decision operation 209 is performed to determine whether or not all transistors have been placed in the layout. If more transistors need to be placed in the layout, the method proceeds from the decision operation 209 to an operation 211 , in which the counter variable “J” is incremented by one. Then, the method proceeds back to operation 207 for placing the current (J-th) transistor. If decision operation 209 determines that all transistors have been placed in the layout, the method proceeds from decision operation 209 to an operation 213 , in which the variable counter is reset to one.
- Operation 213 is the beginning of the interconnection of nodes. From the operation 213 , the method proceeds with an operation 215 for connecting DGSB (Drain, Gate, Source, Bulk) of the current transistor as identified by the counter variable J (i.e., the J-th transistor). Then, a decision operation 217 is performed to determine whether or not DGSB has been connected for all transistors. If more transistors need to be DGSB connected in the layout, the method proceeds from the decision operation 217 to an operation 219 , in which the counter variable “J” is incremented by one. Then, the method proceeds back to operation 215 for connecting DGSB of the current (J-th) transistor. If decision operation 217 determines that all transistors have been DGSB connected in the layout, the method proceeds from decision operation 217 to an operation 221 , in which fill and/or dummy shapes are added to the layout, if necessary.
- DGSB Drain, Gate, Source, Bulk
- FIG. 3 shows a plan view of the two input NAND gate of Table 2 and FIG. 1 with the placements of the diffusion ( 345 , 347 , 341 , 343 ) and linear conductive structures ( 351 , 353 ) that form gate electrodes of the four transistors m1, m2, m3, m4, in accordance with one embodiment of the present invention.
- FIG. 3 shows the output of the layout generator of the method of FIG. 2 , as applied to the two input NAND gate, just prior to operation 213 .
- the layout generator has found four transistors (m1, m2, m3, m4) and placed their centers at the coordinates specified by the meta-data.
- the diffusions ( 345 , 347 , 341 , 343 ) have been extended past the gate-space centerlines depending on the “type” of the transistor diffusion or “active” region.
- the linear conductive structures ( 351 , 353 ) have been extended vertically across the cell since the gate electrodes of transistors m1 and m2 share linear conductive structure 351 , and the gate electrodes of transistors m3 and m4 share linear conductive structure 353 .
- an x-y grid defined by x-direction lines 301 - 321 and y-direction lines 331 - 337 is shown in FIG. 3 to aid visualizing where the physical elements will be placed.
- FIG. 4 shows a plan view of the two input NAND gate with the addition of a VSS rail 465 , and a gate connection formed by a gate contact 463 and a metal-1 structure 461 , in accordance with one embodiment of the present invention.
- the drain 341 b of transistor m1 is connected by diffusion to the source 343 a of transistor m3, so nothing needs to be added for connection of the drain 341 of transistor m1.
- the gate of transistor m1 is contacted by metal-1 line 5 (Met1-5), so the contact 463 and metal-1 structure 461 are placed into the layout as shown in FIG. 4 .
- the horizontal dimension of the metal-1 structure 461 is determined by both the technology file physical rules as well as the technology file guidelines, such as “metal-1 line used for a cell pin must cross at least 2 metal-2 tracks.”
- the source 341 a of transistor m1 is connected to VSS, which is defined in the technology file as a metal-1 structure in the bottom track (Met1-1). This is illustrated as VSS rail 465 in FIG. 4 . To allow scalability, the power supply connection is technology dependent.
- FIG. 5 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a metal-1 vertical structure 523 and a diffusion contact 525 , in accordance with one embodiment of the present invention.
- the metal-1 structure 523 is a vertical stub from metal-1 structure 465 .
- the diffusion contact 525 connects the metal-1 structure 523 to the diffusion region 341 a .
- This metal-1 construction may be allowed in technologies of 32 nm and larger, but may not be allowed for smaller technology nodes because of the difficulty in making the bend in the metal-1 pattern.
- FIG. 6 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a diffusion structure 623 and a diffusion contact 625 , in accordance with one embodiment of the present invention.
- the diffusion structure 623 is contiguous with the diffusion region 341 a .
- the diffusion contact 625 extends vertically to connect with both the diffusion structure 623 and the metal-1 structure 465 .
- This metal-1 construction may be allowed in technologies of 40 nm and larger, but may not be allowed for smaller technology nodes because of the difficulty in making the bend in the diffusion pattern.
- FIG. 7 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a local-interconnect structure 723 and a contact structure 725 , in accordance with one embodiment of the present invention.
- the local-interconnect structure 723 is electrically connected to the diffusion region 341 a .
- the contact structure 725 extends vertically to connect with both the local-interconnect structure 723 and the metal-1 structure 465 .
- This construction is highly scalable since it involves a simple rectangular pattern for the local-interconnect structure 723 .
- the local-interconnect structure 723 can be self-aligned to the gate electrodes or photo-aligned to create the pattern shown in FIG. 7 .
- FIG. 8 shows a plan view of the two input NAND gate with all the connections made, in accordance with one embodiment of the present invention.
- local interconnect is used to connect the power rails to the transistors m1, m2, and m4.
- FIG. 7 shows the local-interconnect connection between VSS rail 465 and transistor m1.
- Diffusion region 345 a of transistor m2 is connected by local-interconnect structure 863 and contact structure 864 to VDD structure 856 .
- diffusion region 347 b of transistor m4 is connected by local-interconnect structure 865 and contact structure 866 to VDD structure 856 .
- the gates of transistors m3 and m4 are connected to metal-1 structure 853 by gate contact 854 .
- the metal-1 structure 853 is connected to input pin B 113 .
- the gates of transistors m1 and m2 are connected to metal-1 structure 461 by gate contact 463 .
- the metal-1 structure 461 is connected to input pin A 111 .
- Drain nodes of transistors m3, m2, and m4 are tied to metal-1 lines 3 and 9, i.e., Met1-3 and Met1-9, and are listed in the meta-data.
- the diffusion region 343 b of transistor m3 is connected to the shared diffusion node of transistors m2 and m4 (formed by diffusion regions 345 b and 347 a ), by connections through both metal-1 and metal-2 structures.
- the diffusion region 343 b is connected to the metal-1 structure 871 by diffusion contact 872 .
- the metal-1 structure 871 is in turn connected to the metal-2 structure 875 by via 877 .
- the diffusion contact 872 and via 877 is a stacked contact/via structure.
- the metal-2 structure 875 is connected to the metal-1 structure 873 by via 876 .
- the metal-1 structure 873 is connected to the shared diffusion node (formed by diffusion regions 345 b and 347 a ) by diffusion contact 874 .
- the connection between the diffusion region 343 b of transistor m3 and the shared diffusion node of transistors m2 and m4 (formed by diffusion regions 345 b and 347 a ) is connected to the output pin Y 115 .
- the layout generator for the technology file in the example of FIG. 8 used a metal-2 jumper and chose the available track 336 to form the above-described output connection.
- the layout generator could have used track 334 for the metal-2 jumper in the output connection.
- the layout generator could have chosen to not put a hard metal-2 structure in the layout for the output connection, but could have put a “must connect” instruction in the .LEF file to complete the connection with a metal-2 track available to the router.
- FIG. 9 shows a plan view of the two input NAND gate with all the connections made, in accordance with another embodiment of the present invention.
- the local interconnect structure 975 connects the diffusion region 343 b of transistor m3 to the metal-1 structure 971 , by way of contact structure 972 .
- the local-interconnect structure 977 connects the shared diffusion node (formed by diffusion regions 345 b and 347 a ) to the metal-1 structure 971 , by way of contact structure 976 .
- the metal-1 structure 971 is chosen to go in an unused metal-1 track 6 (Met1-6).
- metal-1 structure 973 and diffusion contact 974 are used to create the output connection to output pin Y 115 , as instructed by the “#” symbol appended to track assignments in the meta-data file of Table 2.
- the input and output pin nodes, as formed by metal-1 structures 461 , 853 , and 973 are made as wide as possible to give more connection points for the cell.
- modified SPICE netlist of Table 2 is further extended to include the following information:
- Table 3 shows an example of a meta-file portion for a buffer circuit that included information for cell height in Metal-1 tracks, input and output pins combined into “signal” pins, node name added to each interconnect segment, and abstract interconnect constructs (CMC, H2M1, LVC).
- the abstract interconnect constructs are used to construct interconnect in different ways depending on the technology.
- a CMC could be implemented with a single local interconnect (LI) line, or it could be implemented without LI using two contacts, two Metal-1 lines, two via-1's, and one Metal-2 line.
- LI local interconnect
- the choice is made at “run time” based on switches or parameters in the technology file.
- An H2M1 is used when a vertical line is connected to a horizontal Metal-1 line. If the vertical line is LI, then an H2M1 is implemented with a contact. If the vertical line is Metal-2, then the H2M1 is implemented with a Via-1.
- An LVC is used for a vertical line which does not connect NMOS and PMOS transistors or a pin “port.”
- the port text is implemented in the LI text layer. If the “z” CMC is implemented in Metal-2, then the port text is implemented in the Metal-2 text layer.
- FIG. 10 shows a plan view of an inverter with all connections made, in accordance with one embodiment of the present invention.
- the inverter includes diffusion regions 1041 and 1043 , and a linear conductive structure 1045 that forms gate electrodes of the two transistors m1 and m2.
- An x-y grid defined by x-direction lines 1001 - 1021 and y-direction lines 1031 - 1035 is shown in FIG. 10 to aid with visualizing where the physical elements are placed.
- the inverter includes a power rail formed by a Metal-1 structure 1051 positioned along the Met1-1 line.
- the power rail structure 1051 is electrically connected to the diffusion region 1041 a of transistor m1 by a contact 1061 and a local interconnect structure 1071 .
- the inverter includes a power rail formed by a Metal-1 structure 1056 positioned along the Met1-11 line.
- the power rail structure 1056 is electrically connected to the diffusion region 1043 a of transistor m2 by a contact 1065 and a local interconnect structure 1073 . If the diffusion region 1041 is of n-type and the diffusion region 1043 is of p-type, then the power rail 1051 is connected to a reference ground and the power rail 1056 is connected to a power supply. If the diffusion region 1041 is of p-type and the diffusion region 1043 is of n-type, then the power rail 1051 is connected to a power supply and the power rail 1056 is connected to a reference ground.
- the inverter includes an input formed by a Metal-1 structure 1053 positioned along the Met1-5 line.
- the Metal-1 structure 1053 is electrically connected to the linear conductive structure 1045 by a contact 1063 .
- the linear conductive structure 1045 forms the gates of transistors m1 and m2 where it crosses diffusion regions 1041 and 1043 , respectively.
- the inverter also includes an output node formed by a local interconnect structure 1082 .
- An electrical connection to the output node is provided by a Metal-1 structure 1054 through contact 1081 .
- the CMOS connector (CMC) in the inverter of FIG. 10 is formed by the local interconnect structure 1082 .
- the hole-to-Metal-1 (H2M1) in the inverter of FIG. 10 is formed by the contact 1081 .
- FIG. 11 shows a variation of the plan view of the inverter of FIG. 10 , in accordance with one embodiment of the present invention.
- the electrical connection to the output node is provided by a Metal-1 structure 1154 .
- the Metal-1 structure 1154 is electrically connected to diffusion region 1041 b through a via 1181 , connected to a Metal-2 structure 1182 , connected to a via 1162 , connected to a Metal-1 structure 1152 , connected to a contact vertically stacked beneath the via 1162 , with the contact connected to the diffusion region 1041 b .
- the Metal-1 structure 1154 is also electrically connected to diffusion region 1043 b through the via 1181 , connected to the Metal-2 structure 1182 , connected to a via 1164 , connected to a Metal-1 structure 1155 , connected to a contact vertically stacked beneath the via 1164 , with the contact connected to the diffusion region 1043 b .
- the CMOS connector (CMC) in the inverter of FIG. 11 is formed by the contacts beneath the vias 1162 and 1164 , and by the Metal-1 structures 1152 and 1155 , and by the vias 1162 and 1164 , and by the Metal-2 structure 1182 .
- the hole-to-Metal-1 (H2M1) in the inverter of FIG. 11 is formed by the via 1181 .
- the layout generator can connect nodes as required by the netlist, but the choice of interconnect approach and location of the interconnects is technology dependent.
- the figures discussed herein illustrate the layout solution for a one-dimensional gridded design style, but bent or two-dimensional shapes are also supported as illustrated in the power supply connection options of FIGS. 5 and 6 .
- Logic cells with functionality less complex and more complex than a two input NAND gate or inverter can be described in a similar fashion by the meta-data to instruct the layout generator on how to place and interconnect devices.
- meta-data can be extended to describe other components which can be included in a SPICE netlist. Since different technology file sections may be selected for different portions of a circuit, for example analog or input-output circuits, these circuit regions can be identified in the meta-data file to allow the generator to produce corresponding layout regions with different design rules.
- layout generator and corresponding methods of the present invention can be extended to systems which include components at a higher level of complexity, along with interconnect that are technology dependent. Also, the layout generator method of the present invention can be further extended to any system which can be described by a list of components and the nets which interconnect them, with an implementation defined by a technology file.
- the layout generator and associated methods of the present invention provide:
- FIG. 12 shows a flowchart of a method for defining an integrated circuit, in accordance with one embodiment of the present invention.
- the method includes an operation 1201 for generating a digital data file that includes both electrical connection information for a number of circuit components and physical topology information for the number of circuit components.
- the method also includes an operation 1203 for operating a computer to execute a layout generation program, whereby the layout generation program reads the electrical connection information and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file.
- the method further includes an operation 1205 for operating the computer to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.
- the number of circuit components include a number of transistors.
- the physical topology information for one or more of the number of transistors includes a transistor width, a transistor channel length, a transistor center location in a first direction, and a transistor center location in a second direction perpendicular to the first direction, wherein the first direction extends perpendicular to the transistor width.
- the transistor width is specified as a fractional multiple of a metal-1 structure pitch.
- the transistor channel length is specified as a fractional multiple of a minimum channel length allowed by design rules of the semiconductor device fabrication process.
- the transistor center location in the first direction is specified as a particular transistor gate electrode track number.
- the transistor center location in the second direction is specified as a fractional multiple of a metal-1 structure pitch.
- the physical topology information for one or more of the number of transistors further includes a drain connection center location in the second direction, a gate connection center location in the second direction, and a source connection center location in the second direction.
- each of the drain, gate, and source center locations in the second direction is specified as a fractional multiple of a higher-level metal structure pitch.
- the physical topology information for one or more of the number of transistors further includes a transistor diffusion region extension specification in the first direction. It should be understood, however, that in other embodiments of the method, the digital data file can include essentially any additional physical topology information not explicitly identified herein.
- the method of FIG. 12 also includes an operation for generating a digital technology file that includes physical dimensions corresponding to a number of variables used for physical topology information in the digital data file.
- the layout generation program reads the physical dimensions from the digital technology file and substitutes the physical dimensions for the corresponding variables in the physical topology information in the digital data file.
- the method can further includes an operation for adjusting the physical dimensions within the digital technology file without adjusting the corresponding variables in the physical topology information in the digital data file.
- FIG. 13 shows a system 1300 for defining an integrated circuit, in accordance with one embodiment of the present invention.
- the system 1300 includes a computer system 1301 including a processor 1303 and a memory 1305 .
- the system 1300 also includes a digital data file 1307 stored in the memory 1305 .
- the digital data file 1307 includes both electrical connection information for a number of circuit components and physical topology information for the number of circuit components.
- the system 1300 further includes a layout generation program 1309 stored as a set of computer executable instructions in the memory 1305 .
- the layout generation program 1309 is defined to read the electrical connection information and physical topology information for each of the number of circuit components from the digital data file 1307 and automatically create a digital representation of one or more layout structures 1311 necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file 1307 .
- the layout generation program 1309 is further defined to store the digital representation of the one or more automatically created layout structures 1311 in a digital format on a computer readable medium 1313 .
- the system 1300 also includes a digital technology file 1315 stored in the memory 1305 .
- the digital technology file 1315 includes physical dimensions corresponding to a number of variables used for physical topology information in the digital data file 1307 .
- the layout generation program 1309 is defined to read the physical dimensions from the digital technology file 1315 and substitute the physical dimensions for the corresponding variables in the physical topology information in the digital data file 1307 .
- the number of circuit components include a number of transistors.
- the physical topology information for one or more of the number of transistors includes a transistor width, a transistor channel length, a transistor center location in a first direction, and a transistor center location in a second direction perpendicular to the first direction, wherein the first direction extends perpendicular to the transistor width.
- the transistor width is specified as a fractional multiple of a metal-1 structure pitch.
- the transistor channel length is specified as a fractional multiple of a minimum channel length allowed by design rules of the semiconductor device fabrication process.
- the transistor center location in the first direction is specified as a particular transistor gate electrode track number.
- the transistor center location in the second direction is specified as a fractional multiple of a metal-1 structure pitch.
- the physical topology information for one or more of the number of transistors further includes a drain connection center location in the second direction, a gate connection center location in the second direction, and a source connection center location in the second direction.
- each of the drain, gate, and source center locations in the second direction is specified as a fractional multiple of a higher-level metal structure pitch.
- the physical topology information for one or more of the number of transistors further includes a transistor diffusion region extension specification in the first direction. It should be understood, however, that in other embodiments of the system 1300 , the digital data file can include essentially any additional physical topology information not explicitly identified herein.
- the invention described herein can be embodied as computer readable code on a computer readable medium.
- the computer readable code can include computer executable program instructions for operating the layout generator.
- the computer readable code can also include program instructions for generating layout libraries and/or cells can also be stored in a digital format on a computer readable medium.
- the computer readable medium mentioned herein is any data storage device that can store data which can thereafter be read by a computer system.
- Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices.
- the computer readable medium can also be distributed over a network of coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
- the invention also relates to a device or an apparatus for performing these operations.
- the apparatus may be specially constructed for the required purpose, such as a special purpose computer.
- the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.
- the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or obtained over a network. When data is obtained over a network the data may be processed by other computers on the network, e.g., a cloud of computing resources.
- the embodiments of the present invention can also be defined as a machine that transforms data from one state to another state.
- the data may represent an article, that can be represented as an electronic signal and electronically manipulate data.
- the transformed data can, in some cases, be visually depicted on a display, representing the physical object that results from the transformation of data.
- the transformed data can be saved to storage generally, or in particular formats that enable the construction or depiction of a physical and tangible object.
- the manipulation can be performed by a processor.
- the processor thus transforms the data from one thing to another.
- the methods can be processed by one or more machines or processors that can be connected over a network. Each machine can transform data from one state or thing to another, and can also process data, save data to storage, transmit data over a network, display the result, or communicate the result to another machine.
- the layouts generated by the layout generator and associated methods disclosed herein can be manufactured as part of a semiconductor device or chip.
- semiconductor devices such as integrated circuits, memory cells, and the like
- a series of manufacturing operations are performed to define features on a semiconductor wafer.
- the wafer includes integrated circuit devices in the form of multi-level structures defined on a silicon substrate.
- transistor devices with diffusion regions are formed.
- interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device.
- patterned conductive layers are insulated from other conductive layers by dielectric materials.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Architecture (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.
Description
- This application is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 14/481,845, filed Sep. 9, 2014, issued as U.S. Pat. No. 9,589,091, on Mar. 7, 2017, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 13/312,673, filed Dec. 6, 2011, issued as U.S. Pat. No. 8,839,175, on Sep. 16, 2014, which:
-
- a) claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/420,313, filed Dec. 6, 2010, and
- b) is a continuation-in-part application under 35 U.S.C. 120 of prior U.S. application Ser. No. 13/047,474, filed Mar. 14, 2011, issued as U.S. Pat. No. 8,756,551, on Jun. 17, 2014, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/013,356, filed Jan. 11, 2008, issued as U.S. Pat. No. 7,908,578, on Mar. 15, 2011, which claims priority under 35 U.S.C. 119(e) to both U.S. Provisional Patent Application No. 60/972,394, filed Sep. 14, 2007, and U.S. Provisional Patent Application No. 60/963,364, filed Aug. 2, 2007, and
- c) is a continuation-in-part application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/572,225, filed Oct. 1, 2009, issued as U.S. Pat. No. 8,436,400, on May 7, 2013, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/212,562, filed Sep. 17, 2008, issued as U.S. Pat. No. 7,842,975, on Nov. 30, 2010, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 11/683,402, filed Mar. 7, 2007, issued as U.S. Pat. No. 7,446,352, on Nov. 4, 2008, which claims priority under 35 U.S.C. 119(e) to both U.S. Provisional Patent Application No. 60/781,288, filed Mar. 9, 2006. The disclosure of each above-identified patent application and patent is incorporated herein by reference in its entirety for all purposes.
- Currently, integrated circuit (IC) layout is represented by polygons in standard formats like GDS-II (Graphic Data System) and OASIS (Open Artwork System Interchange Standard). Re-use of IC layout has been desired for many years. Because of technology scaling, re-use of IC layout has been limited or not possible. Therefore, the IC layout polygons need to be redrawn each time a technology changes, for example moving to smaller dimensions.
- The Mead and Conway “lambda” rules were an early attempt at scaling, but were not useful outside an academic environment. None of these layout representations comprehend different interconnect structures as circuits scale. Two significant problems with scaling include:
-
- 1. Lithographic resolution is scaling at a different rate from overlay scaling, and
- 2. Device and interconnect structures change because of material properties and/or electric field requirements.
- It is within this context that the present invention arises.
- In one embodiment, a method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information for a number of circuit components and physical topology information for the number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection information and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The method further includes operating the computer to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.
- In one embodiment, a system for defining an integrated circuit is disclosed. The system includes a computer system including a processor and a memory. The system also includes a digital data file stored in the memory. The digital data file includes both electrical connection information for a number of circuit components and physical topology information for the number of circuit components. The system also includes a layout generation program stored as a set of computer executable instructions in the memory. The layout generation program is defined to read the electrical connection information and physical topology information for each of the number of circuit components from the digital data file and automatically create a digital representation of one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The layout generation program is further defined to store the digital representation of the one or more automatically created layout structures in a digital format on a computer readable medium.
- Other aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention.
-
FIG. 1 shows a topological schematic view of the two input NAND gate of Table 2, in accordance with one embodiment of the present invention. -
FIG. 2 shows a flow chart of a method for generating a physical layout from meta-data input, in accordance with one embodiment of the present invention. -
FIG. 3 shows a plan view of the two input NAND gate of Table 2 andFIG. 1 with the placements of the diffusion (345, 347, 341, 343) and linear conductive structures (351, 353) that form gate electrodes of the four transistors m1, m2, m3, m4, in accordance with one embodiment of the present invention. -
FIG. 4 shows a plan view of the two input NAND gate with the addition of aVSS rail 465, and a gate connection formed by agate contact 463 and a metal-1structure 461, in accordance with one embodiment of the present invention. -
FIG. 5 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a metal-1vertical structure 523 and adiffusion contact 525, in accordance with one embodiment of the present invention. -
FIG. 6 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with adiffusion structure 623 and adiffusion contact 625, in accordance with one embodiment of the present invention. -
FIG. 7 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a local-interconnect structure 723 and acontact structure 725, in accordance with one embodiment of the present invention. -
FIG. 8 shows a plan view of the two input NAND gate with all the connections made, in accordance with one embodiment of the present invention. -
FIG. 9 shows a plan view of the two input NAND gate with all the connections made, in accordance with another embodiment of the present invention. -
FIG. 10 shows a plan view of an inverter with all connections made, in accordance with one embodiment of the present invention. -
FIG. 11 shows a variation of the plan view of the inverter ofFIG. 10 , in accordance with one embodiment of the present invention. -
FIG. 12 shows a flowchart of a method for defining an integrated circuit, in accordance with one embodiment of the present invention. -
FIG. 13 shows a system for defining an integrated circuit, in accordance with one embodiment of the present invention. - In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
- By way of example, the invention described herein can use the Tela Innovations, Inc., Dynamic Array Architecture (i.e., gridded design style), as described in U.S. Pat. Nos. 7,446,352 and 7,917,879, each of which is incorporated herein by reference in its entirety. However, it should be understood that the invention is not limited to the Dynamic Array Architecture design style. Also, CMOS transistors are used in the examples described herein, but it should be understood that other components can be handled in an analogous fashion. It should also be noted that the Dynamic Array Architecture can be implemented with a coarse grid in the “x” and “y” directions to facilitate identification of the locations of objects like transistors, contacts, and gaps in lines, i.e., linear conductive structures. The linear conductive structures can be positioned on and/or according to the grids.
- Embodiments of the present invention can provide the following:
-
- a. A data format which is similar to a SPICE netlist but which includes information on where devices are and how they are connected.
- b. A tool, e.g., computer program, which can implement a different device or interconnect technology driven by a technology file input. The tool can be defined as computer executable code stored on a computer readable medium.
- c. An output of the tool which includes design intent information to allow further modification to the layout after cells are placed into a hierarchy such as a block of logic cells.
- d. A tool which can take the design intent information and revise final layout to improve manufacturability. The tool can be defined as computer executable code stored on a computer readable medium.
- Table 1 shows a portion of a SPICE netlist, listing the lines needed for a two input NAND gate identified as a sub-circuit. On the first line, a name is specified for the sub-circuit, followed by identification of input, output, and power supply pins. The four transistors used are identified with one in each line. The SPICE convention for a MOS transistor is “name Drain Gate Source Bulk Model-name Width Length.” Other parameters can also be included. The 4 nodes of the transistor are in the order DGSB.
-
TABLE 1 .subckt t10_nd2d1 a b y vdd vss m1 n1 a vss vss nmos w= 160n 1=20nm2 y a vdd vdd pmos w= 192n 1=20nm3 y b n1 vss nmos w= 160n 1=20nm4 y b vdd vdd pmos w= 192n 1=20n.ends - The netlist of Table 1 is an example, using MOS transistors. Other components like resistors, diodes, bipolar transistors, and MOS transistors with other model names (e.g., to represent transistors with different threshold voltages) can be expected and handled in the same fashion.
- It should be noted that each of the input, output, and power supply pins are connected to nodes of transistors as needed to perform the circuit function. In the example of Table 1, there is one internal node, n1, which has no connection outside the sub-circuit.
- The netlist describes a circuit topology that is quite universal. However, having fixed values for the length and width parameters within the netlist circuit topology limits the scalability of the NAND sub-circuit. The length and width parameters can be replaced by variable values or expressions which are controlled by global parameters within the complete SPICE deck. Also, a similar Verilog-AMS netlist could be used, since it would contain a representation of the components and the topological connections of the nodes.
- In one embodiment of the present invention the SPICE netlist is extended to include additional information for generating a physical topology from the circuit topology. Table 2 shows an example netlist for the two input NAND gate including possible extensions for generating the physical topology, in accordance with one embodiment of the present invention. The initial comments in the netlist explain the new syntax.
-
TABLE 2 * Transistor width in units of metal-1 pitch / 4 * Transistor length in units of the minimum * X values in units of poly tracks (not counting edge dummy poly) * Y values for transistor center in units of metal-1 pitch / 4 * Y values for drain, gate, source connections in units of metal pitch * Transistor type: 0 - (00) no extension past the centerline in X * Transistor type: 1 - (01) extension on the right * Transistor type: 2 - (10) extension on the left * Transistor type: 3 - (11) extension on both sides .subckt t10_nd2d1_s a b y vdd vss m1 n1 a vss vss nmos $w=8 $1=1 $x=1 $y=10 $yg=5# $ys=1 $type=2 m2 y a vdd vdd pmos $w=10 $1=1 $x=1 $y=33 $ys=11 $type=2 m3 y b n1 vss nmos $w=8 $1=1 $x=2 $y=10 $yd=3 $yg=7# $type=1 m4 y b vdd vdd pmos $w=10 $1=1 $x=2 $y=33 $yd=9# $ys=11 $type=1 .ends - It should be noted that width could be in some other simple unit of metal-1 pitch, for example ⅛ or ⅕ of the metal-1 pitch. Also, the length could be specified as coded values. For example, a netlist could specify $1=A for several transistors, and $1=B for other transistors, and $1=C for yet other transistors. The layout generator would use the technology file to build the layout using the appropriate sizes. For example, in one example embodiment, at a 45 nm (nanometer) CMOS technology node, A=40 nm, B=42 nm, C=44 nm. These specific values would exist in the technology file, so the meta-data netlist is still technology independent. In one example embodiment, the A, B, C values of length could be used in variant logic cells needed for power optimization.
-
FIG. 1 shows a topological schematic view of the two input NAND gate of Table 2, in accordance with one embodiment of the present invention. Input pin A is 111. Input pin B is 113. Output pin Y is 115 and is connected to internal node n2, which is 121. VDD is 101. VSS is 103. Internal node n1 is 123. Transistor m1 is 135, and is connected to VSS byconnection 109, and is further connected tointernal node n1 123. Transistor m2 is 131, and is connected to VDD byconnection 107, and is further connected to bothinternal node n2 121 andoutput pin Y 115. Transistor m3 is 137, and is connected tointernal node n1 123, and is further connected to bothoutput pin Y 115 andinternal node n2 121. Transistor m4 is 133, and is connected to VDD byconnection 105, and is further connected to bothinternal node n2 121 andoutput pin Y 115. -
FIG. 2 shows a flow chart of a method for generating a physical layout from meta-data input, in accordance with one embodiment of the present invention. The method ofFIG. 2 can be implemented by a tool (e.g., computer program) which reads meta-data object input, and combines the meta-data object input with information from a technology file to create a physical layout. Because essentially any circuit is formed by components attached to nodes which are interconnected, the method ofFIG. 2 is not limited to CMOS devices. In general, the method ofFIG. 2 can be applied to any mapping of a topology of elements, nodes, and interconnect into another representation (e.g., into a physical representation) of the same electrical topology. - The method includes an
operation 201 for reading the meta-data object. The method proceeds with anoperation 203 for reading the technology description, such as that provided by information within a technology file. The method then proceeds with aninitialization operation 205 to set a counter variable “J” equal to one. In anoperation 207, the transistor corresponding to the current counter value, i.e., the J-th transistor, is placed in the layout. Then, adecision operation 209 is performed to determine whether or not all transistors have been placed in the layout. If more transistors need to be placed in the layout, the method proceeds from thedecision operation 209 to anoperation 211, in which the counter variable “J” is incremented by one. Then, the method proceeds back tooperation 207 for placing the current (J-th) transistor. Ifdecision operation 209 determines that all transistors have been placed in the layout, the method proceeds fromdecision operation 209 to anoperation 213, in which the variable counter is reset to one. -
Operation 213 is the beginning of the interconnection of nodes. From theoperation 213, the method proceeds with anoperation 215 for connecting DGSB (Drain, Gate, Source, Bulk) of the current transistor as identified by the counter variable J (i.e., the J-th transistor). Then, adecision operation 217 is performed to determine whether or not DGSB has been connected for all transistors. If more transistors need to be DGSB connected in the layout, the method proceeds from thedecision operation 217 to anoperation 219, in which the counter variable “J” is incremented by one. Then, the method proceeds back tooperation 215 for connecting DGSB of the current (J-th) transistor. Ifdecision operation 217 determines that all transistors have been DGSB connected in the layout, the method proceeds fromdecision operation 217 to anoperation 221, in which fill and/or dummy shapes are added to the layout, if necessary. -
FIG. 3 shows a plan view of the two input NAND gate of Table 2 andFIG. 1 with the placements of the diffusion (345, 347, 341, 343) and linear conductive structures (351, 353) that form gate electrodes of the four transistors m1, m2, m3, m4, in accordance with one embodiment of the present invention. Also,FIG. 3 shows the output of the layout generator of the method ofFIG. 2 , as applied to the two input NAND gate, just prior tooperation 213. In this example, the layout generator has found four transistors (m1, m2, m3, m4) and placed their centers at the coordinates specified by the meta-data. Note that the diffusions (345, 347, 341, 343) have been extended past the gate-space centerlines depending on the “type” of the transistor diffusion or “active” region. Also note that the linear conductive structures (351, 353) have been extended vertically across the cell since the gate electrodes of transistors m1 and m2 share linearconductive structure 351, and the gate electrodes of transistors m3 and m4 share linearconductive structure 353. Also, an x-y grid defined by x-direction lines 301-321 and y-direction lines 331-337 is shown inFIG. 3 to aid visualizing where the physical elements will be placed. - During the first pass through
operation 215 of the method ofFIG. 2 , the layout generator begins making the connections for transistor m1.FIG. 4 shows a plan view of the two input NAND gate with the addition of aVSS rail 465, and a gate connection formed by agate contact 463 and a metal-1structure 461, in accordance with one embodiment of the present invention. Thedrain 341 b of transistor m1 is connected by diffusion to thesource 343 a of transistor m3, so nothing needs to be added for connection of thedrain 341 of transistor m1. The gate of transistor m1 is contacted by metal-1 line 5 (Met1-5), so thecontact 463 and metal-1structure 461 are placed into the layout as shown inFIG. 4 . The horizontal dimension of the metal-1structure 461 is determined by both the technology file physical rules as well as the technology file guidelines, such as “metal-1 line used for a cell pin must cross at least 2 metal-2 tracks.” - The
source 341 a of transistor m1 is connected to VSS, which is defined in the technology file as a metal-1 structure in the bottom track (Met1-1). This is illustrated asVSS rail 465 inFIG. 4 . To allow scalability, the power supply connection is technology dependent. -
FIG. 5 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a metal-1vertical structure 523 and adiffusion contact 525, in accordance with one embodiment of the present invention. The metal-1structure 523 is a vertical stub from metal-1structure 465. Thediffusion contact 525 connects the metal-1structure 523 to thediffusion region 341 a. This metal-1 construction may be allowed in technologies of 32 nm and larger, but may not be allowed for smaller technology nodes because of the difficulty in making the bend in the metal-1 pattern. -
FIG. 6 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with adiffusion structure 623 and adiffusion contact 625, in accordance with one embodiment of the present invention. Thediffusion structure 623 is contiguous with thediffusion region 341 a. Thediffusion contact 625 extends vertically to connect with both thediffusion structure 623 and the metal-1structure 465. This metal-1 construction may be allowed in technologies of 40 nm and larger, but may not be allowed for smaller technology nodes because of the difficulty in making the bend in the diffusion pattern. -
FIG. 7 shows a portion of the plan view of the two input NAND gate with a VSS connection to the transistor m1 done with a local-interconnect structure 723 and acontact structure 725, in accordance with one embodiment of the present invention. The local-interconnect structure 723 is electrically connected to thediffusion region 341 a. Thecontact structure 725 extends vertically to connect with both the local-interconnect structure 723 and the metal-1structure 465. This construction is highly scalable since it involves a simple rectangular pattern for the local-interconnect structure 723. Additionally, in one embodiment, the local-interconnect structure 723 can be self-aligned to the gate electrodes or photo-aligned to create the pattern shown inFIG. 7 . - It should be understood that a similar set of technology dependent power supply connections can be created in the same fashion as exemplified in
FIGS. 5-7 for other nodes identified in the meta-data. For instance,FIG. 8 shows a plan view of the two input NAND gate with all the connections made, in accordance with one embodiment of the present invention. In the example ofFIG. 8 , local interconnect is used to connect the power rails to the transistors m1, m2, and m4.FIG. 7 shows the local-interconnect connection betweenVSS rail 465 and transistor m1.Diffusion region 345 a of transistor m2 is connected by local-interconnect structure 863 andcontact structure 864 toVDD structure 856. Similarly,diffusion region 347 b of transistor m4 is connected by local-interconnect structure 865 andcontact structure 866 toVDD structure 856. - Also, the gates of transistors m3 and m4 are connected to metal-1
structure 853 bygate contact 854. The metal-1structure 853 is connected to inputpin B 113. Similarly, the gates of transistors m1 and m2 are connected to metal-1structure 461 bygate contact 463. The metal-1structure 461 is connected to inputpin A 111. - Drain nodes of transistors m3, m2, and m4 are tied to metal-1
lines 3 and 9, i.e., Met1-3 and Met1-9, and are listed in the meta-data. Thediffusion region 343 b of transistor m3 is connected to the shared diffusion node of transistors m2 and m4 (formed bydiffusion regions diffusion region 343 b is connected to the metal-1structure 871 bydiffusion contact 872. The metal-1structure 871 is in turn connected to the metal-2structure 875 by via 877. Thediffusion contact 872 and via 877 is a stacked contact/via structure. The metal-2structure 875 is connected to the metal-1structure 873 by via 876. The metal-1structure 873 is connected to the shared diffusion node (formed bydiffusion regions diffusion contact 874. The connection between thediffusion region 343 b of transistor m3 and the shared diffusion node of transistors m2 and m4 (formed bydiffusion regions output pin Y 115. - It should be appreciated that the layout generator for the technology file in the example of
FIG. 8 used a metal-2 jumper and chose theavailable track 336 to form the above-described output connection. In another embodiment, the layout generator could have usedtrack 334 for the metal-2 jumper in the output connection. In yet another embodiment, the layout generator could have chosen to not put a hard metal-2 structure in the layout for the output connection, but could have put a “must connect” instruction in the .LEF file to complete the connection with a metal-2 track available to the router. -
FIG. 9 shows a plan view of the two input NAND gate with all the connections made, in accordance with another embodiment of the present invention. InFIG. 9 , thelocal interconnect structure 975 connects thediffusion region 343 b of transistor m3 to the metal-1 structure 971, by way of contact structure 972. Similarly, the local-interconnect structure 977 connects the shared diffusion node (formed bydiffusion regions contact structure 976. In this example, the metal-1 structure 971 is chosen to go in an unused metal-1 track 6 (Met1-6). Also, the metal-1structure 973 anddiffusion contact 974 are used to create the output connection tooutput pin Y 115, as instructed by the “#” symbol appended to track assignments in the meta-data file of Table 2. The input and output pin nodes, as formed by metal-1structures - In one embodiment of the present invention the modified SPICE netlist of Table 2 is further extended to include the following information:
-
- Additional meta-data, including:
- i. Cell height in Metal-1 tracks added,
- ii. Input and output pins combined into “signal” pins, and
- iii. Node name added to each interconnect segment.
- Addition of abstract interconnect constructs, including:
- i. CMOS Connector (CMC),
- ii. Hole-to-Metal-1 (H2M1), and
- iii. Local Vertical Connector (LVC).
- Addition of components, including:
- i. Well taps,
- ii. Diodes, and
- iii. MOSFETs with different VT or gate oxide thickness.
- Additional meta-data, including:
- Table 3 shows an example of a meta-file portion for a buffer circuit that included information for cell height in Metal-1 tracks, input and output pins combined into “signal” pins, node name added to each interconnect segment, and abstract interconnect constructs (CMC, H2M1, LVC).
- The abstract interconnect constructs are used to construct interconnect in different ways depending on the technology. For example, a CMC could be implemented with a single local interconnect (LI) line, or it could be implemented without LI using two contacts, two Metal-1 lines, two via-1's, and one Metal-2 line. In one embodiment, the choice is made at “run time” based on switches or parameters in the technology file.
- An H2M1 is used when a vertical line is connected to a horizontal Metal-1 line. If the vertical line is LI, then an H2M1 is implemented with a contact. If the vertical line is Metal-2, then the H2M1 is implemented with a Via-1.
- An LVC is used for a vertical line which does not connect NMOS and PMOS transistors or a pin “port.” In the meta-file example of Table 3, if the output “z” CMC is implemented in LI, then the port text is implemented in the LI text layer. If the “z” CMC is implemented in Metal-2, then the port text is implemented in the Metal-2 text layer.
-
TABLE 3 .subckt buf_1x1 a0 z vdd vss * HEIGHT: M1, 10 * signal pins 2 a0, M1, 5, 2 z, LVC, 7, 5 * power supply pins 2 vss, 0 vdd, 10 * metal interconnect nodes 4 a0, 2, M1,5,0,4, CT,5,2 z, 1, CMC,2,2,7 n1, 3, M1,4,0,6, H2M1,4,1, CT,4,4 n1, 1, CMC,0,2,7 * name left gate right bulk model scaledW scaledL Xloc Yloc Type Ydrain Ygate Ysource 4 mn1, n1, a0, vss, vss, nch, 10, A, 1, 10, 2, 2, 5, 0 mn2, vss, n1, z, vss, nch, 20, A, 2, 5, 1, 0, 4, 2 mp1, n1, a0, vdd, vdd, pch, 18, A, 1, 46, 2, 7, 5, 0 mp2, vdd, n1, z, vdd, pch, 35, A, 2, 38, 1, 0, 4, 7 .ends -
FIG. 10 shows a plan view of an inverter with all connections made, in accordance with one embodiment of the present invention. The inverter includesdiffusion regions conductive structure 1045 that forms gate electrodes of the two transistors m1 and m2. An x-y grid defined by x-direction lines 1001-1021 and y-direction lines 1031-1035 is shown inFIG. 10 to aid with visualizing where the physical elements are placed. The inverter includes a power rail formed by a Metal-1structure 1051 positioned along the Met1-1 line. Thepower rail structure 1051 is electrically connected to thediffusion region 1041 a of transistor m1 by acontact 1061 and alocal interconnect structure 1071. The inverter includes a power rail formed by a Metal-1structure 1056 positioned along the Met1-11 line. Thepower rail structure 1056 is electrically connected to thediffusion region 1043 a of transistor m2 by acontact 1065 and alocal interconnect structure 1073. If thediffusion region 1041 is of n-type and thediffusion region 1043 is of p-type, then thepower rail 1051 is connected to a reference ground and thepower rail 1056 is connected to a power supply. If thediffusion region 1041 is of p-type and thediffusion region 1043 is of n-type, then thepower rail 1051 is connected to a power supply and thepower rail 1056 is connected to a reference ground. - The inverter includes an input formed by a Metal-1
structure 1053 positioned along the Met1-5 line. The Metal-1structure 1053 is electrically connected to the linearconductive structure 1045 by a contact 1063. The linearconductive structure 1045 forms the gates of transistors m1 and m2 where it crossesdiffusion regions local interconnect structure 1082. An electrical connection to the output node is provided by a Metal-1structure 1054 throughcontact 1081. The CMOS connector (CMC) in the inverter ofFIG. 10 is formed by thelocal interconnect structure 1082. Also, the hole-to-Metal-1 (H2M1) in the inverter ofFIG. 10 is formed by thecontact 1081. -
FIG. 11 shows a variation of the plan view of the inverter ofFIG. 10 , in accordance with one embodiment of the present invention. InFIG. 11 , the electrical connection to the output node is provided by a Metal-1 structure 1154. The Metal-1 structure 1154 is electrically connected todiffusion region 1041 b through a via 1181, connected to a Metal-2structure 1182, connected to a via 1162, connected to a Metal-1structure 1152, connected to a contact vertically stacked beneath the via 1162, with the contact connected to thediffusion region 1041 b. The Metal-1 structure 1154 is also electrically connected todiffusion region 1043 b through the via 1181, connected to the Metal-2structure 1182, connected to a via 1164, connected to a Metal-1 structure 1155, connected to a contact vertically stacked beneath the via 1164, with the contact connected to thediffusion region 1043 b. The CMOS connector (CMC) in the inverter ofFIG. 11 is formed by the contacts beneath thevias structures 1152 and 1155, and by thevias structure 1182. Also, the hole-to-Metal-1 (H2M1) in the inverter ofFIG. 11 is formed by the via 1181. - It should be noted that the layout generator can connect nodes as required by the netlist, but the choice of interconnect approach and location of the interconnects is technology dependent. The figures discussed herein illustrate the layout solution for a one-dimensional gridded design style, but bent or two-dimensional shapes are also supported as illustrated in the power supply connection options of
FIGS. 5 and 6 . - Logic cells with functionality less complex and more complex than a two input NAND gate or inverter can be described in a similar fashion by the meta-data to instruct the layout generator on how to place and interconnect devices. Also, meta-data can be extended to describe other components which can be included in a SPICE netlist. Since different technology file sections may be selected for different portions of a circuit, for example analog or input-output circuits, these circuit regions can be identified in the meta-data file to allow the generator to produce corresponding layout regions with different design rules.
- It should be appreciated that the layout generator and corresponding methods of the present invention can be extended to systems which include components at a higher level of complexity, along with interconnect that are technology dependent. Also, the layout generator method of the present invention can be further extended to any system which can be described by a list of components and the nets which interconnect them, with an implementation defined by a technology file.
- The layout generator and associated methods of the present invention provide:
-
- 1. A meta-data object describing a circuit or other structure involving components and connections between components, including functional intent.
- 2. A computer executable tool using the meta-data object to create a structure with dimensions provided by a technology file.
- 3. A layout convention which conveys design intent.
- 4. A computer executable tool which can use design intent information to modify patterns to enhance manufacturability.
- 5. A final layout/structure derived from the meta-data object.
- 6. A computer executable tool for creating scaled and dimensioned (with actual dimensions) representations of the circuit defined by the meta-data object, such as a scaled and dimensioned SPICE model, a library exchange format (.LEF) file, and/or a design exchange format (.DEF) file, among others, which may be used by a place-and-route tool to fabricate the circuit.
-
FIG. 12 shows a flowchart of a method for defining an integrated circuit, in accordance with one embodiment of the present invention. The method includes anoperation 1201 for generating a digital data file that includes both electrical connection information for a number of circuit components and physical topology information for the number of circuit components. The method also includes anoperation 1203 for operating a computer to execute a layout generation program, whereby the layout generation program reads the electrical connection information and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The method further includes anoperation 1205 for operating the computer to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium. - In one embodiment, the number of circuit components include a number of transistors. And, the physical topology information for one or more of the number of transistors includes a transistor width, a transistor channel length, a transistor center location in a first direction, and a transistor center location in a second direction perpendicular to the first direction, wherein the first direction extends perpendicular to the transistor width. In one embodiment, the transistor width is specified as a fractional multiple of a metal-1 structure pitch. In one embodiment, the transistor channel length is specified as a fractional multiple of a minimum channel length allowed by design rules of the semiconductor device fabrication process. In one embodiment, the transistor center location in the first direction is specified as a particular transistor gate electrode track number. In one embodiment, the transistor center location in the second direction is specified as a fractional multiple of a metal-1 structure pitch.
- Also, in one embodiment, the physical topology information for one or more of the number of transistors further includes a drain connection center location in the second direction, a gate connection center location in the second direction, and a source connection center location in the second direction. In one embodiment, each of the drain, gate, and source center locations in the second direction is specified as a fractional multiple of a higher-level metal structure pitch. Additionally, in one embodiment, the physical topology information for one or more of the number of transistors further includes a transistor diffusion region extension specification in the first direction. It should be understood, however, that in other embodiments of the method, the digital data file can include essentially any additional physical topology information not explicitly identified herein.
- In one embodiment, the method of
FIG. 12 also includes an operation for generating a digital technology file that includes physical dimensions corresponding to a number of variables used for physical topology information in the digital data file. In this embodiment, the layout generation program reads the physical dimensions from the digital technology file and substitutes the physical dimensions for the corresponding variables in the physical topology information in the digital data file. Also, in this embodiment, the method can further includes an operation for adjusting the physical dimensions within the digital technology file without adjusting the corresponding variables in the physical topology information in the digital data file. -
FIG. 13 shows asystem 1300 for defining an integrated circuit, in accordance with one embodiment of the present invention. Thesystem 1300 includes acomputer system 1301 including aprocessor 1303 and amemory 1305. Thesystem 1300 also includes a digital data file 1307 stored in thememory 1305. The digital data file 1307 includes both electrical connection information for a number of circuit components and physical topology information for the number of circuit components. Thesystem 1300 further includes alayout generation program 1309 stored as a set of computer executable instructions in thememory 1305. Thelayout generation program 1309 is defined to read the electrical connection information and physical topology information for each of the number of circuit components from the digital data file 1307 and automatically create a digital representation of one ormore layout structures 1311 necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file 1307. Thelayout generation program 1309 is further defined to store the digital representation of the one or more automatically createdlayout structures 1311 in a digital format on a computerreadable medium 1313. - In one embodiment, the
system 1300 also includes adigital technology file 1315 stored in thememory 1305. Thedigital technology file 1315 includes physical dimensions corresponding to a number of variables used for physical topology information in the digital data file 1307. Thelayout generation program 1309 is defined to read the physical dimensions from thedigital technology file 1315 and substitute the physical dimensions for the corresponding variables in the physical topology information in the digital data file 1307. - In one embodiment of the
system 1300, the number of circuit components include a number of transistors. And, in one embodiment, the physical topology information for one or more of the number of transistors includes a transistor width, a transistor channel length, a transistor center location in a first direction, and a transistor center location in a second direction perpendicular to the first direction, wherein the first direction extends perpendicular to the transistor width. In one embodiment, the transistor width is specified as a fractional multiple of a metal-1 structure pitch. In one embodiment, the transistor channel length is specified as a fractional multiple of a minimum channel length allowed by design rules of the semiconductor device fabrication process. In one embodiment, the transistor center location in the first direction is specified as a particular transistor gate electrode track number. In one embodiment, the transistor center location in the second direction is specified as a fractional multiple of a metal-1 structure pitch. - Also, in one embodiment of the
system 1300, the physical topology information for one or more of the number of transistors further includes a drain connection center location in the second direction, a gate connection center location in the second direction, and a source connection center location in the second direction. In one embodiment, each of the drain, gate, and source center locations in the second direction is specified as a fractional multiple of a higher-level metal structure pitch. Additionally, in one embodiment of thesystem 1300, the physical topology information for one or more of the number of transistors further includes a transistor diffusion region extension specification in the first direction. It should be understood, however, that in other embodiments of thesystem 1300, the digital data file can include essentially any additional physical topology information not explicitly identified herein. - It should be understood that in one embodiment the invention described herein can be embodied as computer readable code on a computer readable medium. For example, the computer readable code can include computer executable program instructions for operating the layout generator. The computer readable code can also include program instructions for generating layout libraries and/or cells can also be stored in a digital format on a computer readable medium.
- The computer readable medium mentioned herein is any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network of coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
- Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purpose, such as a special purpose computer. When defined as a special purpose computer, the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose. Alternatively, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or obtained over a network. When data is obtained over a network the data may be processed by other computers on the network, e.g., a cloud of computing resources.
- The embodiments of the present invention can also be defined as a machine that transforms data from one state to another state. The data may represent an article, that can be represented as an electronic signal and electronically manipulate data. The transformed data can, in some cases, be visually depicted on a display, representing the physical object that results from the transformation of data. The transformed data can be saved to storage generally, or in particular formats that enable the construction or depiction of a physical and tangible object. In some embodiments, the manipulation can be performed by a processor. In such an example, the processor thus transforms the data from one thing to another. Still further, the methods can be processed by one or more machines or processors that can be connected over a network. Each machine can transform data from one state or thing to another, and can also process data, save data to storage, transmit data over a network, display the result, or communicate the result to another machine.
- It should be further understood that the layouts generated by the layout generator and associated methods disclosed herein can be manufactured as part of a semiconductor device or chip. In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on a semiconductor wafer. The wafer includes integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
- While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention.
Claims (1)
1. An integrated circuit, comprising:
a first diffusion region having a size measured in a first direction in units of a first interconnect level pitch, the first diffusion region having a size measured in a second direction in units of one-quarter of a gate electrode pitch;
a second diffusion region having a size measured in the first direction in units of the first interconnect level pitch, the second diffusion region having a size measured in the second direction in units of one-quarter of the gate electrode pitch;
a gate electrode structure having a linear shape and a lengthwise centerline oriented in the first direction and positioned in accordance with the gate electrode pitch, the gate electrode structure positioned between the first diffusion region and the second diffusion region, the gate electrode structure having a length measured in the first direction in units of one-half of the first interconnect level pitch, the gate electrode structure having a width measured in the second direction to extend from the first diffusion region to the second diffusion region;
a local interconnect structure formed to physically contact the first diffusion region, the local interconnect structure having a size measured in the first direction that is at least as large as the first interconnect level pitch, the local interconnect structure having a size measured in the second direction in units of one-quarter of the gate electrode pitch;
a first interconnect level structure having a linear shape and a lengthwise centerline oriented in the second direction and positioned in accordance with the first interconnect level pitch; and
a contact structure extending between the local interconnect structure and the first interconnect level structure, the contact structure physically contacting both the local interconnect structure and the first interconnect level structure, the contact structure positioned in accordance with one-half of the gate electrode pitch.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/452,364 US20170177779A1 (en) | 2006-03-09 | 2017-03-07 | Integrated Circuit Implementing Scalable Meta-Data Objects |
Applications Claiming Priority (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US78128806P | 2006-03-09 | 2006-03-09 | |
US11/683,402 US7446352B2 (en) | 2006-03-09 | 2007-03-07 | Dynamic array architecture |
US96336407P | 2007-08-02 | 2007-08-02 | |
US97239407P | 2007-09-14 | 2007-09-14 | |
US12/013,356 US7908578B2 (en) | 2007-08-02 | 2008-01-11 | Methods for designing semiconductor device with dynamic array section |
US12/212,562 US7842975B2 (en) | 2006-03-09 | 2008-09-17 | Dynamic array architecture |
US12/572,225 US8436400B2 (en) | 2006-03-09 | 2009-10-01 | Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length |
US42031310P | 2010-12-06 | 2010-12-06 | |
US13/047,474 US8756551B2 (en) | 2007-08-02 | 2011-03-14 | Methods for designing semiconductor device with dynamic array section |
US13/312,673 US8839175B2 (en) | 2006-03-09 | 2011-12-06 | Scalable meta-data objects |
US14/481,845 US9589091B2 (en) | 2006-03-09 | 2014-09-09 | Scalable meta-data objects |
US15/452,364 US20170177779A1 (en) | 2006-03-09 | 2017-03-07 | Integrated Circuit Implementing Scalable Meta-Data Objects |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/481,845 Continuation US9589091B2 (en) | 2006-03-09 | 2014-09-09 | Scalable meta-data objects |
Publications (1)
Publication Number | Publication Date |
---|---|
US20170177779A1 true US20170177779A1 (en) | 2017-06-22 |
Family
ID=46163484
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/312,673 Expired - Fee Related US8839175B2 (en) | 2006-03-09 | 2011-12-06 | Scalable meta-data objects |
US14/481,845 Expired - Fee Related US9589091B2 (en) | 2006-03-09 | 2014-09-09 | Scalable meta-data objects |
US15/452,364 Abandoned US20170177779A1 (en) | 2006-03-09 | 2017-03-07 | Integrated Circuit Implementing Scalable Meta-Data Objects |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/312,673 Expired - Fee Related US8839175B2 (en) | 2006-03-09 | 2011-12-06 | Scalable meta-data objects |
US14/481,845 Expired - Fee Related US9589091B2 (en) | 2006-03-09 | 2014-09-09 | Scalable meta-data objects |
Country Status (1)
Country | Link |
---|---|
US (3) | US8839175B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190096909A1 (en) * | 2017-09-28 | 2019-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Local interconnect structure |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8839175B2 (en) * | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
KR101749351B1 (en) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8893069B2 (en) * | 2011-10-07 | 2014-11-18 | Synopsys, Inc. | Method of schematic driven layout creation |
US8832632B1 (en) * | 2011-10-27 | 2014-09-09 | Synopsys Taiwan Co., LTD. | Compact routing |
US9031975B2 (en) | 2012-11-06 | 2015-05-12 | Rockwell Automation Technologies, Inc. | Content management |
US9355193B2 (en) * | 2012-11-06 | 2016-05-31 | Rockwell Automation Technologies, Inc. | Object design data model |
US9563861B2 (en) | 2012-11-06 | 2017-02-07 | Rockwell Automation Technologies, Inc. | Integration of workflow and library modules |
US10037397B2 (en) | 2014-06-23 | 2018-07-31 | Synopsys, Inc. | Memory cell including vertical transistors and horizontal nanowire bit lines |
US9400862B2 (en) | 2014-06-23 | 2016-07-26 | Synopsys, Inc. | Cells having transistors and interconnects including nanowires or 2D material strips |
US9361418B2 (en) | 2014-06-23 | 2016-06-07 | Synopsys, Inc. | Nanowire or 2D material strips interconnects in an integrated circuit cell |
US9378320B2 (en) | 2014-06-23 | 2016-06-28 | Synopsys, Inc. | Array with intercell conductors including nanowires or 2D material strips |
US10147714B2 (en) * | 2016-10-10 | 2018-12-04 | Globalfoundries Inc. | Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell |
US10312229B2 (en) | 2016-10-28 | 2019-06-04 | Synopsys, Inc. | Memory cells including vertical nanowire transistors |
TWI625640B (en) * | 2017-05-18 | 2018-06-01 | 和碩聯合科技股份有限公司 | Data processing method for generating a relay file for different computer-aided design softwares and related data processing system |
US11030372B2 (en) | 2018-10-31 | 2021-06-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for generating layout diagram including cell having pin patterns and semiconductor device based on same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5756385A (en) * | 1994-03-30 | 1998-05-26 | Sandisk Corporation | Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
US20040245547A1 (en) * | 2003-06-03 | 2004-12-09 | Hitachi Global Storage Technologies B.V. | Ultra low-cost solid-state memory |
US20070211521A1 (en) * | 2006-02-28 | 2007-09-13 | Atsushi Kawasumi | Semiconductor memory device |
US20090159950A1 (en) * | 2007-12-20 | 2009-06-25 | Hitachi, Ltd. | Semiconductor Device and manufacturing Method of Semiconductor Device |
Family Cites Families (661)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4069493A (en) | 1970-10-02 | 1978-01-17 | Thomson-Csf | Novel integrated circuit and method of manufacturing same |
US4197555A (en) | 1975-12-29 | 1980-04-08 | Fujitsu Limited | Semiconductor device |
JPS5746536A (en) | 1980-09-04 | 1982-03-17 | Matsushita Electric Ind Co Ltd | Gate circuit |
US4424460A (en) | 1981-07-14 | 1984-01-03 | Rockwell International Corporation | Apparatus and method for providing a logical exclusive OR/exclusive NOR function |
JPS5943824B2 (en) | 1982-03-03 | 1984-10-24 | 三菱電機株式会社 | Semiconductor integrated circuit device |
JPS58182242U (en) | 1982-05-28 | 1983-12-05 | パイオニア株式会社 | Push button with slide lock |
JPS58215827A (en) | 1982-06-09 | 1983-12-15 | Toshiba Corp | Logical circuit |
JPS5943548A (en) | 1982-09-06 | 1984-03-10 | Hitachi Ltd | Semiconductor integrated circuit device |
US4613940A (en) | 1982-11-09 | 1986-09-23 | International Microelectronic Products | Method and structure for use in designing and building electronic systems in integrated circuits |
JPS6035532A (en) | 1983-07-29 | 1985-02-23 | Fujitsu Ltd | Master slice integrated circuit device |
US4575648A (en) | 1983-12-23 | 1986-03-11 | At&T Bell Laboratories | Complementary field effect transistor EXCLUSIVE OR logic gates |
US5121186A (en) | 1984-06-15 | 1992-06-09 | Hewlett-Packard Company | Integrated circuit device having improved junction connections |
US5545904A (en) | 1986-01-17 | 1996-08-13 | Quick Technologies Ltd. | Personalizable gate array devices |
US4975756A (en) | 1985-05-01 | 1990-12-04 | Texas Instruments Incorporated | SRAM with local interconnect |
US4657628A (en) | 1985-05-01 | 1987-04-14 | Texas Instruments Incorporated | Process for patterning local interconnects |
US4804636A (en) | 1985-05-01 | 1989-02-14 | Texas Instruments Incorporated | Process for making integrated circuits having titanium nitride triple interconnect |
JPH0216605Y2 (en) | 1985-05-02 | 1990-05-08 | ||
US4602270A (en) | 1985-05-17 | 1986-07-22 | United Technologies Corporation | Gate array with reduced isolation |
US5097422A (en) | 1986-10-10 | 1992-03-17 | Cascade Design Automation Corporation | Method and apparatus for designing integrated circuits |
US4745084A (en) | 1986-11-12 | 1988-05-17 | Vlsi Technology, Inc. | Method of making a customized semiconductor integrated device |
US4884115A (en) | 1987-02-27 | 1989-11-28 | Siemens Aktiengesellschaft | Basic cell for a gate array arrangement in CMOS Technology |
US4801986A (en) | 1987-04-03 | 1989-01-31 | General Electric Company | Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method |
JP2742052B2 (en) | 1987-06-12 | 1998-04-22 | 日本電信電話株式会社 | Complementary MIS master slice logic integrated circuit |
US5119313A (en) * | 1987-08-04 | 1992-06-02 | Texas Instruments Incorporated | Comprehensive logic circuit layout system |
KR100212098B1 (en) | 1987-09-19 | 1999-08-02 | 가나이 쓰도무 | Semiconductor integrated circuit device and manufacturing method thereof, wiring board of semiconductor integrated circuit device and manufacturing method thereof |
US5068603A (en) | 1987-10-07 | 1991-11-26 | Xilinx, Inc. | Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays |
US4812688A (en) | 1987-12-30 | 1989-03-14 | International Business Machines Corporation | Transistor delay circuits |
JPH01284115A (en) | 1988-05-11 | 1989-11-15 | Sharp Corp | Logical circuit |
US5268319A (en) | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
US4928160A (en) | 1989-01-17 | 1990-05-22 | Ncr Corporation | Gate isolated base cell structure with off-grid gate polysilicon pattern |
JPH02198154A (en) | 1989-01-27 | 1990-08-06 | Hitachi Ltd | Method of forming wiring and semiconductor device utilizing same |
US5224057A (en) | 1989-02-28 | 1993-06-29 | Kabushiki Kaisha Toshiba | Arrangement method for logic cells in semiconductor IC device |
US5351197A (en) | 1989-04-13 | 1994-09-27 | Cascade Design Automation Corporation | Method and apparatus for designing the layout of a subcircuit in an integrated circuit |
JPH03165061A (en) | 1989-11-22 | 1991-07-17 | Hitachi Ltd | Semiconductor integrated circuit device |
US5298774A (en) | 1990-01-11 | 1994-03-29 | Mitsubishi Denki Kabushiki Kaisha | Gate array system semiconductor integrated circuit device |
US5483104A (en) | 1990-01-12 | 1996-01-09 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
KR100199258B1 (en) | 1990-02-09 | 1999-06-15 | 가나이 쓰도무 | Semiconductor integrated circuit device |
US6100025A (en) | 1990-04-20 | 2000-08-08 | Cold Spring Harbor Laboratory | Cloning by complementation and related processes |
US5977305A (en) | 1990-04-20 | 1999-11-02 | Cold Spring Harbor Laboratories | Cloning by complementation and related processes |
US5047979A (en) | 1990-06-15 | 1991-09-10 | Integrated Device Technology, Inc. | High density SRAM circuit with ratio independent memory cells |
US5208765A (en) | 1990-07-20 | 1993-05-04 | Advanced Micro Devices, Inc. | Computer-based method and system for product development |
US5079614A (en) | 1990-09-26 | 1992-01-07 | S-Mos Systems, Inc. | Gate array architecture with basic cell interleaved gate electrodes |
JP3017789B2 (en) | 1990-10-18 | 2000-03-13 | 三菱電機株式会社 | Layout design method for semiconductor integrated circuit device |
JP2851447B2 (en) | 1991-03-08 | 1999-01-27 | 三菱電機株式会社 | Shape simulation method |
JPH05152937A (en) | 1991-11-26 | 1993-06-18 | Hitachi Ltd | Logic gate circuit |
JP3129336B2 (en) | 1991-12-09 | 2001-01-29 | 沖電気工業株式会社 | Semiconductor storage device |
US7071060B1 (en) | 1996-02-28 | 2006-07-04 | Sandisk Corporation | EEPROM with split gate source side infection with sidewall spacers |
US5242770A (en) | 1992-01-16 | 1993-09-07 | Microunity Systems Engineering, Inc. | Mask for photolithography |
JP2760195B2 (en) | 1992-01-20 | 1998-05-28 | 日本電気株式会社 | Logic circuit |
US5526307A (en) | 1992-01-22 | 1996-06-11 | Macronix International Co., Ltd. | Flash EPROM integrated circuit architecture |
JPH05218362A (en) | 1992-02-04 | 1993-08-27 | Sharp Corp | Basic cells of gate array |
US5367187A (en) | 1992-12-22 | 1994-11-22 | Quality Semiconductor, Inc. | Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions |
IT1257184B (en) | 1992-12-22 | 1996-01-10 | Applied Research Systems | PREPARED FOR ANTI-INFLAMMATORY, ANTI-AGULANT AND ANTI-TUMORAL ACTIVITY |
US5420447A (en) | 1993-01-29 | 1995-05-30 | Sgs-Thomson Microelectronics, Inc. | Double buffer base gate array cell |
US5359226A (en) | 1993-02-02 | 1994-10-25 | Paradigm Technology, Inc. | Static memory with self aligned contacts and split word lines |
US5497334A (en) | 1993-02-19 | 1996-03-05 | International Business Machines Corporation | Application generator for use in verifying a hierarchical circuit design |
US5410107A (en) | 1993-03-01 | 1995-04-25 | The Board Of Trustees Of The University Of Arkansas | Multichip module |
FR2702595B1 (en) | 1993-03-11 | 1996-05-24 | Toshiba Kk | Multilayer wiring structure. |
US5536955A (en) | 1993-03-29 | 1996-07-16 | Toppan Electronics (Usa) Inc. | Electronic devices for use in generating integrated circuit structures and method therefor |
US5338963A (en) | 1993-04-05 | 1994-08-16 | International Business Machines Corporation | Soft error immune CMOS static RAM cell |
US5691218A (en) | 1993-07-01 | 1997-11-25 | Lsi Logic Corporation | Method of fabricating a programmable polysilicon gate array base cell structure |
US5396128A (en) | 1993-09-13 | 1995-03-07 | Motorola, Inc. | Output circuit for interfacing integrated circuits having different power supply potentials |
JP3144967B2 (en) | 1993-11-08 | 2001-03-12 | 株式会社日立製作所 | Semiconductor integrated circuit and method of manufacturing the same |
JP2746087B2 (en) | 1993-12-01 | 1998-04-28 | 日本電気株式会社 | Semiconductor integrated circuit |
US5625568A (en) | 1993-12-22 | 1997-04-29 | Vlsi Technology, Inc. | Method and apparatus for compacting integrated circuits with standard cell architectures |
JP2684980B2 (en) | 1993-12-24 | 1997-12-03 | 日本電気株式会社 | Semiconductor memory device and manufacturing method thereof |
US5378649A (en) | 1994-04-08 | 1995-01-03 | United Microelectronics Corporation | Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas |
US5636002A (en) | 1994-04-29 | 1997-06-03 | Lucent Technologies Inc. | Auxiliary mask features for enhancing the resolution of photolithography |
JP3463180B2 (en) | 1994-05-02 | 2003-11-05 | Necトーキン株式会社 | Method for producing magnetic garnet oxide powder and method for producing magnetic garnet oxide film |
US5591995A (en) | 1994-05-10 | 1997-01-07 | Texas Instruments, Incorporated | Base cell for BiCMOS and CMOS gate arrays |
TW297158B (en) | 1994-05-27 | 1997-02-01 | Hitachi Ltd | |
JP3202490B2 (en) | 1994-07-22 | 2001-08-27 | 株式会社東芝 | Integrated circuit layout method and integrated circuit layout device |
JP3469362B2 (en) | 1994-08-31 | 2003-11-25 | 株式会社東芝 | Semiconductor storage device |
US5528177A (en) | 1994-09-16 | 1996-06-18 | Research Foundation Of State University Of New York | Complementary field-effect transistor logic circuits for wave pipelining |
US5497337A (en) | 1994-10-21 | 1996-03-05 | International Business Machines Corporation | Method for designing high-Q inductors in silicon technology without expensive metalization |
US5852562A (en) | 1994-12-13 | 1998-12-22 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones |
JPH08292938A (en) | 1995-02-24 | 1996-11-05 | Fujitsu Ltd | Method and device for finite element mesh generation and method and device for analysis |
JP2647045B2 (en) | 1995-02-28 | 1997-08-27 | 日本電気株式会社 | Semiconductor memory device and method of manufacturing the same |
US5682323A (en) | 1995-03-06 | 1997-10-28 | Lsi Logic Corporation | System and method for performing optical proximity correction on macrocell libraries |
US5581098A (en) | 1995-05-05 | 1996-12-03 | Circuit Integration Technology, Inc. | Circuit routing structure using fewer variable masks |
JP3708168B2 (en) | 1995-06-13 | 2005-10-19 | 富士通株式会社 | Delay device |
JP3535615B2 (en) | 1995-07-18 | 2004-06-07 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
US5774367A (en) | 1995-07-24 | 1998-06-30 | Motorola, Inc. | Method of selecting device threshold voltages for high speed and low power |
US5764533A (en) | 1995-08-01 | 1998-06-09 | Sun Microsystems, Inc. | Apparatus and methods for generating cell layouts |
US5841663A (en) | 1995-09-14 | 1998-11-24 | Vlsi Technology, Inc. | Apparatus and method for synthesizing integrated circuits using parameterized HDL modules |
US5789776A (en) | 1995-09-22 | 1998-08-04 | Nvx Corporation | Single poly memory cell and array |
JPH0993118A (en) | 1995-09-22 | 1997-04-04 | Kawasaki Steel Corp | Path transistor logic circuit |
JPH0997885A (en) | 1995-09-28 | 1997-04-08 | Denso Corp | Gate array |
US5723883A (en) | 1995-11-14 | 1998-03-03 | In-Chip | Gate array cell architecture and routing scheme |
US5640342A (en) | 1995-11-20 | 1997-06-17 | Micron Technology, Inc. | Structure for cross coupled thin film transistors and static random access memory cell |
JP3400215B2 (en) | 1995-11-21 | 2003-04-28 | 沖電気工業株式会社 | Semiconductor device |
JP3486725B2 (en) | 1995-11-28 | 2004-01-13 | 株式会社ルネサステクノロジ | Variable logic integrated circuit |
JP3934719B2 (en) | 1995-12-22 | 2007-06-20 | 株式会社東芝 | Optical proximity correction method |
US6043562A (en) | 1996-01-26 | 2000-03-28 | Micron Technology, Inc. | Digit line architecture for dynamic memory |
KR100229577B1 (en) | 1996-01-31 | 1999-11-15 | 포만 제프리 엘 | Integrated circuit chip having gate array book personalization using local interconnect |
US5798298A (en) | 1996-02-09 | 1998-08-25 | United Microelectronics Corporation | Method of automatically generating dummy metals for multilevel interconnection |
US5705301A (en) | 1996-02-27 | 1998-01-06 | Lsi Logic Corporation | Performing optical proximity correction with the aid of design rule checkers |
US6269472B1 (en) | 1996-02-27 | 2001-07-31 | Lsi Logic Corporation | Optical proximity correction method and apparatus |
US5698873A (en) | 1996-03-08 | 1997-12-16 | Lsi Logic Corporation | High density gate array base cell architecture |
JP2914292B2 (en) | 1996-04-25 | 1999-06-28 | 日本電気株式会社 | Semiconductor device |
US5740068A (en) | 1996-05-30 | 1998-04-14 | International Business Machines Corporation | Fidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correction |
US5935763A (en) | 1996-06-11 | 1999-08-10 | International Business Machines Corporation | Self-aligned pattern over a reflective layer |
US6026223A (en) | 1996-06-28 | 2000-02-15 | Scepanovic; Ranko | Advanced modular cell placement system with overlap remover with minimal noise |
JP3311244B2 (en) | 1996-07-15 | 2002-08-05 | 株式会社東芝 | Basic cell library and method of forming the same |
US5796128A (en) | 1996-07-25 | 1998-08-18 | Translogic Technology, Inc. | Gate array with fully wired multiplexer circuits |
JP2918101B2 (en) | 1996-07-25 | 1999-07-12 | 日本電気株式会社 | Layout method of semiconductor integrated circuit |
US5920486A (en) | 1996-08-16 | 1999-07-06 | International Business Machines Corporation | Parameterized cells for generating dense layouts of VLSI circuits |
JP3152635B2 (en) | 1996-09-09 | 2001-04-03 | 三洋電機株式会社 | Master slice type basic cell, semiconductor integrated circuit device, flip-flop circuit, exclusive OR circuit, multiplexer and adder |
US5858580A (en) | 1997-09-17 | 1999-01-12 | Numerical Technologies, Inc. | Phase shifting circuit manufacture method and apparatus |
US5790417A (en) | 1996-09-25 | 1998-08-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of automatic dummy layout generation |
US5923060A (en) | 1996-09-27 | 1999-07-13 | In-Chip Systems, Inc. | Reduced area gate array cell design based on shifted placement of alternate rows of cells |
US5684733A (en) | 1996-09-30 | 1997-11-04 | Holtek Microelectronics, Inc. | Fixed resistance high density parallel ROM device |
JP3529563B2 (en) | 1996-10-09 | 2004-05-24 | 株式会社東芝 | Semiconductor integrated circuit re-layout method and medium recording semiconductor integrated circuit re-layout program |
US6209123B1 (en) * | 1996-11-01 | 2001-03-27 | Motorola, Inc. | Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors |
US6099584A (en) | 1996-12-06 | 2000-08-08 | Vsli Technology, Inc. | System to fix post-layout timing and design rules violations |
JP3523762B2 (en) | 1996-12-19 | 2004-04-26 | 株式会社東芝 | Semiconductor storage device |
JP3352895B2 (en) | 1996-12-25 | 2002-12-03 | 株式会社東芝 | Semiconductor integrated circuit, method of designing and manufacturing semiconductor integrated circuit |
JPH10189746A (en) | 1996-12-27 | 1998-07-21 | Oki Electric Ind Co Ltd | Wiring layout method for lsi logic circuit |
JP3420694B2 (en) | 1996-12-27 | 2003-06-30 | 株式会社東芝 | Standard cell integrated circuit |
JP3180700B2 (en) | 1997-02-03 | 2001-06-25 | 日本電気株式会社 | Semiconductor integrated circuit device |
JP3036588B2 (en) | 1997-02-03 | 2000-04-24 | 日本電気株式会社 | Semiconductor storage device |
JP3352349B2 (en) | 1997-02-24 | 2002-12-03 | シャープ株式会社 | Bidirectional thyristor element |
US5900340A (en) | 1997-03-03 | 1999-05-04 | Motorola, Inc. | One dimensional lithographic proximity correction using DRC shape functions |
US5977574A (en) | 1997-03-28 | 1999-11-02 | Lsi Logic Corporation | High density gate array cell architecture with sharing of well taps between cells |
US5880991A (en) | 1997-04-14 | 1999-03-09 | International Business Machines Corporation | Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure |
US6393601B1 (en) | 1997-04-14 | 2002-05-21 | Matsushita Electric Industrial Co., Ltd. | Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method |
JP3178799B2 (en) | 1997-04-18 | 2001-06-25 | シャープ株式会社 | MOS logic circuit and semiconductor device provided with the MOS logic circuit |
KR100227621B1 (en) | 1997-05-22 | 1999-11-01 | 김영환 | Method for manufacturing transistor of semiconductor device |
US6005296A (en) | 1997-05-30 | 1999-12-21 | Stmicroelectronics, Inc. | Layout for SRAM structure |
US6445049B1 (en) | 1997-06-30 | 2002-09-03 | Artisan Components, Inc. | Cell based array comprising logic, transfer and drive cells |
US6282696B1 (en) | 1997-08-15 | 2001-08-28 | Lsi Logic Corporation | Performing optical proximity correction with the aid of design rule checkers |
US6370679B1 (en) | 1997-09-17 | 2002-04-09 | Numerical Technologies, Inc. | Data hierarchy layout correction and verification method and apparatus |
US6470489B1 (en) | 1997-09-17 | 2002-10-22 | Numerical Technologies, Inc. | Design rule checking system and method |
US6009251A (en) | 1997-09-30 | 1999-12-28 | Synopsys, Inc. | Method and system for layout verification of an integrated circuit design with reusable subdesigns |
US6114071A (en) | 1997-11-24 | 2000-09-05 | Asml Masktools Netherlands B.V. | Method of fine feature edge tuning with optically-halftoned mask |
DE69727581D1 (en) | 1997-11-28 | 2004-03-18 | St Microelectronics Srl | RAM memory cell with low power consumption |
JP3701781B2 (en) | 1997-11-28 | 2005-10-05 | 株式会社ルネサステクノロジ | Logic circuit and its creation method |
JP3926011B2 (en) | 1997-12-24 | 2007-06-06 | 株式会社ルネサステクノロジ | Semiconductor device design method |
JP3777768B2 (en) | 1997-12-26 | 2006-05-24 | 株式会社日立製作所 | Semiconductor integrated circuit device, storage medium storing cell library, and method of designing semiconductor integrated circuit |
KR100278273B1 (en) | 1997-12-30 | 2001-02-01 | 김영환 | A method for forming contact holes in semiconductor device |
US6249902B1 (en) | 1998-01-09 | 2001-06-19 | Silicon Perspective Corporation | Design hierarchy-based placement |
US6571140B1 (en) | 1998-01-15 | 2003-05-27 | Eutech Cybernetics Pte Ltd. | Service-oriented community agent |
JPH11214662A (en) | 1998-01-29 | 1999-08-06 | Mitsubishi Electric Corp | Semiconductor device |
US6091845A (en) | 1998-02-24 | 2000-07-18 | Micron Technology, Inc. | Inspection technique of photomask |
US6378110B1 (en) | 1998-03-31 | 2002-04-23 | Synopsys, Inc. | Layer-based rule checking for an integrated circuit layout |
US6230299B1 (en) | 1998-03-31 | 2001-05-08 | Mentor Graphics Corporation | Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design |
JPH11297856A (en) | 1998-04-16 | 1999-10-29 | Mitsubishi Electric Corp | Static semiconductor memory |
US5915199A (en) | 1998-06-04 | 1999-06-22 | Sharp Microelectronics Technology, Inc. | Method for manufacturing a CMOS self-aligned strapped interconnection |
US6262487B1 (en) | 1998-06-23 | 2001-07-17 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method |
US6063132A (en) | 1998-06-26 | 2000-05-16 | International Business Machines Corporation | Method for verifying design rule checking software |
US6480989B2 (en) | 1998-06-29 | 2002-11-12 | Lsi Logic Corporation | Integrated circuit design incorporating a power mesh |
US6714903B1 (en) | 1998-07-10 | 2004-03-30 | Lsi Logic Corporation | Placement and routing of circuits using a combined processing/buffer cell |
US6240542B1 (en) | 1998-07-14 | 2001-05-29 | Lsi Logic Corporation | Poly routing for chip interconnects with minimal impact on chip performance |
US6182272B1 (en) | 1998-07-16 | 2001-01-30 | Lsi Logic Corporation | Metal layer assignment |
JP3562975B2 (en) | 1998-09-29 | 2004-09-08 | 株式会社東芝 | Integrated circuit design method and integrated circuit design device |
US20020008257A1 (en) | 1998-09-30 | 2002-01-24 | John P. Barnak | Mosfet gate electrodes having performance tuned work functions and methods of making same |
JP2000114262A (en) | 1998-10-05 | 2000-04-21 | Toshiba Corp | Semiconductor device and its manufacture |
JP3852729B2 (en) | 1998-10-27 | 2006-12-06 | 富士通株式会社 | Semiconductor memory device |
US6275973B1 (en) | 1998-10-30 | 2001-08-14 | Lsi Logic Corporation | Integrated circuit design with delayed cell selection |
US6174742B1 (en) | 1998-10-30 | 2001-01-16 | Lsi Logic Corporation | Off-grid metal layer utilization |
US6166415A (en) | 1998-11-02 | 2000-12-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with improved noise resistivity |
JP3680594B2 (en) | 1998-11-10 | 2005-08-10 | 株式会社日立製作所 | Semiconductor integrated circuit |
TW476069B (en) * | 1998-11-20 | 2002-02-11 | Via Tech Inc | Placement and routing for array device |
WO2000031871A1 (en) | 1998-11-25 | 2000-06-02 | Nanopower, Inc. | Improved flip-flops and other logic circuits and techniques for improving layouts of integrated circuits |
US6477695B1 (en) | 1998-12-09 | 2002-11-05 | Artisan Components, Inc. | Methods for designing standard cell transistor structures |
WO2000036466A1 (en) | 1998-12-11 | 2000-06-22 | Hitachi, Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
KR100291384B1 (en) | 1998-12-31 | 2001-07-12 | 윤종용 | Layout method of semiconductor device |
US6159839A (en) | 1999-02-11 | 2000-12-12 | Vanguard International Semiconductor Corporation | Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections |
US6974978B1 (en) | 1999-03-04 | 2005-12-13 | Intel Corporation | Gate array architecture |
US6480032B1 (en) | 1999-03-04 | 2002-11-12 | Intel Corporation | Gate array architecture |
US6691297B1 (en) | 1999-03-04 | 2004-02-10 | Matsushita Electric Industrial Co., Ltd. | Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI |
US6331733B1 (en) | 1999-08-10 | 2001-12-18 | Easic Corporation | Semiconductor device |
US6194912B1 (en) | 1999-03-11 | 2001-02-27 | Easic Corporation | Integrated circuit device |
US6044007A (en) | 1999-03-24 | 2000-03-28 | Advanced Micro Devices, Inc. | Modification of mask layout data to improve writeability of OPC |
JP3986036B2 (en) | 1999-04-16 | 2007-10-03 | 株式会社日立製作所 | Semiconductor integrated circuit device |
US6505328B1 (en) | 1999-04-27 | 2003-01-07 | Magma Design Automation, Inc. | Method for storing multiple levels of design data in a common database |
US6507941B1 (en) | 1999-04-28 | 2003-01-14 | Magma Design Automation, Inc. | Subgrid detailed routing |
JP4565700B2 (en) | 1999-05-12 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US6492066B1 (en) | 1999-05-28 | 2002-12-10 | Advanced Micro Devices, Inc. | Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion |
US6425112B1 (en) | 1999-06-17 | 2002-07-23 | International Business Machines Corporation | Auto correction of error checked simulated printed images |
US6381730B1 (en) | 1999-07-09 | 2002-04-30 | Sequence Design, Inc. | Method and system for extraction of parasitic interconnect impedance including inductance |
US6525350B1 (en) | 1999-07-16 | 2003-02-25 | Kawasaki Steel Corporation | Semiconductor integrated circuit basic cell semiconductor integrated circuit using the same |
JP2001056463A (en) | 1999-08-20 | 2001-02-27 | Casio Comput Co Ltd | Liquid crystal display device |
JP2001068558A (en) | 1999-08-30 | 2001-03-16 | Hitachi Ltd | Semiconductor integrated circuit device |
US6436805B1 (en) | 1999-09-01 | 2002-08-20 | Micron Technology, Inc. | Local interconnect structures and methods for making the same |
US6496965B1 (en) | 1999-09-20 | 2002-12-17 | Magma Design Automation, Inc. | Automated design of parallel drive standard cells |
TW423218B (en) | 1999-10-06 | 2001-02-21 | Ind Tech Res Inst | Charge-redistribution low-swing differential logic circuit |
US6194104B1 (en) | 1999-10-12 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Optical proximity correction (OPC) method for improving lithography process window |
US6737347B1 (en) | 1999-10-20 | 2004-05-18 | Texas Instruments Incorporated | Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device |
US6426269B1 (en) | 1999-10-21 | 2002-07-30 | International Business Machines Corporation | Dummy feature reduction using optical proximity effect correction |
US6255845B1 (en) | 1999-11-16 | 2001-07-03 | Advanced Micro Devices, Inc. | Efficient use of spare gates for post-silicon debug and enhancements |
US6570234B1 (en) | 1999-11-17 | 2003-05-27 | Aeroflex Utmc Microelectronic Systems, Inc. | Radiation resistant integrated circuit design |
JP2001144603A (en) | 1999-11-18 | 2001-05-25 | Oki Micro Design Co Ltd | Level shifter circuit and data output circuit including it |
AU1770301A (en) | 1999-11-18 | 2001-05-30 | Pdf Solutions, Inc. | System and method for product yield prediction using device and process neighborhood characterization vehicle |
JP2001168707A (en) | 1999-12-03 | 2001-06-22 | Sony Corp | Logic circuit and full adder using the same |
US6421820B1 (en) | 1999-12-13 | 2002-07-16 | Infineon Technologies Ag | Semiconductor device fabrication using a photomask with assist features |
US6303252B1 (en) | 1999-12-27 | 2001-10-16 | United Microelectronics Corp. | Reticle having assist feature between semi-dense lines |
KR100346832B1 (en) | 2000-01-12 | 2002-08-03 | 삼성전자 주식회사 | Static random access memory device and manufacturing method thereof |
US6737199B1 (en) | 2000-01-31 | 2004-05-18 | Taiwan Semiconductor Manufacturing Company | Using new pattern fracturing rules for optical proximity correction mask-making to improve critical dimension uniformity |
US6408427B1 (en) | 2000-02-22 | 2002-06-18 | The Regents Of The University Of California | Wire width planning and performance optimization for VLSI interconnects |
US6756811B2 (en) | 2000-03-10 | 2004-06-29 | Easic Corporation | Customizable and programmable cell array |
US6331790B1 (en) | 2000-03-10 | 2001-12-18 | Easic Corporation | Customizable and programmable cell array |
US6399972B1 (en) | 2000-03-13 | 2002-06-04 | Oki Electric Industry Co., Ltd. | Cell based integrated circuit and unit cell architecture therefor |
US6536028B1 (en) | 2000-03-14 | 2003-03-18 | Ammocore Technologies, Inc. | Standard block architecture for integrated circuit design |
JP2001272228A (en) | 2000-03-24 | 2001-10-05 | Railway Technical Res Inst | System and method for measuring amount of relative displacement |
US6356112B1 (en) | 2000-03-28 | 2002-03-12 | Translogic Technology, Inc. | Exclusive or/nor circuit |
US6553544B2 (en) | 2000-04-04 | 2003-04-22 | Matsushita Electric Industrial Co., Ltd. | Method for design of partial circuit |
US6416907B1 (en) | 2000-04-27 | 2002-07-09 | Micron Technology, Inc. | Method for designing photolithographic reticle layout, reticle, and photolithographic process |
TW512424B (en) | 2000-05-01 | 2002-12-01 | Asml Masktools Bv | Hybrid phase-shift mask |
US6583041B1 (en) | 2000-05-01 | 2003-06-24 | Advanced Micro Devices, Inc. | Microdevice fabrication method using regular arrays of lines and spaces |
JP4885365B2 (en) | 2000-05-16 | 2012-02-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US6509952B1 (en) | 2000-05-23 | 2003-01-21 | Silicon Valley Group, Inc. | Method and system for selective linewidth optimization during a lithographic process |
US6610607B1 (en) | 2000-05-25 | 2003-08-26 | International Business Machines Corporation | Method to define and tailor process limited lithographic features using a modified hard mask process |
US6445065B1 (en) | 2000-06-06 | 2002-09-03 | In-Chip Systems, Inc. | Routing driven, metal programmable integrated circuit architecture with multiple types of core cells |
US6617621B1 (en) | 2000-06-06 | 2003-09-09 | Virage Logic Corporation | Gate array architecture using elevated metal levels for customization |
US6425113B1 (en) | 2000-06-13 | 2002-07-23 | Leigh C. Anderson | Integrated verification and manufacturability tool |
US6889370B1 (en) | 2000-06-20 | 2005-05-03 | Unisys Corporation | Method and apparatus for selecting and aligning cells using a placement tool |
JP2002026296A (en) | 2000-06-22 | 2002-01-25 | Internatl Business Mach Corp <Ibm> | Semiconductor integrated circuit device |
JP2002009160A (en) | 2000-06-26 | 2002-01-11 | Nec Microsystems Ltd | Automatic layout method of semiconductor integrated circuit, semiconductor integrated circuit manufactured by the method and recording medium recording the method |
US7225423B2 (en) | 2000-06-30 | 2007-05-29 | Zenasis Technologies, Inc. | Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks |
US6787271B2 (en) | 2000-07-05 | 2004-09-07 | Numerical Technologies, Inc. | Design and layout of phase shifting photolithographic masks |
US6978436B2 (en) | 2000-07-05 | 2005-12-20 | Synopsys, Inc. | Design data format and hierarchy management for phase processing |
US6733929B2 (en) | 2000-07-05 | 2004-05-11 | Numerical Technologies, Inc. | Phase shift masking for complex patterns with proximity adjustments |
US7028285B2 (en) | 2000-07-05 | 2006-04-11 | Synopsys, Inc. | Standard cell design incorporating phase information |
JP4794030B2 (en) | 2000-07-10 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US6516459B1 (en) | 2000-07-10 | 2003-02-04 | Mentor Graphics Corporation | Integrated circuit design correction using fragment correspondence |
US6632741B1 (en) | 2000-07-19 | 2003-10-14 | International Business Machines Corporation | Self-trimming method on looped patterns |
US20050136340A1 (en) | 2000-07-21 | 2005-06-23 | Asml Netherlands B.V. | Lithographic apparatus and methods, patterning structure and method for making a patterning structure, device manufacturing method, and device manufactured thereby |
US6574786B1 (en) | 2000-07-21 | 2003-06-03 | Aeroflex UTMC Microelectronics Systems, Inc. | Gate array cell generator using cadence relative object design |
US6523162B1 (en) | 2000-08-02 | 2003-02-18 | Numerical Technologies, Inc. | General purpose shape-based layout processing scheme for IC layout modifications |
JP4764987B2 (en) | 2000-09-05 | 2011-09-07 | 富士電機株式会社 | Super junction semiconductor device |
WO2002025373A2 (en) | 2000-09-13 | 2002-03-28 | Massachusetts Institute Of Technology | Method of design and fabrication of integrated circuits using regular arrays and gratings |
US6800883B2 (en) | 2000-09-21 | 2004-10-05 | Matsushita Electric Industrial Co., Ltd. | CMOS basic cell and method for fabricating semiconductor integrated circuit using the same |
US6625801B1 (en) | 2000-09-29 | 2003-09-23 | Numerical Technologies, Inc. | Dissection of printed edges from a fabrication layout for correcting proximity effects |
US6557162B1 (en) | 2000-09-29 | 2003-04-29 | Numerical Technologies, Inc. | Method for high yield reticle formation |
US6453457B1 (en) | 2000-09-29 | 2002-09-17 | Numerical Technologies, Inc. | Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout |
US6794677B2 (en) | 2000-10-02 | 2004-09-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for fabricating the same |
US6555450B2 (en) | 2000-10-04 | 2003-04-29 | Samsung Electronics Co., Ltd. | Contact forming method for semiconductor device |
US6566720B2 (en) | 2000-10-05 | 2003-05-20 | United Memories, Inc. | Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits |
US6978437B1 (en) | 2000-10-10 | 2005-12-20 | Toppan Photomasks, Inc. | Photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufacture with same |
KR20020034313A (en) | 2000-10-31 | 2002-05-09 | 박종섭 | Method of manufacturing sram cell |
US6703170B1 (en) | 2000-12-13 | 2004-03-09 | Dupont Photomasks, Inc. | Method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process |
JP2002184870A (en) | 2000-12-18 | 2002-06-28 | Mitsubishi Electric Corp | Static semiconductor storage device |
US6992394B2 (en) | 2000-12-28 | 2006-01-31 | Infineon Technologies Ag | Multi-level conductive lines with reduced pitch |
US6553559B2 (en) | 2001-01-05 | 2003-04-22 | International Business Machines Corporation | Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensions |
US6578190B2 (en) | 2001-01-11 | 2003-06-10 | International Business Machines Corporation | Process window based optical proximity correction of lithographic images |
JP2002289703A (en) | 2001-01-22 | 2002-10-04 | Nec Corp | Semiconductor memory and its manufacturing method |
JP2002252161A (en) | 2001-02-23 | 2002-09-06 | Hitachi Ltd | Semiconductor manufacturing system |
US6792591B2 (en) | 2001-02-28 | 2004-09-14 | Asml Masktools B.V. | Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs |
JP4928675B2 (en) | 2001-03-01 | 2012-05-09 | エルピーダメモリ株式会社 | Semiconductor device |
JP4736206B2 (en) | 2001-03-05 | 2011-07-27 | 大日本印刷株式会社 | Photomask pattern defect inspection method and fine figure pattern detection method |
DE60202230T2 (en) | 2001-03-14 | 2005-12-15 | Asml Masktools B.V. | Close-effect correction by means of unresolved auxiliary structures in the form of conductor bars |
US6732334B2 (en) * | 2001-04-02 | 2004-05-04 | Matsushita Electric Industrial Co., Ltd. | Analog MOS semiconductor device, manufacturing method therefor, manufacturing program therefor, and program device therefor |
US6514849B1 (en) | 2001-04-02 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of forming smaller contact size using a spacer hard mask |
US6574779B2 (en) * | 2001-04-12 | 2003-06-03 | International Business Machines Corporation | Hierarchical layout method for integrated circuits |
US6505327B2 (en) | 2001-04-13 | 2003-01-07 | Numerical Technologies, Inc. | Generating an instance-based representation of a design hierarchy |
US6524870B2 (en) | 2001-04-24 | 2003-02-25 | Pell, Iii Edwin A. | Method and apparatus for improving resolution of objects in a semiconductor wafer |
JP4187947B2 (en) | 2001-04-26 | 2008-11-26 | 株式会社東芝 | PATTERN CORRECTION METHOD, PATTERN CORRECTION DEVICE, AND RECORDING MEDIUM CONTAINING PATTERN CORRECTION PROGRAM |
US6936908B2 (en) | 2001-05-03 | 2005-08-30 | Ixys Corporation | Forward and reverse blocking devices |
US6553562B2 (en) | 2001-05-04 | 2003-04-22 | Asml Masktools B.V. | Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques |
US6590289B2 (en) | 2001-05-17 | 2003-07-08 | Lsi Logic Corporation | Hexadecagonal routing |
US6523156B2 (en) | 2001-06-08 | 2003-02-18 | Library Technologies, Inc. | Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries |
JP2002368135A (en) | 2001-06-12 | 2002-12-20 | Hitachi Ltd | Semiconductor memory device |
US6759282B2 (en) | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
JP4746770B2 (en) | 2001-06-19 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US6609235B2 (en) | 2001-06-22 | 2003-08-19 | Bae Systems Information And Electronic Systems Integration, Inc. | Method for providing a fill pattern for an integrated circuit design |
US7079989B2 (en) | 2001-06-29 | 2006-07-18 | Shmuel Wimer | Arrangements for automatic re-legging of transistors |
US6835591B2 (en) | 2001-07-25 | 2004-12-28 | Nantero, Inc. | Methods of nanotube films and articles |
DE10137830A1 (en) | 2001-08-02 | 2003-02-27 | Infineon Technologies Ag | Method for producing a self-aligned structure on a semiconductor wafer |
DE10143723B4 (en) | 2001-08-31 | 2006-09-28 | Infineon Technologies Ag | A method for optimizing a layout for a mask for use in semiconductor fabrication |
US6684382B2 (en) | 2001-08-31 | 2004-01-27 | Numerical Technologies, Inc. | Microloading effect correction |
US6633182B2 (en) | 2001-09-05 | 2003-10-14 | Carnegie Mellon University | Programmable gate array based on configurable metal interconnect vias |
JP4786836B2 (en) | 2001-09-07 | 2011-10-05 | 富士通セミコンダクター株式会社 | Wiring connection design method and semiconductor device |
JP2003092250A (en) | 2001-09-18 | 2003-03-28 | Hitachi Ltd | Semiconductor device and manufacturing method therefor |
JP3989213B2 (en) | 2001-09-25 | 2007-10-10 | シャープ株式会社 | Pass transistor logic circuit |
JP3637299B2 (en) | 2001-10-05 | 2005-04-13 | 松下電器産業株式会社 | Semiconductor memory device |
US7175940B2 (en) | 2001-10-09 | 2007-02-13 | Asml Masktools B.V. | Method of two dimensional feature model calibration and optimization |
JP2003124339A (en) | 2001-10-11 | 2003-04-25 | Toshiba Corp | Semiconductor device and its manufacturing method |
JP3526450B2 (en) | 2001-10-29 | 2004-05-17 | 株式会社東芝 | Semiconductor integrated circuit and standard cell layout design method |
JP2003142584A (en) | 2001-11-05 | 2003-05-16 | Matsushita Electric Ind Co Ltd | Method for designing semiconductor integrated circuit |
US6673638B1 (en) | 2001-11-14 | 2004-01-06 | Kla-Tencor Corporation | Method and apparatus for the production of process sensitive lithographic features |
JP3789351B2 (en) | 2001-11-30 | 2006-06-21 | 株式会社日立製作所 | Reflective liquid crystal display device and manufacturing method thereof |
JP2003168640A (en) | 2001-12-03 | 2003-06-13 | Hitachi Ltd | Method of manufacturing semiconductor device |
JP2003188361A (en) | 2001-12-20 | 2003-07-04 | Mitsubishi Electric Corp | Semiconductor integrated circuit with gate array structure |
JP3828419B2 (en) | 2001-12-25 | 2006-10-04 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US6787469B2 (en) | 2001-12-28 | 2004-09-07 | Texas Instruments Incorporated | Double pattern and etch of poly with hard mask |
US7159197B2 (en) | 2001-12-31 | 2007-01-02 | Synopsys, Inc. | Shape-based geometry engine to perform smoothing and other layout beautification operations |
US6817000B2 (en) * | 2002-01-02 | 2004-11-09 | International Business Machines Corporation | Delay correlation analysis and representation for vital complaint VHDL models |
US7085701B2 (en) * | 2002-01-02 | 2006-08-01 | International Business Machines Corporation | Size reduction techniques for vital compliant VHDL simulation models |
JP2003203993A (en) | 2002-01-10 | 2003-07-18 | Mitsubishi Electric Corp | Semiconductor storage device and its manufacturing method |
US6749972B2 (en) | 2002-01-15 | 2004-06-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Optical proximity correction common process window maximization over varying feature pitch |
US6721926B2 (en) * | 2002-01-25 | 2004-04-13 | Intel Corporation | Method and apparatus for improving digital circuit design |
US6662350B2 (en) | 2002-01-28 | 2003-12-09 | International Business Machines Corporation | FinFET layout generation |
US6820248B1 (en) | 2002-02-14 | 2004-11-16 | Xilinx, Inc. | Method and apparatus for routing interconnects to devices with dissimilar pitches |
US6877144B1 (en) | 2002-02-28 | 2005-04-05 | Dupont Photomasks, Inc. | System and method for generating a mask layout file to reduce power supply voltage fluctuations in an integrated circuit |
JP2003264231A (en) | 2002-03-11 | 2003-09-19 | Mitsubishi Electric Corp | Method for designing layout and semiconductor device |
TWI252516B (en) | 2002-03-12 | 2006-04-01 | Toshiba Corp | Determination method of process parameter and method for determining at least one of process parameter and design rule |
US7386433B2 (en) | 2002-03-15 | 2008-06-10 | Synopsys, Inc. | Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout |
US6732338B2 (en) | 2002-03-20 | 2004-05-04 | International Business Machines Corporation | Method for comprehensively verifying design rule checking runsets |
US6765245B2 (en) | 2002-03-25 | 2004-07-20 | Bae Systems Information And Electronic Systems Integration Inc. | Gate array core cell for VLSI ASIC devices |
US6754121B2 (en) | 2002-03-29 | 2004-06-22 | Stmicroelectronics, Inc. | Sense amplifying circuit and method |
US6745372B2 (en) | 2002-04-05 | 2004-06-01 | Numerical Technologies, Inc. | Method and apparatus for facilitating process-compliant layout optimization |
US6789246B1 (en) | 2002-04-07 | 2004-09-07 | Barcelona Design, Inc. | Method and apparatus for automatic layout of circuit structures |
US7252909B2 (en) | 2002-04-18 | 2007-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to reduce CD non-uniformity in IC manufacturing |
JP4190796B2 (en) * | 2002-04-24 | 2008-12-03 | Necエレクトロニクス株式会社 | How to make exposure master |
US6992925B2 (en) | 2002-04-26 | 2006-01-31 | Kilopass Technologies, Inc. | High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline |
US6826738B2 (en) | 2002-05-10 | 2004-11-30 | Pdf Solutions, Inc. | Optimization of die placement on wafers |
US6794914B2 (en) | 2002-05-24 | 2004-09-21 | Qualcomm Incorporated | Non-volatile multi-threshold CMOS latch with leakage control |
JP2004013920A (en) | 2002-06-03 | 2004-01-15 | Mitsubishi Electric Corp | Semiconductor storage device |
US6980211B2 (en) * | 2002-06-04 | 2005-12-27 | Springsoft, Inc. | Automatic schematic diagram generation using topology information |
US20030229875A1 (en) | 2002-06-07 | 2003-12-11 | Smith Taber H. | Use of models in integrated circuit fabrication |
EP1532670A4 (en) | 2002-06-07 | 2007-09-12 | Praesagus Inc | Characterization adn reduction of variation for integrated circuits |
US7774726B2 (en) | 2002-06-07 | 2010-08-10 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US7363099B2 (en) | 2002-06-07 | 2008-04-22 | Cadence Design Systems, Inc. | Integrated circuit metrology |
US7712056B2 (en) | 2002-06-07 | 2010-05-04 | Cadence Design Systems, Inc. | Characterization and verification for integrated circuit designs |
US7152215B2 (en) | 2002-06-07 | 2006-12-19 | Praesagus, Inc. | Dummy fill for integrated circuits |
US7124386B2 (en) | 2002-06-07 | 2006-10-17 | Praesagus, Inc. | Dummy fill for integrated circuits |
US6795953B2 (en) | 2002-06-11 | 2004-09-21 | Hpl Technologies, Inc. | Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design |
JP3879063B2 (en) | 2002-06-11 | 2007-02-07 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
US7039882B2 (en) | 2002-06-17 | 2006-05-02 | Amar Pal Singh Rana | Technology dependent transformations for Silicon-On-Insulator in digital design synthesis |
JP2004022070A (en) | 2002-06-17 | 2004-01-22 | Renesas Technology Corp | Semiconductor storage device |
JP4036688B2 (en) | 2002-06-18 | 2008-01-23 | 松下電器産業株式会社 | Standard cell library for automatic placement and routing and semiconductor integrated device |
JP4462528B2 (en) | 2002-06-24 | 2010-05-12 | 株式会社日立製作所 | Semiconductor integrated circuit device |
EP1376676A3 (en) | 2002-06-24 | 2008-08-20 | Interuniversitair Microelektronica Centrum Vzw | Multibit non-volatile memory device and method |
US6687895B2 (en) | 2002-07-03 | 2004-02-03 | Numerical Technologies Inc. | Method and apparatus for reducing optical proximity correction output file size |
US6998722B2 (en) | 2002-07-08 | 2006-02-14 | Viciciv Technology | Semiconductor latches and SRAM devices |
JP2004040042A (en) | 2002-07-08 | 2004-02-05 | Fujitsu Ltd | Semiconductor memory device |
US20040009409A1 (en) | 2002-07-11 | 2004-01-15 | Jiunn-Ren Hwang | Optical proximity correction method |
US7063923B2 (en) | 2002-07-11 | 2006-06-20 | United Electronics Corp. | Optical proximity correction method |
US7231628B2 (en) | 2002-07-12 | 2007-06-12 | Cadence Design Systems, Inc. | Method and system for context-specific mask inspection |
JP4416384B2 (en) | 2002-07-19 | 2010-02-17 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
KR100445638B1 (en) | 2002-07-26 | 2004-08-25 | 삼성전자주식회사 | Interconnection structure connecting electrically isolated regions and method of fabricatinging the same |
US7739624B2 (en) | 2002-07-29 | 2010-06-15 | Synopsys, Inc. | Methods and apparatuses to generate a shielding mesh for integrated circuit devices |
US7171645B2 (en) | 2002-08-06 | 2007-01-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device |
KR100493025B1 (en) | 2002-08-07 | 2005-06-07 | 삼성전자주식회사 | Method for manufacturing semiconductor memory device |
US6789244B1 (en) | 2002-08-08 | 2004-09-07 | Xilinx, Inc. | Placement of clock objects under constraints |
US7143380B1 (en) | 2002-08-08 | 2006-11-28 | Xilinx, Inc. | Method for application of network flow techniques under constraints |
US6785875B2 (en) | 2002-08-15 | 2004-08-31 | Fulcrum Microsystems, Inc. | Methods and apparatus for facilitating physical synthesis of an integrated circuit design |
US6854100B1 (en) | 2002-08-27 | 2005-02-08 | Taiwan Semiconductor Manufacturing Company | Methodology to characterize metal sheet resistance of copper damascene process |
JP3795846B2 (en) | 2002-08-29 | 2006-07-12 | 富士通株式会社 | Semiconductor device |
US7345511B2 (en) | 2002-08-29 | 2008-03-18 | Technion Research & Development Foundation Ltd. | Logic circuit and method of logic circuit design |
US6734521B2 (en) | 2002-08-30 | 2004-05-11 | Texas Instruments Incorporated | Integrated circuit cells |
DE10241170A1 (en) | 2002-09-05 | 2004-03-18 | Infineon Technologies Ag | High density NROM FINFET |
US20040049754A1 (en) | 2002-09-06 | 2004-03-11 | Sun Microsystems, Inc. | Method and apparatus for filling and connecting filler material in a layout |
TWI274969B (en) | 2002-09-11 | 2007-03-01 | Asml Masktools Bv | Method and computer program product of generating masks and mask generated thereby, device manufacturing method and device manufactured thereby, and method of printing pattern |
US6807663B2 (en) | 2002-09-23 | 2004-10-19 | Numerical Technologies, Inc. | Accelerated layout processing using OPC pre-processing |
US6928635B2 (en) | 2002-09-25 | 2005-08-09 | Numerical Technologies, Inc. | Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits |
US7327597B1 (en) | 2002-10-02 | 2008-02-05 | Cisco Technology, Inc. | Static random access memory architecture |
WO2004034463A1 (en) | 2002-10-10 | 2004-04-22 | Fujitsu Limited | Layout method, layout apparatus, layout program, and recording medium |
US7214579B2 (en) | 2002-10-24 | 2007-05-08 | Nxp Bv. | Self-aligned 2-bit “double poly CMP” flash memory cell |
US6994939B1 (en) | 2002-10-29 | 2006-02-07 | Advanced Micro Devices, Inc. | Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types |
US7053424B2 (en) | 2002-10-31 | 2006-05-30 | Yamaha Corporation | Semiconductor integrated circuit device and its manufacture using automatic layout |
US7219326B2 (en) | 2002-12-16 | 2007-05-15 | Intrinsity, Inc. | Physical realization of dynamic logic using parameterized tile partitioning |
JP3848248B2 (en) | 2002-12-17 | 2006-11-22 | 株式会社東芝 | SRAM cell and memory integrated circuit using the same |
US6953956B2 (en) | 2002-12-18 | 2005-10-11 | Easic Corporation | Semiconductor device having borderless logic array and flexible I/O |
US7093228B2 (en) | 2002-12-20 | 2006-08-15 | Lsi Logic Corporation | Method and system for classifying an integrated circuit for optical proximity correction |
EP1434264A3 (en) | 2002-12-27 | 2017-01-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method using the transfer technique |
JP4202120B2 (en) | 2002-12-27 | 2008-12-24 | セイコーインスツル株式会社 | Integrated circuit optimization design equipment |
US6898770B2 (en) | 2003-01-09 | 2005-05-24 | Lsi Logic Corporation | Split and merge design flow concept for fast turnaround time of circuit layout design |
JP4136684B2 (en) | 2003-01-29 | 2008-08-20 | Necエレクトロニクス株式会社 | Semiconductor device and dummy pattern arrangement method thereof |
US6996790B2 (en) | 2003-01-30 | 2006-02-07 | Synopsys, Inc. | System and method for generating a two-dimensional yield map for a full layout |
JP2004241529A (en) | 2003-02-05 | 2004-08-26 | Matsushita Electric Ind Co Ltd | Semiconductor circuit device and method of simulating circuit thereof |
US6884712B2 (en) | 2003-02-07 | 2005-04-26 | Chartered Semiconductor Manufacturing, Ltd. | Method of manufacturing semiconductor local interconnect and contact |
US6777146B1 (en) | 2003-02-21 | 2004-08-17 | International Business Machines Corporation | Method of optical proximity correction with sub-resolution assists |
JP2004253730A (en) | 2003-02-21 | 2004-09-09 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
US7149999B2 (en) | 2003-02-25 | 2006-12-12 | The Regents Of The University Of California | Method for correcting a mask design layout |
JP4531340B2 (en) | 2003-02-27 | 2010-08-25 | ルネサスエレクトロニクス株式会社 | Multiplexer cell layout structure |
EP1597631B1 (en) | 2003-02-27 | 2009-07-22 | The University of Hong Kong | Multiple exposure method for circuit performance improvement and maskset |
JP4290457B2 (en) | 2003-03-31 | 2009-07-08 | 株式会社ルネサステクノロジ | Semiconductor memory device |
JP3920804B2 (en) | 2003-04-04 | 2007-05-30 | 松下電器産業株式会社 | Semiconductor memory device |
US6931617B2 (en) | 2003-04-21 | 2005-08-16 | Synopsys, Inc. | Mask cost driven logic optimization and synthesis |
US7065731B2 (en) | 2003-05-07 | 2006-06-20 | Cadence Design Systems, Inc. | Removal of acute angles in a design layout |
KR100915258B1 (en) | 2003-05-07 | 2009-09-03 | 모사이드 테크놀로지스 코포레이션 | Managing power on integrated circuits using power islands |
US7093208B2 (en) | 2003-05-12 | 2006-08-15 | International Business Machines Corporation | Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices |
JP2004342757A (en) | 2003-05-14 | 2004-12-02 | Toshiba Corp | Semiconductor integrated circuit and method of designing the same |
US7063920B2 (en) | 2003-05-16 | 2006-06-20 | Asml Holding, N.V. | Method for the generation of variable pitch nested lines and/or contact holes using fixed size pixels for direct-write lithographic systems |
JP4233381B2 (en) | 2003-05-21 | 2009-03-04 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US7770144B2 (en) | 2003-05-28 | 2010-08-03 | Eric Dellinger | Modular array defined by standard cell logic |
US7107551B1 (en) | 2003-05-30 | 2006-09-12 | Prolific, Inc. | Optimization of circuit designs using a continuous spectrum of library cells |
US7183611B2 (en) | 2003-06-03 | 2007-02-27 | Micron Technology, Inc. | SRAM constructions, and electronic systems comprising SRAM constructions |
US7400627B2 (en) | 2003-06-05 | 2008-07-15 | Brooktree Broadband Holding, Inc. | ATM header compression using hash tables |
US6992916B2 (en) | 2003-06-13 | 2006-01-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement |
JP4245418B2 (en) | 2003-06-25 | 2009-03-25 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor integrated circuit device having diagonal wiring and layout method thereof |
US20050009312A1 (en) | 2003-06-26 | 2005-01-13 | International Business Machines Corporation | Gate length proximity corrected device |
US6900999B1 (en) | 2003-06-30 | 2005-05-31 | Integrated Device Technology, Inc. | Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratio |
KR100577610B1 (en) | 2003-07-15 | 2006-05-10 | 삼성전자주식회사 | semiconductor device, method for manufacturing semiconductor decice, SRAM device and method for manufacturing SRAM |
US6993741B2 (en) | 2003-07-15 | 2006-01-31 | International Business Machines Corporation | Generating mask patterns for alternating phase-shift mask lithography |
EP1519421A1 (en) | 2003-09-25 | 2005-03-30 | Interuniversitair Microelektronica Centrum Vzw | Multiple gate semiconductor device and method for forming same |
US6921982B2 (en) | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
EP1569273A3 (en) | 2003-07-30 | 2005-09-14 | St Microelectronics S.A. | Conductive lines embedded in isolation regions |
US6924560B2 (en) | 2003-08-08 | 2005-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Compact SRAM cell with FinFET |
JP4398195B2 (en) | 2003-08-08 | 2010-01-13 | パナソニック株式会社 | Semiconductor memory device |
JP4620942B2 (en) | 2003-08-21 | 2011-01-26 | 川崎マイクロエレクトロニクス株式会社 | Semiconductor integrated circuit layout method, layout structure thereof, and photomask |
TWI220268B (en) | 2003-09-17 | 2004-08-11 | Faraday Tech Corp | Method for programming a routing layout design through one via layer |
US7345909B2 (en) | 2003-09-24 | 2008-03-18 | Yen-Jen Chang | Low-power SRAM memory cell |
US6957402B2 (en) | 2003-09-24 | 2005-10-18 | Artisan Components, Inc. | Yield maximization in the manufacture of integrated circuits |
KR100516226B1 (en) | 2003-09-25 | 2005-09-23 | 동부아남반도체 주식회사 | Cell for test of SRAM cell and method for test SRAM cell |
JP2005114752A (en) | 2003-10-02 | 2005-04-28 | Yamaha Corp | Music player |
JP4599048B2 (en) | 2003-10-02 | 2010-12-15 | 川崎マイクロエレクトロニクス株式会社 | Semiconductor integrated circuit layout structure, semiconductor integrated circuit layout method, and photomask |
JP4632287B2 (en) | 2003-10-06 | 2011-02-16 | 株式会社日立製作所 | Semiconductor integrated circuit device |
US7155689B2 (en) | 2003-10-07 | 2006-12-26 | Magma Design Automation, Inc. | Design-manufacturing interface via a unified model |
FR2860920A1 (en) | 2003-10-14 | 2005-04-15 | St Microelectronics Sa | Multiple short local electrical connections for selective linkage of integrated circuit elements comprise masked selective humid attack of deposited metal |
JP2005123524A (en) | 2003-10-20 | 2005-05-12 | Toshiba Corp | Semiconductor device and its manufacturing method |
US6867073B1 (en) | 2003-10-21 | 2005-03-15 | Ziptronix, Inc. | Single mask via method and device |
JP4346410B2 (en) | 2003-10-28 | 2009-10-21 | 東芝メモリシステムズ株式会社 | Wiring design method for semiconductor integrated circuit and semiconductor integrated circuit |
US7329953B2 (en) | 2003-10-29 | 2008-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same |
JP2005149265A (en) | 2003-11-18 | 2005-06-09 | Olympus Corp | Arithmetic processing system and arithmetic processor |
US7269803B2 (en) | 2003-12-18 | 2007-09-11 | Lsi Corporation | System and method for mapping logical components to physical locations in an integrated circuit design environment |
US7052972B2 (en) | 2003-12-19 | 2006-05-30 | Micron Technology, Inc. | Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus |
JP4585197B2 (en) | 2003-12-22 | 2010-11-24 | ルネサスエレクトロニクス株式会社 | Layout design method and photomask |
KR100702552B1 (en) | 2003-12-22 | 2007-04-04 | 인터내셔널 비지네스 머신즈 코포레이션 | METHOD AND DEVICE FOR AUTOMATED LAYER GENERATION FOR DOUBLE-GATE FinFET DESIGNS |
JP2005197345A (en) | 2004-01-05 | 2005-07-21 | Hitachi Ltd | Semiconductor device |
JP2005203447A (en) | 2004-01-13 | 2005-07-28 | Toshiba Corp | Semiconductor integrated circuit, designing system thereof, and designing method thereof |
US7064068B2 (en) | 2004-01-23 | 2006-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to improve planarity of electroplated copper |
KR100564612B1 (en) | 2004-02-19 | 2006-03-28 | 삼성전자주식회사 | Hard Disc Drive |
US7523429B2 (en) | 2004-02-20 | 2009-04-21 | Takumi Technology Corporation | System for designing integrated circuits with enhanced manufacturability |
US7569308B2 (en) | 2004-02-24 | 2009-08-04 | The University Of Hong Kong | Rectangular contact lithography for circuit performance improvement and manufacture cost reduction |
US7084476B2 (en) | 2004-02-26 | 2006-08-01 | International Business Machines Corp. | Integrated circuit logic with self compensating block delays |
JP2005243928A (en) | 2004-02-26 | 2005-09-08 | Fujitsu Ltd | Semiconductor device with paired transistor isolated by trench isolation |
US7353492B2 (en) | 2004-02-26 | 2008-04-01 | International Business Machines Corporation | Method of IC fabrication, IC mask fabrication and program product therefor |
US7335966B2 (en) | 2004-02-26 | 2008-02-26 | Triad Semiconductor, Inc. | Configurable integrated circuit capacitor array using via mask layers |
US7115343B2 (en) | 2004-03-10 | 2006-10-03 | International Business Machines Corporation | Pliant SRAF for improved performance and manufacturability |
US7423298B2 (en) | 2004-03-17 | 2008-09-09 | Sharp Kabushiki Kaisha | Bidirectional photothyristor chip, optical lighting coupler, and solid state relay |
JP2005268610A (en) | 2004-03-19 | 2005-09-29 | Matsushita Electric Ind Co Ltd | Design method of standard cell, and semiconductor integrated circuit |
DE102004014472B4 (en) | 2004-03-24 | 2012-05-03 | Infineon Technologies Ag | Application specific semiconductor integrated circuit |
US7126837B1 (en) | 2004-03-26 | 2006-10-24 | Netlogic Microsystems, Inc. | Interlocking memory/logic cell layout and method of manufacture |
EP1730777B1 (en) | 2004-04-01 | 2007-09-19 | Soisic | Improved layout of a sram memory cell |
EP1738412A1 (en) | 2004-04-02 | 2007-01-03 | Triad Semiconductor, Inc. | Via configurable architecture for customization of analog circuitry in a semiconductor device |
JP2007536564A (en) | 2004-04-02 | 2007-12-13 | クリア・シェイプ・テクノロジーズ・インコーポレーテッド | Modeling the super-resolution process in integrated circuit manufacturing. |
US7404173B2 (en) | 2004-04-07 | 2008-07-22 | Aprio Technologies, Inc. | Intermediate layout for resolution enhancement in semiconductor fabrication |
US20050229130A1 (en) | 2004-04-07 | 2005-10-13 | Aprio Technologies, Inc. | Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements |
US7115920B2 (en) | 2004-04-12 | 2006-10-03 | International Business Machines Corporation | FinFET transistor and circuit |
JP2007534258A (en) | 2004-04-20 | 2007-11-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | High speed differential receiver with rail-to-rail common mode operation with low skew symmetrical differential output signal |
JP2007536581A (en) | 2004-05-07 | 2007-12-13 | メンター・グラフィクス・コーポレーション | Integrated circuit layout design method using process variation band |
US7194712B2 (en) | 2004-05-12 | 2007-03-20 | Synopsys, Inc. | Method and apparatus for identifying line-end features for lithography verification |
US7053668B2 (en) | 2004-05-25 | 2006-05-30 | Kabushiki Kaisha Toshiba | SOI sense amplifier with cross-coupled body terminal |
US7426710B2 (en) | 2004-05-27 | 2008-09-16 | Verisilicon Holdings, Co. Ltd. | Standard cell library having cell drive strengths selected according to delay |
US6975133B1 (en) | 2004-05-27 | 2005-12-13 | International Business Machines Corporation | Logic circuits having linear and cellular gate transistors |
US7257017B2 (en) | 2004-05-28 | 2007-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM cell for soft-error rate reduction and cell stability improvement |
KR100591158B1 (en) | 2004-06-01 | 2006-06-19 | 동부일렉트로닉스 주식회사 | Method for manufacturing gate electrode of semiconductor devices |
US20070257277A1 (en) | 2004-06-04 | 2007-11-08 | Nec Corporation | Semiconductor Device and Method for Manufacturing the Same |
JP4834853B2 (en) * | 2004-06-10 | 2011-12-14 | シャープ株式会社 | THIN FILM TRANSISTOR CIRCUIT, THIN FILM TRANSISTOR CIRCUIT DESIGN METHOD, THIN FILM TRANSISTOR CIRCUIT DESIGN PROGRAM, DESIGN PROGRAM RECORDING MEDIUM, AND DISPLAY DEVICE |
JP4248451B2 (en) | 2004-06-11 | 2009-04-02 | パナソニック株式会社 | Semiconductor device and layout design method thereof |
JP4778689B2 (en) | 2004-06-16 | 2011-09-21 | パナソニック株式会社 | Standard cells, standard cell libraries, and semiconductor integrated circuits |
US7327591B2 (en) | 2004-06-17 | 2008-02-05 | Texas Instruments Incorporated | Staggered memory cell array |
US7003068B2 (en) | 2004-06-21 | 2006-02-21 | Kenet, Inc. | Device for subtracting or adding a constant amount of charge in a charge-coupled device at high operating frequencies |
JP4405865B2 (en) | 2004-06-24 | 2010-01-27 | 富士通マイクロエレクトロニクス株式会社 | Multilayer wiring structure manufacturing method and FIB apparatus |
JP4175649B2 (en) | 2004-07-22 | 2008-11-05 | 松下電器産業株式会社 | Semiconductor device |
KR101234746B1 (en) | 2004-07-27 | 2013-02-19 | 이에이직 코포레이션 | Structured integrated circuit device |
US7176508B2 (en) | 2004-07-27 | 2007-02-13 | International Business Machines Corporation | Temperature sensor for high power very large scale integration circuits |
JP2006049780A (en) | 2004-08-09 | 2006-02-16 | Elpida Memory Inc | Semiconductor integrated circuit device |
US7093213B2 (en) | 2004-08-13 | 2006-08-15 | International Business Machines Corporation | Method for designing an integrated circuit defect monitor |
US7365432B2 (en) | 2004-08-23 | 2008-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell structure |
JP2006073696A (en) | 2004-09-01 | 2006-03-16 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit using standard cell and design method thereof |
US7632610B2 (en) | 2004-09-02 | 2009-12-15 | Intel Corporation | Sub-resolution assist features |
US20060063334A1 (en) | 2004-09-17 | 2006-03-23 | International Business Machines Corporation | Fin FET diode structures and methods for building |
US7227183B2 (en) | 2004-09-17 | 2007-06-05 | International Business Machines Corporation | Polysilicon conductor width measurement for 3-dimensional FETs |
US7185294B2 (en) | 2004-09-23 | 2007-02-27 | Verisilicon Holdings, Co Ltd | Standard cell library having globally scalable transistor channel length |
DE102004047263B4 (en) | 2004-09-24 | 2010-04-22 | Qimonda Ag | A method of generating an aberration avoiding mask layout for a mask |
JP2006100718A (en) | 2004-09-30 | 2006-04-13 | Matsushita Electric Ind Co Ltd | Operation analyzing method for semiconductor integrated circuit device, analyzing apparatus used therefor, and optimization designing method using the apparatus |
US7337421B2 (en) | 2004-09-30 | 2008-02-26 | Cadence Design Systems, Inc. | Method and system for managing design corrections for optical and process effects based on feature tolerances |
US7466607B2 (en) | 2004-09-30 | 2008-12-16 | Analog Devices, Inc. | Memory access system and method using de-coupled read and write circuits |
JP2006114668A (en) | 2004-10-14 | 2006-04-27 | Sony Corp | Semiconductor integrated circuit and its manufacturing method |
US7487475B1 (en) | 2004-10-15 | 2009-02-03 | Cadence Design Systems, Inc. | Systems, methods, and apparatus to perform statistical static timing analysis |
JP2006119195A (en) | 2004-10-19 | 2006-05-11 | Nec Electronics Corp | Layout method of wiring |
US7458045B2 (en) | 2004-10-29 | 2008-11-25 | Synopsys, Inc. | Silicon tolerance specification using shapes as design intent markers |
US7302651B2 (en) | 2004-10-29 | 2007-11-27 | International Business Machines Corporation | Technology migration for integrated circuits with radical design restrictions |
WO2006052738A2 (en) | 2004-11-04 | 2006-05-18 | Fabbrix, Inc. | A method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features |
US7350183B2 (en) | 2004-11-05 | 2008-03-25 | International Business Machines Corporation | Method for improving optical proximity correction |
KR100587692B1 (en) | 2004-11-05 | 2006-06-08 | 삼성전자주식회사 | Circuit wiring layout in semiconductor memory device and layout method thereof |
JP2006156778A (en) | 2004-11-30 | 2006-06-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and its layout designing method |
US7424696B2 (en) | 2004-12-03 | 2008-09-09 | Lsi Corporation | Power mesh for multiple frequency operation of semiconductor products |
US7465973B2 (en) | 2004-12-03 | 2008-12-16 | International Business Machines Corporation | Integrated circuit having gates and active regions forming a regular grating |
US7345330B2 (en) | 2004-12-09 | 2008-03-18 | Omnivision Technologies, Inc. | Local interconnect structure and method for a CMOS image sensor |
JP2006165365A (en) | 2004-12-09 | 2006-06-22 | Renesas Technology Corp | Semiconductor device and method of manufacturing same |
US7396732B2 (en) | 2004-12-17 | 2008-07-08 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Formation of deep trench airgaps and related applications |
JP4357409B2 (en) | 2004-12-17 | 2009-11-04 | 株式会社東芝 | Semiconductor integrated circuit device and design method thereof |
FR2879816B1 (en) | 2004-12-20 | 2007-06-08 | Atmel Nantes Sa Sa | ELECTRONIC CIRCUIT COMPRISING AT LEAST ONE FIRST AND A SECOND DIFFERENTIAL PAIRS WHOSE TRANSISTORS SHARE THE SAME HOUSING |
JP2007043049A (en) | 2004-12-20 | 2007-02-15 | Matsushita Electric Ind Co Ltd | Cell, standard cell, placement method using standard cell, standard cell library, and semiconductor integrated circuit |
JP5392985B2 (en) | 2004-12-28 | 2014-01-22 | スパンション エルエルシー | Semiconductor device and operation control method thereof |
US7106620B2 (en) | 2004-12-30 | 2006-09-12 | International Business Machines Corporation | Memory cell having improved read stability |
US7509621B2 (en) | 2005-01-03 | 2009-03-24 | Synopsys, Inc. | Method and apparatus for placing assist features by identifying locations of constructive and destructive interference |
US7366997B1 (en) | 2005-01-11 | 2008-04-29 | Synplicity, Inc. | Methods and apparatuses for thermal analysis based circuit design |
JP2006196627A (en) | 2005-01-12 | 2006-07-27 | Nec Electronics Corp | Semiconductor device and its design program |
DE102005002533B4 (en) | 2005-01-14 | 2007-09-13 | Infineon Technologies Ag | A method of generating an aberration avoiding mask layout for a mask |
JP4455356B2 (en) | 2005-01-28 | 2010-04-21 | Necエレクトロニクス株式会社 | Semiconductor device |
KR20060092408A (en) | 2005-02-17 | 2006-08-23 | 삼성전자주식회사 | Circuits and methods for high performance exclusive or and exclusive nor |
JP4602112B2 (en) | 2005-02-17 | 2010-12-22 | 株式会社東芝 | Manufacturing method of semiconductor integrated circuit and semiconductor integrated circuit |
JP5018475B2 (en) | 2005-02-23 | 2012-09-05 | 富士通セミコンダクター株式会社 | Semiconductor circuit device and method of manufacturing the semiconductor circuit device |
US7721246B2 (en) | 2005-02-24 | 2010-05-18 | Synopsys, Inc. | Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout |
US7266787B2 (en) | 2005-02-24 | 2007-09-04 | Icera, Inc. | Method for optimising transistor performance in integrated circuits |
US7421678B2 (en) | 2005-02-24 | 2008-09-02 | Synopsys, Inc. | Assist feature placement using a process-sensitivity model |
US7287237B2 (en) | 2005-02-24 | 2007-10-23 | Icera Inc. | Aligned logic cell grid and interconnect routing architecture |
US7200835B2 (en) | 2005-02-24 | 2007-04-03 | Texas Instruments Incorporated | Method of locating sub-resolution assist feature(s) |
US7188322B2 (en) | 2005-02-25 | 2007-03-06 | International Business Machines Corporation | Circuit layout methodology using a shape processing application |
TWI281317B (en) | 2005-03-07 | 2007-05-11 | Sunplus Technology Co Ltd | Self DC-bias high frequency logic gate, NAND gate, and NOR gate using the same |
US7992122B1 (en) | 2005-03-25 | 2011-08-02 | Gg Technology, Inc. | Method of placing and routing for power optimization and timing closure |
US7563701B2 (en) | 2005-03-31 | 2009-07-21 | Intel Corporation | Self-aligned contacts for transistors |
US7882456B2 (en) | 2005-04-09 | 2011-02-01 | Cadence Design Systems, Inc. | Optical lithography correction process |
JP4617272B2 (en) | 2005-04-12 | 2011-01-19 | エーエスエムエル マスクツールズ ビー.ブイ. | Method, program product and device manufacturing method for performing double exposure lithography |
JP4634849B2 (en) | 2005-04-12 | 2011-02-16 | 株式会社東芝 | Integrated circuit pattern layout, photomask, semiconductor device manufacturing method, and data creation method |
JP4921723B2 (en) | 2005-04-18 | 2012-04-25 | 株式会社東芝 | Manufacturing method of semiconductor device |
TWI297101B (en) | 2005-04-20 | 2008-05-21 | Nanya Technology Corp | Phase shifting mask for equal line/space dense line patterns |
US7506300B2 (en) | 2005-04-29 | 2009-03-17 | Cadence Design Systems, Inc. | Apparatus and method for breaking up and merging polygons |
US7480891B2 (en) | 2005-04-29 | 2009-01-20 | Cadence Design Systems, Inc. | Method and apparatus of model-based photomask synthesis |
US7441211B1 (en) | 2005-05-06 | 2008-10-21 | Blaze Dfm, Inc. | Gate-length biasing for digital circuit optimization |
US8044437B1 (en) | 2005-05-16 | 2011-10-25 | Lsi Logic Corporation | Integrated circuit cell architecture configurable for memory or logic elements |
JP4936418B2 (en) | 2005-05-17 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | Semiconductor device, manufacturing method thereof, and semiconductor device design program |
US7308669B2 (en) | 2005-05-18 | 2007-12-11 | International Business Machines Corporation | Use of redundant routes to increase the yield and reliability of a VLSI layout |
JP4912016B2 (en) | 2005-05-23 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
CN101180729B (en) * | 2005-05-26 | 2011-11-30 | Nxp股份有限公司 | Electronic device and its manufacture method |
US7411252B2 (en) | 2005-06-21 | 2008-08-12 | International Business Machines Corporation | Substrate backgate for trigate FET |
US7960791B2 (en) | 2005-06-24 | 2011-06-14 | International Business Machines Corporation | Dense pitch bulk FinFET process by selective EPI and etch |
US7492013B2 (en) | 2005-06-27 | 2009-02-17 | International Business Machines Corporation | Systems and arrangements to interconnect components of a semiconductor device |
WO2007002799A1 (en) | 2005-06-29 | 2007-01-04 | Lightspeed Logic, Inc. | Methods and systems for placement |
US8405216B2 (en) | 2005-06-29 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for integrated circuits |
US7236396B2 (en) | 2005-06-30 | 2007-06-26 | Texas Instruments Incorporated | Area efficient implementation of small blocks in an SRAM array |
JP2007012855A (en) | 2005-06-30 | 2007-01-18 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit, design method and design equipment thereof standard cell, and standard cell library |
JP2007013060A (en) | 2005-07-04 | 2007-01-18 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JP2007018588A (en) | 2005-07-06 | 2007-01-25 | Toshiba Corp | Semiconductor storage device and method of driving the semiconductor storage device |
US7235424B2 (en) | 2005-07-14 | 2007-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for enhanced CMP planarization using surrounded dummy design |
DE112005003638B4 (en) | 2005-07-22 | 2018-10-25 | Fujitsu Semiconductor Ltd. | Method for producing photomask structure data and method for producing a semiconductor device |
WO2007014053A2 (en) | 2005-07-22 | 2007-02-01 | Nanopower Technologies, Inc. | High sensitivity rfid tag integrated circuits |
US7404154B1 (en) | 2005-07-25 | 2008-07-22 | Lsi Corporation | Basic cell architecture for structured application-specific integrated circuits |
US7934172B2 (en) | 2005-08-08 | 2011-04-26 | Micronic Laser Systems Ab | SLM lithography: printing to below K1=.30 without previous OPC processing |
US7568174B2 (en) | 2005-08-19 | 2009-07-28 | Cadence Design Systems, Inc. | Method for checking printability of a lithography target |
JP2007093861A (en) | 2005-09-28 | 2007-04-12 | Renesas Technology Corp | Method for designing mask pattern, and method for manufacturing semiconductor device |
US7749662B2 (en) | 2005-10-07 | 2010-07-06 | Globalfoundries Inc. | Process margin using discrete assist features |
US7485934B2 (en) | 2005-10-25 | 2009-02-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated semiconductor structure for SRAM cells |
US7397260B2 (en) | 2005-11-04 | 2008-07-08 | International Business Machines Corporation | Structure and method for monitoring stress-induced degradation of conductive interconnects |
US20070106971A1 (en) | 2005-11-04 | 2007-05-10 | Lizotech, Inc. | Apparatus for a routing system |
US7569309B2 (en) | 2005-11-09 | 2009-08-04 | Texas Instruments Incorporated | Gate critical dimension variation by use of ghost features |
US7527900B2 (en) | 2005-11-10 | 2009-05-05 | United Microelectronics Corp. | Reticle and optical proximity correction method |
US7934184B2 (en) | 2005-11-14 | 2011-04-26 | Takumi Technology Corporation | Integrated circuit design using modified cells |
JP2007141971A (en) | 2005-11-15 | 2007-06-07 | Matsushita Electric Ind Co Ltd | Designing method of semiconductor integrated circuit |
US7543262B2 (en) | 2005-12-06 | 2009-06-02 | Cadence Design Systems, Inc. | Analog layout module generator and method |
US7569310B2 (en) | 2005-12-07 | 2009-08-04 | Intel Corporation | Sub-resolution assist features for photolithography with trim ends |
US7512017B2 (en) | 2005-12-21 | 2009-03-31 | Intel Corporation | Integration of planar and tri-gate devices on the same substrate |
JP4774294B2 (en) | 2005-12-26 | 2011-09-14 | 富士通株式会社 | Integrated circuit layout apparatus, method and program |
EP1804282A1 (en) | 2005-12-29 | 2007-07-04 | Interuniversitair Microelektronica Centrum vzw ( IMEC) | Methods for manufacturing dense integrated circuits |
US7640522B2 (en) | 2006-01-14 | 2009-12-29 | Tela Innovations, Inc. | Method and system for placing layout objects in a standard-cell layout |
US7614030B2 (en) | 2006-01-17 | 2009-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Scattering bar OPC application method for mask ESD prevention |
JP4675249B2 (en) * | 2006-02-07 | 2011-04-20 | パナソニック株式会社 | Position-dependent variation calculation method and circuit analysis method |
US7480880B2 (en) | 2006-02-21 | 2009-01-20 | International Business Machines Corporation | Method, system, and program product for computing a yield gradient from statistical timing |
US7469401B2 (en) | 2006-02-22 | 2008-12-23 | International Business Machines Corporation | Method for using partitioned masks to build a chip |
US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US9009641B2 (en) * | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
US8839175B2 (en) * | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US7956421B2 (en) * | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US8225261B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US7932545B2 (en) | 2006-03-09 | 2011-04-26 | Tela Innovations, Inc. | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US7943967B2 (en) | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
JP2007265179A (en) * | 2006-03-29 | 2007-10-11 | Fujitsu Ltd | Layout verification method, and layout verification unit |
JP4882455B2 (en) | 2006-03-31 | 2012-02-22 | 富士通セミコンダクター株式会社 | Unit cell of semiconductor integrated circuit, wiring method using unit cell, and wiring program |
US7437691B2 (en) | 2006-04-11 | 2008-10-14 | International Business Machines Corporation | VLSI artwork legalization for hierarchical designs with multiple grid constraints |
US7484197B2 (en) | 2006-04-14 | 2009-01-27 | International Business Machines Corporation | Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs |
US7509622B2 (en) | 2006-04-17 | 2009-03-24 | Synopsys, Inc. | Dummy filling technique for improved planarization of chip surface topography |
JP5579959B2 (en) | 2006-04-18 | 2014-08-27 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device |
US7407890B2 (en) | 2006-04-21 | 2008-08-05 | International Business Machines Corporation | Patterning sub-lithographic features with variable widths |
US7355906B2 (en) | 2006-05-24 | 2008-04-08 | International Business Machines Corporation | SRAM cell design to improve stability |
US7941776B2 (en) * | 2006-05-26 | 2011-05-10 | Open-Silicon Inc. | Method of IC design optimization via creation of design-specific cells from post-layout patterns |
WO2007149004A1 (en) * | 2006-06-13 | 2007-12-27 | Freescale Semiconductor, Inc. | Methods and apparatus for simulating distributed effects |
US7317339B1 (en) | 2006-06-16 | 2008-01-08 | Via Technologies, Inc. | N-domino register with accelerated non-discharge path |
US7459792B2 (en) | 2006-06-19 | 2008-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via layout with via groups placed in interlocked arrangement |
US7992117B2 (en) | 2006-06-20 | 2011-08-02 | Adtran, Inc. | System and method for designing a common centroid layout for an integrated circuit |
JP2008004796A (en) * | 2006-06-23 | 2008-01-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and circuit element layout method |
US7763932B2 (en) | 2006-06-29 | 2010-07-27 | International Business Machines Corporation | Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices |
US7444609B2 (en) | 2006-06-29 | 2008-10-28 | International Business Machines Corporation | Method of optimizing customizable filler cells in an integrated circuit physical design process |
US7739627B2 (en) | 2006-07-05 | 2010-06-15 | Chew Marko P | System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells |
JP2008027940A (en) * | 2006-07-18 | 2008-02-07 | Matsushita Electric Ind Co Ltd | Design method for semiconductor integrated circuit and circuit simulation method |
DE102006037162B4 (en) | 2006-08-01 | 2008-08-21 | Qimonda Ag | Method and apparatus and their use for testing the layout of an electronic circuit |
US7966579B2 (en) | 2006-08-04 | 2011-06-21 | Infineon Technologies Ag | Methods of optical proximity correction |
WO2008015111A2 (en) | 2006-08-04 | 2008-02-07 | Sagantec Israel Ltd | Method and system for adapting a circuit layout to a predefined grid |
US7873929B2 (en) | 2006-08-14 | 2011-01-18 | The Regents Of The University Of California | Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction |
US7886262B2 (en) | 2006-08-15 | 2011-02-08 | Chew Marko P | System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization |
TW200811704A (en) | 2006-08-31 | 2008-03-01 | Univ Nat Yunlin Sci & Tech | Full adder of complementary type carry logic voltage compensator |
US7434185B2 (en) | 2006-09-27 | 2008-10-07 | International Business Machines Corporation | Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data |
JP4362785B2 (en) | 2006-09-28 | 2009-11-11 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
US20080082952A1 (en) | 2006-09-29 | 2008-04-03 | Texas Instruments Incorporated | Method of inclusion of sub-resolution assist feature(s) |
JP4814044B2 (en) | 2006-10-05 | 2011-11-09 | ルネサスエレクトロニクス株式会社 | Pattern design method |
JP2008103610A (en) | 2006-10-20 | 2008-05-01 | Matsushita Electric Ind Co Ltd | Wiring structure for semiconductor integrated circuit, its design method, and design device |
US8230379B2 (en) | 2006-10-20 | 2012-07-24 | Kabushiki Kaisha Toshiba | Layout generating method for semiconductor integrated circuits |
US7624369B2 (en) | 2006-10-31 | 2009-11-24 | International Business Machines Corporation | Closed-loop design for manufacturability process |
US7774739B2 (en) | 2006-11-30 | 2010-08-10 | Texas Instruments Incorporated | Methods for adjusting shifter width of an alternating phase shifter having variable width |
US7802219B2 (en) | 2006-11-30 | 2010-09-21 | Cadence Design Systems, Inc. | Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout |
US8378407B2 (en) | 2006-12-07 | 2013-02-19 | Tower Semiconductor, Ltd. | Floating gate inverter type memory cell and array |
US8156450B2 (en) | 2006-12-18 | 2012-04-10 | Cadence Design Systems, Inc. | Method and system for mask optimization |
US7814447B2 (en) | 2006-12-29 | 2010-10-12 | Cadence Design Systems, Inc. | Supplant design rules in electronic designs |
US8178905B2 (en) | 2007-01-12 | 2012-05-15 | Panasonic Corporation | Layout structure of semiconductor device |
JP5217180B2 (en) | 2007-02-20 | 2013-06-19 | 富士通セミコンダクター株式会社 | Method for manufacturing electrostatic discharge protection device |
US8667443B2 (en) * | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US20080216207A1 (en) | 2007-03-09 | 2008-09-11 | Shen-Hai Tsai | Finger pressing massage glove |
KR100911187B1 (en) | 2007-03-13 | 2009-08-06 | 주식회사 하이닉스반도체 | Latch Structure And Bit Line Sense Amp Having The Same |
US7575973B2 (en) | 2007-03-27 | 2009-08-18 | Sandisk 3D Llc | Method of making three dimensional NAND memory |
US7543252B2 (en) | 2007-03-28 | 2009-06-02 | International Business Machines Corporation | Migration of integrated circuit layout for alternating phase shift masks |
US7791109B2 (en) | 2007-03-29 | 2010-09-07 | International Business Machines Corporation | Metal silicide alloy local interconnect |
US7757196B2 (en) * | 2007-04-04 | 2010-07-13 | Cisco Technology, Inc. | Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards |
US7723786B2 (en) | 2007-04-11 | 2010-05-25 | Ronald Kakoschke | Apparatus of memory array using FinFETs |
US7964267B1 (en) | 2007-04-13 | 2011-06-21 | Bae Systems Tensylon H.P.M., Inc. | Ballistic-resistant panel including high modulus ultra high molecular weight polyethylene tape |
US7453125B1 (en) | 2007-04-24 | 2008-11-18 | Infineon Technologies Ag | Double mesh finfet |
JP4461154B2 (en) | 2007-05-15 | 2010-05-12 | 株式会社東芝 | Semiconductor device |
US20080283910A1 (en) | 2007-05-15 | 2008-11-20 | Qimonda Ag | Integrated circuit and method of forming an integrated circuit |
US7911830B2 (en) | 2007-05-17 | 2011-03-22 | Integrated Magnetoelectronics | Scalable nonvolatile memory |
JP4445521B2 (en) | 2007-06-15 | 2010-04-07 | 株式会社東芝 | Semiconductor device |
US7898040B2 (en) | 2007-06-18 | 2011-03-01 | Infineon Technologies Ag | Dual gate FinFET |
US7923337B2 (en) | 2007-06-20 | 2011-04-12 | International Business Machines Corporation | Fin field effect transistor devices with self-aligned source and drain regions |
US7759194B2 (en) | 2008-07-25 | 2010-07-20 | Semiconductor Manufacturing International (Shanghai) Corporation | Electrically programmable device with embedded EEPROM and method for making thereof |
JP2009025914A (en) | 2007-07-17 | 2009-02-05 | Nec Electronics Corp | Method and program for designing semiconductor integrated circuit |
US7700466B2 (en) | 2007-07-26 | 2010-04-20 | International Business Machines Corporation | Tunneling effect transistor with self-aligned gate |
US7625790B2 (en) | 2007-07-26 | 2009-12-01 | International Business Machines Corporation | FinFET with sublithographic fin width |
US20090057780A1 (en) | 2007-08-27 | 2009-03-05 | International Business Machines Corporation | Finfet structure including multiple semiconductor fin channel heights |
US8156451B2 (en) | 2007-09-14 | 2012-04-10 | Renesas Electronics Corporation | Method of manufacturing photomask |
KR100905157B1 (en) | 2007-09-18 | 2009-06-29 | 주식회사 하이닉스반도체 | Method for forming fine pattern of semiconductor device |
JP2009088085A (en) | 2007-09-28 | 2009-04-23 | Tokyo Electron Ltd | Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, control program, and program storage medium |
US20090101940A1 (en) | 2007-10-19 | 2009-04-23 | Barrows Corey K | Dual gate fet structures for flexible gate array design methodologies |
US8042070B2 (en) | 2007-10-23 | 2011-10-18 | International Business Machines Corporation | Methods and system for analysis and management of parametric yield |
JP2009130238A (en) | 2007-11-27 | 2009-06-11 | Fujitsu Microelectronics Ltd | Semiconductor device |
JP5193582B2 (en) | 2007-12-12 | 2013-05-08 | 株式会社東芝 | Manufacturing method of semiconductor device |
JPWO2009078069A1 (en) | 2007-12-14 | 2011-04-28 | 富士通株式会社 | Semiconductor device |
US7825437B2 (en) | 2007-12-28 | 2010-11-02 | Intel Corporation | Unity beta ratio tri-gate transistor static random access memory (SRAM) |
EP2235453B1 (en) | 2007-12-31 | 2016-08-10 | Arçelik Anonim Sirketi | A cooling device |
US7957178B2 (en) | 2008-01-04 | 2011-06-07 | Texas Instruments Incorporated | Storage cell having buffer circuit for driving the bitline |
US7934173B2 (en) | 2008-01-14 | 2011-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reverse dummy insertion algorithm |
US7926001B2 (en) | 2008-01-16 | 2011-04-12 | Cadence Design Systems, Inc. | Uniformity for semiconductor patterning operations |
US7984395B2 (en) | 2008-01-17 | 2011-07-19 | Synopsys, Inc. | Hierarchical compression for metal one logic layer |
US8453094B2 (en) * | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US8866254B2 (en) | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
US8423947B2 (en) | 2008-03-13 | 2013-04-16 | International Business Machines Corporation | Gridded glyph geometric objects (L3GO) design method |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US8173544B2 (en) | 2008-05-02 | 2012-05-08 | Texas Instruments Incorporated | Integrated circuit having interleaved gridded features, mask set and method for printing |
US7958465B2 (en) | 2008-05-08 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy pattern design for reducing device performance drift |
US7917877B2 (en) | 2008-05-09 | 2011-03-29 | Cadence Design Systems, Inc. | System and method for circuit schematic generation |
EP2117045A1 (en) | 2008-05-09 | 2009-11-11 | Imec | Design Methodology for MuGFET ESD Protection Devices |
US7853915B2 (en) * | 2008-06-24 | 2010-12-14 | Synopsys, Inc. | Interconnect-driven physical synthesis using persistent virtual routing |
KR101749351B1 (en) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US8136072B2 (en) | 2008-11-03 | 2012-03-13 | Arm Limited | Standard cell placement |
US8363455B2 (en) | 2008-12-04 | 2013-01-29 | David Rennie | Eight transistor soft error robust storage cell |
US8116121B2 (en) | 2009-03-06 | 2012-02-14 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing methods with using non-planar type of transistors |
EP2248161B1 (en) | 2009-03-06 | 2019-05-01 | Kaixin Inc. | Leadless integrated circuit package having high density contacts |
US8184472B2 (en) | 2009-03-13 | 2012-05-22 | International Business Machines Corporation | Split-gate DRAM with lateral control-gate MuGFET |
US8004042B2 (en) | 2009-03-20 | 2011-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Static random access memory (SRAM) cell and method for forming same |
US8053299B2 (en) | 2009-04-17 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabrication of a FinFET element |
US8076236B2 (en) | 2009-06-01 | 2011-12-13 | Globalfoundries Inc. | SRAM bit cell with self-aligned bidirectional local interconnects |
US8294212B2 (en) | 2009-09-18 | 2012-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed |
US8675397B2 (en) | 2010-06-25 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure for dual-port SRAM |
US8860107B2 (en) | 2010-06-03 | 2014-10-14 | International Business Machines Corporation | FinFET-compatible metal-insulator-metal capacitor |
US8839162B2 (en) * | 2010-07-14 | 2014-09-16 | International Business Machines Corporation | Specifying circuit level connectivity during circuit design synthesis |
US8796759B2 (en) | 2010-07-15 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) device and method of manufacturing same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8418111B2 (en) | 2010-11-24 | 2013-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for achieving multiple patterning technology compliant design layout |
US8402397B2 (en) | 2011-07-26 | 2013-03-19 | Mentor Graphics Corporation | Hotspot detection based on machine learning |
US8689164B2 (en) | 2011-10-18 | 2014-04-01 | National Taiwan University | Method of analytical placement with weighted-average wirelength model |
US9006841B2 (en) | 2011-12-30 | 2015-04-14 | Stmicroelectronics International N.V. | Dual port SRAM having reduced cell size and rectangular shape |
FR2996950B1 (en) | 2012-10-11 | 2016-01-01 | Dolphin Integration Sa | MEMORY NETWORK BASED ON ROCKETS |
-
2011
- 2011-12-06 US US13/312,673 patent/US8839175B2/en not_active Expired - Fee Related
-
2014
- 2014-09-09 US US14/481,845 patent/US9589091B2/en not_active Expired - Fee Related
-
2017
- 2017-03-07 US US15/452,364 patent/US20170177779A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5756385A (en) * | 1994-03-30 | 1998-05-26 | Sandisk Corporation | Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
US20040245547A1 (en) * | 2003-06-03 | 2004-12-09 | Hitachi Global Storage Technologies B.V. | Ultra low-cost solid-state memory |
US20070211521A1 (en) * | 2006-02-28 | 2007-09-13 | Atsushi Kawasumi | Semiconductor memory device |
US20090159950A1 (en) * | 2007-12-20 | 2009-06-25 | Hitachi, Ltd. | Semiconductor Device and manufacturing Method of Semiconductor Device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190096909A1 (en) * | 2017-09-28 | 2019-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Local interconnect structure |
US11018157B2 (en) * | 2017-09-28 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Local interconnect structure |
US11916077B2 (en) | 2017-09-28 | 2024-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for routing local interconnect structure at same level as reference metal line |
Also Published As
Publication number | Publication date |
---|---|
US8839175B2 (en) | 2014-09-16 |
US20140380260A1 (en) | 2014-12-25 |
US20120144360A1 (en) | 2012-06-07 |
US9589091B2 (en) | 2017-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9589091B2 (en) | Scalable meta-data objects | |
US11983479B2 (en) | Integrated circuit, system for and method of forming an integrated circuit | |
US8869089B2 (en) | Semiconductor integrated circuit and method of designing the same | |
US10621300B2 (en) | Computing system for performing colorless routing for quadruple patterning lithography | |
JP2006196627A (en) | Semiconductor device and its design program | |
US11495619B2 (en) | Integrated circuit device with improved layout | |
US11239228B2 (en) | Integrated circuit layout and method of configuring the same | |
US20210183768A1 (en) | Integrated circuits including via array and methods of manufacturing the same | |
US20240037309A1 (en) | Multiplexer | |
CN116547810A (en) | Adaptive row pattern for custom tiled placement structure for hybrid height cell library | |
CN108205602B (en) | Integrated circuit, and computing system and method for designing an integrated circuit | |
US20210272605A1 (en) | Cell structures and power routing for integrated circuits | |
US11392743B2 (en) | Multiplexer | |
US20180166433A1 (en) | Method of providing layout design of sram cell | |
US20020087941A1 (en) | Semiconductor device having embedded array | |
US11935894B2 (en) | Integrated circuit device with improved layout | |
US20230099326A1 (en) | Integrated circuit, method for forming a layout of integrated circuit using standard cells | |
US10515944B2 (en) | Integrated circuit and method of generating integrated circuit layout | |
US20240169137A1 (en) | Integrated circuit including standard cells and method of designing the same | |
JP2010073728A (en) | Method and device for designing semiconductor integrated circuit layout | |
JPH06188312A (en) | Manufacture of semiconductor integrated circuit | |
US20200201954A1 (en) | Method of designing a layout for a semiconductor integrated circuit | |
DE102022132289A1 (en) | METHOD OF IMPLEMENTING AN INTEGRATED CIRCUIT WITH A NARROW WIDTH CELL AND A WIDER WIDTH CELL WITH THE SAME FUNCTIONALITY | |
JP2004172594A (en) | Method of manufacturing semiconductor integrated circuit device, apparatus of manufacturing semiconductor integrated circuit device, program, semiconductor integrated circuit device, and method of instructing automatic placement of semiconductor integrated circuit device | |
JP2004355438A (en) | System and method for generating input file for circuit simulation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: RPX CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TELA INNOVATIONS, INC.;REEL/FRAME:056602/0001 Effective date: 20210604 |
|
AS | Assignment |
Owner name: BARINGS FINANCE LLC, AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:RPX CORPORATION;REEL/FRAME:063424/0569 Effective date: 20210706 |