US20170117886A1 - Clock generation circuit having deskew function and semiconductor integrated circuit device including same - Google Patents

Clock generation circuit having deskew function and semiconductor integrated circuit device including same Download PDF

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Publication number
US20170117886A1
US20170117886A1 US15/290,344 US201615290344A US2017117886A1 US 20170117886 A1 US20170117886 A1 US 20170117886A1 US 201615290344 A US201615290344 A US 201615290344A US 2017117886 A1 US2017117886 A1 US 2017117886A1
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US
United States
Prior art keywords
signal
output
clock
waveform
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/290,344
Other languages
English (en)
Inventor
Jin Ook Song
Bong Il Park
Jae Gon Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, JAE GON, PARK, BONG IL, SONG, JIN OOK
Publication of US20170117886A1 publication Critical patent/US20170117886A1/en
Priority to US16/388,602 priority Critical patent/US10432183B2/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
US15/290,344 2015-10-21 2016-10-11 Clock generation circuit having deskew function and semiconductor integrated circuit device including same Abandoned US20170117886A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/388,602 US10432183B2 (en) 2015-10-21 2019-04-18 Clock generation circuit having deskew function and semiconductor integrated circuit device including same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020150146933A KR102432457B1 (ko) 2015-10-21 2015-10-21 디스큐 기능을 갖는 클락 발생 회로 및 상기 회로를 포함하는 반도체 집적회로 장치
KR10-2015-0146933 2015-10-21

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/388,602 Division US10432183B2 (en) 2015-10-21 2019-04-18 Clock generation circuit having deskew function and semiconductor integrated circuit device including same

Publications (1)

Publication Number Publication Date
US20170117886A1 true US20170117886A1 (en) 2017-04-27

Family

ID=58490355

Family Applications (2)

Application Number Title Priority Date Filing Date
US15/290,344 Abandoned US20170117886A1 (en) 2015-10-21 2016-10-11 Clock generation circuit having deskew function and semiconductor integrated circuit device including same
US16/388,602 Active US10432183B2 (en) 2015-10-21 2019-04-18 Clock generation circuit having deskew function and semiconductor integrated circuit device including same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US16/388,602 Active US10432183B2 (en) 2015-10-21 2019-04-18 Clock generation circuit having deskew function and semiconductor integrated circuit device including same

Country Status (5)

Country Link
US (2) US20170117886A1 (ko)
KR (1) KR102432457B1 (ko)
CN (1) CN106972842B (ko)
DE (1) DE102016119494A1 (ko)
TW (1) TWI717402B (ko)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10320386B1 (en) * 2017-12-08 2019-06-11 Xilinx, Inc. Programmable pipeline interface circuit
US10432183B2 (en) * 2015-10-21 2019-10-01 Samsung Electronics Co., Ltd. Clock generation circuit having deskew function and semiconductor integrated circuit device including same
CN111756328A (zh) * 2019-03-28 2020-10-09 精工爱普生株式会社 输出电路、电路装置、振荡器、电子设备以及移动体
US20220149821A1 (en) * 2020-11-09 2022-05-12 Samsung Electronics Co., Ltd. Semiconductor circuit

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JPH03213010A (ja) * 1990-01-18 1991-09-18 Sharp Corp クロック発生器
US5461561A (en) 1991-09-10 1995-10-24 Electronic Retailing Systems International Inc. System for recognizing display devices
US5550783A (en) * 1995-04-19 1996-08-27 Alliance Semiconductor Corporation Phase shift correction circuit for monolithic random access memory
US5537062A (en) 1995-06-07 1996-07-16 Ast Research, Inc. Glitch-free clock enable circuit
JPH0951254A (ja) 1995-08-03 1997-02-18 Mitsubishi Electric Corp クロックジェネレータ
US5812462A (en) * 1997-04-03 1998-09-22 Micron Technology, Inc. Integrated circuit clock input buffer
JPH11186901A (ja) * 1997-12-17 1999-07-09 Oki Electric Ind Co Ltd クロック信号生成回路
JP2000114939A (ja) * 1998-10-05 2000-04-21 Nec Corp クロック信号生成装置
US6507230B1 (en) 2000-06-16 2003-01-14 International Business Machines Corporation Clock generator having a deskewer
US6664833B1 (en) * 2000-11-20 2003-12-16 Intersil Americas, Inc. Dual-edge function clock generator and method of deriving clocking signals for executing reduced instruction sequences in a re-programmable I/O interface
KR100384781B1 (ko) * 2000-12-29 2003-05-22 주식회사 하이닉스반도체 듀티 사이클 보정 회로
KR100413761B1 (ko) * 2001-05-31 2003-12-31 삼성전자주식회사 온도와 공정에 따라 리프레시 사이클이 조절되는 반도체메모리 장치 및 방법
JP4883850B2 (ja) * 2001-06-29 2012-02-22 ルネサスエレクトロニクス株式会社 半導体装置
US6917232B2 (en) * 2003-12-10 2005-07-12 Hewlett-Packard Development Company, L.P. Method and apparatus for generating a quadrature clock
JP2005322075A (ja) * 2004-05-10 2005-11-17 Matsushita Electric Ind Co Ltd クロック信号出力装置
CN100338875C (zh) * 2004-11-12 2007-09-19 鸿富锦精密工业（深圳）有限公司 时钟信号发生器
US7353420B2 (en) * 2005-04-07 2008-04-01 Winbond Electronics Corp. Circuit and method for generating programmable clock signals with minimum skew
DE102005049232A1 (de) 2005-10-14 2007-04-26 Infineon Technologies Ag Integrierter Schaltkreis und Verfahren zum Betreiben eines integrierten Schaltkreises
KR100671749B1 (ko) 2006-01-05 2007-01-19 삼성전자주식회사 클럭 분주기
US20070200597A1 (en) * 2006-02-28 2007-08-30 Oakland Steven F Clock generator having improved deskewer
JP2008166910A (ja) * 2006-12-27 2008-07-17 Matsushita Electric Ind Co Ltd クロック信号生成装置及びアナログ−デジタル変換装置
US7443222B1 (en) 2007-05-24 2008-10-28 Quicklogic Corporation Dynamic clock control
US7996807B2 (en) 2008-04-17 2011-08-09 International Business Machines Corporation Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method
TWI462483B (zh) * 2011-06-07 2014-11-21 Himax Imaging Inc 用來產生輸出時脈訊號的時脈產生電路及相關方法
TWI440310B (zh) * 2011-08-09 2014-06-01 Univ Nat Chiao Tung 時間至數位轉換器及數位控制時脈產生器及全數位時脈產生器
EP2629423B1 (en) * 2012-02-20 2018-08-29 Dialog Semiconductor GmbH Fully digital method for generating sub clock division and clock waves
US8736340B2 (en) 2012-06-27 2014-05-27 International Business Machines Corporation Differential clock signal generator
US9712171B2 (en) * 2013-09-11 2017-07-18 Intel Corporation Clocked all-spin logic circuit
KR102432457B1 (ko) * 2015-10-21 2022-08-12 삼성전자주식회사 디스큐 기능을 갖는 클락 발생 회로 및 상기 회로를 포함하는 반도체 집적회로 장치

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10432183B2 (en) * 2015-10-21 2019-10-01 Samsung Electronics Co., Ltd. Clock generation circuit having deskew function and semiconductor integrated circuit device including same
US10320386B1 (en) * 2017-12-08 2019-06-11 Xilinx, Inc. Programmable pipeline interface circuit
US20190181863A1 (en) * 2017-12-08 2019-06-13 Xilinx, Inc. Programmable pipeline interface circuit
CN111756328A (zh) * 2019-03-28 2020-10-09 精工爱普生株式会社 输出电路、电路装置、振荡器、电子设备以及移动体
US11005456B2 (en) * 2019-03-28 2021-05-11 Seiko Epson Corporation Output circuit, circuit device, oscillator, electronic apparatus, and vehicle
US20220149821A1 (en) * 2020-11-09 2022-05-12 Samsung Electronics Co., Ltd. Semiconductor circuit
US11526194B2 (en) * 2020-11-09 2022-12-13 Samsung Electronics Co., Ltd. Semiconductor circuit

Also Published As

Publication number Publication date
TWI717402B (zh) 2021-02-01
CN106972842A (zh) 2017-07-21
DE102016119494A1 (de) 2017-04-27
KR102432457B1 (ko) 2022-08-12
US20190245529A1 (en) 2019-08-08
US10432183B2 (en) 2019-10-01
TW201720058A (zh) 2017-06-01
CN106972842B (zh) 2022-02-11
KR20170046504A (ko) 2017-05-02

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Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SONG, JIN OOK;PARK, BONG IL;LEE, JAE GON;REEL/FRAME:040035/0844

Effective date: 20160607

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION