US20150203753A1 - Liquid etchant composition, and etching process in capacitor process of dram using the same - Google Patents

Liquid etchant composition, and etching process in capacitor process of dram using the same Download PDF

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Publication number
US20150203753A1
US20150203753A1 US14/157,527 US201414157527A US2015203753A1 US 20150203753 A1 US20150203753 A1 US 20150203753A1 US 201414157527 A US201414157527 A US 201414157527A US 2015203753 A1 US2015203753 A1 US 2015203753A1
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United States
Prior art keywords
etchant
tin
tmah
liquid
composition
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Abandoned
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US14/157,527
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English (en)
Inventor
Michael Tristan Andreas
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Nanya Technology Corp
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Nanya Technology Corp
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Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to US14/157,527 priority Critical patent/US20150203753A1/en
Assigned to NANYA TECHNOLOGY CORPORATION reassignment NANYA TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ANDREAS, MICHAEL TRISTAN
Priority to TW103104752A priority patent/TWI553156B/zh
Priority to CN201410100945.0A priority patent/CN104795320A/zh
Publication of US20150203753A1 publication Critical patent/US20150203753A1/en
Priority to US15/176,160 priority patent/US10593559B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L27/1085—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Definitions

  • This invention relates to integrated circuit fabrication, and particularly relates to a liquid etchant composition, and to an etching process in a capacitor process of DRAM (dynamic random access memory) using the liquid etchant composition.
  • a conventional DRAM cell includes a transistor and a capacitor coupled thereto.
  • lower electrodes of the capacitors which are made of TiN, are formed in trenches and/or holes previously formed in a poly-Si layer, an aqueous solution of tetramethylammonium hydroxide (TMAH) is used as an etchant to wet-etch and remove the poly-Si layer, and then a capacitor dielectric layer and an upper electrode are formed covering the surfaces of the lower electrodes.
  • TMAH tetramethylammonium hydroxide
  • a limited etching selectivity of poly-Si to TiN may limit the capacitor height, destroy the structures of the TiN electrodes, or leave behind silicon residuals to cause electrical shorts between the memory cells.
  • this invention provides a liquid etchant composition that has a higher etching selectivity of silicon to TiN.
  • This invention also provides an etching process in a capacitor process of DRAM, which uses the liquid etchant composition to remove the silicon layer containing the lower electrodes.
  • the liquid etchant composition of this invention includes TMAH, an additive including hydroxylamine (HDA) or a metal corrosion inhibitor, and water as a solvent.
  • the etching process in a capacitor process of DRAM of this invention is described as follows.
  • a substrate is provided, which has thereon a silicon layer and a plurality of metal electrodes in the silicon layer.
  • the silicon layer is removed using the liquid etchant composition of this invention.
  • the etching selectivity of Si to the metal material can be much improved by using the liquid etchant composition of this invention.
  • the capacitor height can be increased, the structures of the metal electrodes are not easily destroyed, and silicon residual causing electrical short is not easily left behind.
  • FIG. 1 illustrates, in a cross-sectional view, a capacitor process of DRAM according to an embodiment of this invention.
  • FIG. 2 shows variations of the respective etching rates of poly-Si and TiN (diamond points, left ⁇ -axis) and the poly-Si/TiN etching selectivity (square points, right ⁇ -axis) with the concentration of hydroxylamine in the TMAH-based liquid etchant in Example 1 of this invention.
  • FIG. 3 shows variations of the respective etching rates of poly-Si and TiN (diamond points, left ⁇ -axis) and the poly-Si/TiN etching selectivity (square points, right ⁇ -axis) with the concentration of the TiN corrosion inhibitor in the TMAH-based liquid etchant at 75° C. in Example 2 of this invention.
  • FIG. 4 shows variations of the respective etching rates of poly-Si and TiN (diamond points, left ⁇ -axis) and the poly-Si/TiN etching selectivity (square points, right ⁇ -axis) with the concentration of silicic acid in the TMAH-based liquid etchant in Comparative Example 1.
  • FIG. 1 illustrates, in a cross-sectional view, a capacitor process of DRAM according to an embodiment of this invention.
  • a substrate 100 is provided, on which a plurality of metal contacts 110 , an etching stop layer 120 , a silicon layer 130 , a cap layer 140 have been formed, a plurality of trenches 150 have been formed in the cap layer 140 , the silicon layer 130 and the etching stop layer 120 , and a plurality of metal electrodes 160 as the lower electrodes of the capacitors are formed in the trenches 150 .
  • the metal contacts 110 may include TiN, Ru or TaN.
  • the etching stop layer 120 may include silicon nitride (SiN) or silicon oxide.
  • the silicon layer 130 may include poly-Si.
  • the cap layer 140 may include SiN.
  • the metal electrodes 160 may include TiN, Ru or TaN.
  • a liquid etchant composition is used to wet-etch and remove the silicon layer 130 to expose the outer surfaces of the metal electrodes 160 .
  • the liquid etchant composition contains tetramethylammonium hydroxide (TMAH), an additive including hydroxylamine or a metal corrosion inhibitor, and water as a solvent.
  • TMAH tetramethylammonium hydroxide
  • the above wet etching is conducted suitably at a temperature of 70-80° C.
  • the amount of TMAH relative to the total weight of the etchant liquid composition is suitably within the range of 4.5-5.5 wt %, usually about 5 wt %.
  • the additive includes hydroxylamine
  • the amount of hydroxylamine relative to the total weight of the etchant liquid composition is suitably with the range of 0.3-0.7 wt %
  • the wet etching is suitably conducted at a temperature within the range of 70-80° C.
  • the amount of the metal corrosion inhibitor relative to the total weight of the etchant liquid composition is suitably within the range of 1 to 5 wt %, depending on the species of the metal corrosion inhibitor, and the wet etching is suitably conducted at a temperature within the range of 70-80° C.
  • the metal corrosion inhibitor includes a TiN corrosion inhibitor, which may include at least one compound selected from the group consisting of diprotic carboxylic acids and phenolic compounds.
  • diprotic carboxylic acids include oxalic acid, malonic acid, and succinic acid, etc.
  • phenolic compounds include phenol, 4-nitrophenol, and 4-hydroxybenzoic acid, etc.
  • Subsequent steps include depositing a capacitor dielectric layer on the inner and outer surfaces of each lower electrode 160 , and then depositing a top electrode over the dielectric layer. These are well known in the art and are not described in details herein.
  • a wafer having thereon a TiN layer of about 10 nm, and another wafer having thereon a poly-Si layer of about 1000 nm were provided.
  • a 1.0 wt % HF solution was used to treat the surface of the TiN layer for 60 seconds and to remove any SiO x on the surface of the poly-Si layer for 30 seconds, distill water was used to rinse both wafers for 30 seconds, and a 5 wt % TMAH solution (purchased from Moses Lake Industries) added with a given amount of hydroxylamine (purchased from Sigma Aldrich) was used to etch the TiN layer at 75° C. for 20 minutes and etch the poly-Si at 75° C. for 10 seconds.
  • TMAH solution purchased from Moses Lake Industries
  • TMAH solutions having been used to etch the TiN layer and the poly-Si layer respectively were then analyzed by ICP-OES (inductively couple plasma optical emission spectrometry) for respective contents of titanium and silicon.
  • ICP-OES inductively couple plasma optical emission spectrometry
  • the measured contents were used to derive the respective etching rates of TiN and poly-Si.
  • FIG. 2 shows variations of the respective etching rates of poly-Si and TiN (diamond points, left ⁇ -axis) and the poly-Si/TiN etching selectivity (square points, right ⁇ -axis) with the concentration of hydroxylamine in the TMAH-based liquid etchant in Example 1 of this invention.
  • the data of the etching rate is also listed in Table 1.
  • a wafer having thereon a TiN layer of about 10 nm, and another wafer having thereon a poly-Si layer of about 1000 nm were provided.
  • a 0.5 wt % HF solution was used to treat the surface of the TiN layer and to remove any SiO x on the surface of the poly-Si layer for 2 minutes
  • a 5 wt % TMAH solution added with a given amount of a TiN corrosion inhibitor, which was provided by Tokyo Ohka Kogyo Co., Ltd. (TOK) and called ST-B046, was used to etch the TiN layer and the poly-Si layer at 75° C. or 80° C. for 6 minutes.
  • a 0.5 wt % HF solution was then used to remove any TiO x on the surface of the TiN layer and to treat the surface of the poly-Si layer for 1 minute.
  • the thickness of the remaining TiN layer was measured by the ellipsometry technique to derive the loss of the TiN thickness.
  • the thickness of the remaining poly-Si layer was measured with X-section SEM to derive the loss of the poly-Si thickness.
  • a wafer having thereon a TiN layer of about 10 nm, and another wafer having thereon a poly-Si layer of about 1000 nm were provided.
  • a 1.0 wt % HF solution was used to treat the surface of the TiN layer and to remove any SiO x on the surface of the poly-Si layer for 60 seconds, distill water was used to rinse both wafers for 30 seconds, and a 5 wt % TMAH solution (produced by Moses Lake) containing a given amount of silicic acid (produced by Sigma-Aldrich) was used to etch the TiN layer and the poly-Si layer at 75° C. for 20 minutes.
  • TMAH solutions having been used to etch the TiN layer was then analyzed by ICP-OES for the content of titanium.
  • the measured content was used to derive the etching rate of TiN.
  • the thickness loss of the poly-Si layer was not measured, because previous experience with silica loading in TMAH suggested no change to Poly-Si etching rate within this range of silicic acid addition.
  • FIG. 4 shows variations of the respective etching rates of poly-Si and TiN (diamond points, left ⁇ -axis) and the poly-Si/TiN etching selectivity (square points, right ⁇ -axis) with the concentration of silicic acid in Comparative Example 1. It is clear from FIG. 4 that by using silicic acid, the etching rate of TiN was increased significantly. Since the etching rate of poly-Si is almost unchanged, the etching selectivity of poly-Si to TiN is significantly lowered by using the liquid etchant composition of this comparative example, as shown in FIG. 4 .
  • the etching selectivity of Si to TiN can be remarkably improved by using the liquid etchant composition of the above embodiment.
  • the capacitor height can be increased, the container structures are not easily destroyed, and silicon residual causing electrical short is not easily left behind.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Weting (AREA)
US14/157,527 2014-01-17 2014-01-17 Liquid etchant composition, and etching process in capacitor process of dram using the same Abandoned US20150203753A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US14/157,527 US20150203753A1 (en) 2014-01-17 2014-01-17 Liquid etchant composition, and etching process in capacitor process of dram using the same
TW103104752A TWI553156B (zh) 2014-01-17 2014-02-13 液體蝕刻劑組成物，以及在ｄｒａｍ之電容器製程中使用上述液體蝕刻劑組成物之蝕刻製程
CN201410100945.0A CN104795320A (zh) 2014-01-17 2014-03-18 液体蚀刻剂组成物以及蚀刻过程
US15/176,160 US10593559B2 (en) 2014-01-17 2016-06-08 Etching process in capacitor process of DRAM using a liquid etchant composition

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US14/157,527 US20150203753A1 (en) 2014-01-17 2014-01-17 Liquid etchant composition, and etching process in capacitor process of dram using the same

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Cited By (1)

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US10177146B2 (en) * 2016-10-10 2019-01-08 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure with improved punch-through and fabrication method thereof

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US11164938B2 (en) * 2019-03-26 2021-11-02 Micromaterials Llc DRAM capacitor module
CN112480928A (zh) * 2019-09-11 2021-03-12 利绅科技股份有限公司 硅蚀刻组成物及其作用于硅基材的蚀刻方法
US20220290049A1 (en) * 2021-03-12 2022-09-15 LCY Chemical Corp. Composition of etchant, method for forming semiconductor device using the same, and semiconductor device

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TW201529897A (zh) 2015-08-01
US10593559B2 (en) 2020-03-17
US20160293448A1 (en) 2016-10-06
TWI553156B (zh) 2016-10-11
CN104795320A (zh) 2015-07-22

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