US20120146728A1 - Compound semiconductor device and method of manufacturing the same - Google Patents

Compound semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
US20120146728A1
US20120146728A1 US13/278,392 US201113278392A US2012146728A1 US 20120146728 A1 US20120146728 A1 US 20120146728A1 US 201113278392 A US201113278392 A US 201113278392A US 2012146728 A1 US2012146728 A1 US 2012146728A1
Authority
US
United States
Prior art keywords
insulating film
compound semiconductor
gate insulating
gate
hydrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/278,392
Other languages
English (en)
Inventor
Kozo Makiyama
Toshihide Kikkawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MAKIYAMA, KOZO, KIKKAWA, TOSHIHIDE
Publication of US20120146728A1 publication Critical patent/US20120146728A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Definitions

  • the present embodiments relate to a compound semiconductor device and a method of manufacturing the same.
  • a nitride semiconductor device has been actively developed as a high withstand voltage and high output semiconductor device by utilizing its characteristics of a high saturation electron velocity, a wide band gap, and so on.
  • a field effect transistor particularly a high electron mobility transistor (High Electron Mobility Transistor: HEMT) have been made.
  • HEMT High Electron Mobility Transistor
  • AlGaN/GaN-HEMT In which GaN is used as an electron transit layer and AlGaN is used as an electron supply layer.
  • distortion ascribable to a lattice constant difference between GaN and AlGaN occurs in AlGaN.
  • a high-concentration two-dimensional electron gas (2DEG) is obtained.
  • 2DEG high-concentration two-dimensional electron gas
  • the nitride semiconductor device used in high voltage application is likely to be affected by charge traps existing in an insulating film, on the front surface of a semiconductor, in the inside of crystals, and so on of the device, and has a problem that electric properties (current-voltage property, gain property, output property, collapse, and so on) change according to its operating state.
  • the charge traps existing in the structure of the semiconductor device vary a potential distribution around the periphery of the traps by activation (electrification) by electric fields or by traps of electrons and holes. As a result, the electric properties change to thereby affect the stable operation of the semiconductor device.
  • a change in threshold voltage during its operation a change in current amount accompanied by the above change, and a change in gain appear.
  • As a semiconductor device having stable electric properties it is necessary to make a mechanism in which the change in electric properties is suppressed, namely a trap phenomenon or the like is mitigated inside the device.
  • a reduction in the charge traps or inactivation around the periphery of a gate electrode and in a gate insulating film, where electric fields concentrate, and which are easily affected by the traps is an important problem.
  • An aspect of the compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed on the compound semiconductor layer via a gate insulating film, in which the gate insulating film is one in which Si x N y is contained as an insulating material, the Si x N y is 0.638 ⁇ x/y ⁇ 0.863, and a hydrogen-terminated group concentration is set to a value within a range of not less than 2 ⁇ 10 22 /cm 3 nor more than 5 ⁇ 10 22 /cm 3 .
  • An aspect of the method of manufacturing the compound semiconductor device includes: forming a gate insulating film on a compound semiconductor layer; and forming a gate electrode on the compound semiconductor layer via the gate insulating film, in which the gate insulating film is one in which Si x N y is contained as an insulating material, the Si x N y is 0.638 ⁇ x/y ⁇ 0.863 and a hydrogen-terminated group concentration is set to a value within a range of not less than 2 ⁇ 10 22 /cm 3 nor more than 5 ⁇ 10 22 /cm 3 .
  • FIG. 1A to FIG. 1C are schematic cross-sectional views depicting a method of manufacturing a MIS-type AlGaN/GaN-HEMT according to a first embodiment in order of processes;
  • FIG. 2A and FIG. 2B are schematic cross-sectional views, subsequent to FIG. 1A to FIG. 1C , depicting the method of manufacturing the MIS-type AlGaN/GaN-HEMT according to the first embodiment in order of processes;
  • FIG. 3A and FIG. 3B are schematic cross-sectional views, subsequent to FIG. 2A and FIG. 2B , depicting the method of manufacturing the MIS-type AlGaN/GaN-HEMT according to the first embodiment in order of processes;
  • FIG. 4 is a schematic view depicting a bonding state of SiN of a gate insulating film formed according to the first embodiment
  • FIG. 5A to FIG. 5C are characteristic charts depicting results of various experiments for confirming a good application range of a hydrogen-terminated group concentration in SiN in the first embodiment
  • FIG. 6A and FIG. 6B are characteristic charts depicting results of various experiments for confirming a good application range of an interatomic hydrogen concentration in SiN in the first embodiment
  • FIG. 7A to FIG. 7C are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 1 of the first embodiment
  • FIG. 8A to FIG. 8C are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 2 of the first embodiment;
  • FIG. 9A and FIG. 9B are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 3 of the first embodiment
  • FIG. 10A and FIG. 10B are schematic cross-sectional views, subsequent to FIG. 9A and FIG. 9B , depicting the main processes of the MIS-type AlGaN/GaN-HEMT according to the modified example 3 of the first embodiment;
  • FIG. 11A and FIG. 11B are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a second embodiment
  • FIG. 12A to FIG. 12C are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 1 of the second embodiment;
  • FIG. 13A to FIG. 13C are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 2 of the second embodiment;
  • FIG. 14A and FIG. 14B are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 3 of the second embodiment;
  • FIG. 15A and FIG. 15B are schematic cross-sectional views, subsequent to FIG. 14A and FIG. 14B , depicting the main processes of the MIS-type AlGaN/GaN-HEMT according to the modified example 3 of the second embodiment;
  • FIG. 16 is a connection diagram depicting a schematic structure of a power supply device according to a fourth embodiment.
  • FIG. 17 is a connection diagram depicting a schematic structure of a high-frequency amplifier according to a fifth embodiment.
  • a MIS-type AlGaN/GaN-HEMT is disclosed as a compound semiconductor device.
  • FIG. 1A to FIG. 1C to FIG. 3A and FIG. 3B are schematic cross-sectional views depicting a method of manufacturing a MIS-type AlGaN/GaN-HEMT according to a first embodiment in order of processes.
  • a compound semiconductor layer 2 is formed on, for example, a semi-insulating SiC substrate 1 as a substrate for growth.
  • the compound semiconductor layer 2 is structured to include: a buffer layer 2 a ; an electron transit layer 2 b ; an intermediate layer 2 c ; an electron supply layer 2 d ; and a cap layer 2 e .
  • a two-dimensional electron gas (2DEG) is produced in the vicinity of an interface of the electron transit layer 2 b with the electron supply layer 2 d (intermediate layer 2 c , correctly).
  • MOVPE Metal Organic Vapor Phase Epitaxy
  • MBE molecular beam epitaxy
  • AlN, n-(intentionally-undoped)-GaN, i-AlGaN, n-AlGaN, and n-GaN are sequentially deposited, and the buffer layer 2 a , the electron transit layer 2 b , the intermediate layer 2 c , the electron supply layer 2 d , and the cap layer 2 e are layered and formed.
  • a mixed gas of a trimethylaluminium gas, a trimethylgallium gas, and an ammonia gas is used as a source gas.
  • the trimethylaluminium gas being an Al source and the trimethylgallium gas being a Ga source are supplied and flow rates of them are appropriately set.
  • a flow rate of the ammonia gas being a common raw material is set to 100 ccm to 10 LM or so.
  • a growth pressure is set to 50 Torr to 300 Torr or so, and a growth temperature is set to 1000° C. to 1200° C. or so.
  • n-type impurity for example, a SiH 4 gas containing Si, for example, is added to the source gas at a predetermined flow rate, and Si is doped in GaN and AlGaN.
  • a doping concentration of Si is set to 1 ⁇ 10 18 /cm 3 or so to 1 ⁇ 10 20 /cm 3 or so, and is set to, for example, 5 ⁇ 10 18 /cm 3 or so.
  • the buffer layer 2 a is formed to have a film thickness of 0.1 ⁇ m or so
  • the electron transit layer 2 b is formed to have a film thickness of 3 ⁇ m or so
  • the intermediate layer 2 c is formed to have a film thickness of 5 nm or so
  • the electron supply layer 2 d is formed to have a film thickness of 20 nm or so and to have an Al ratio of 0.2 to 0.3 or so, for example
  • the cap layer 2 e is formed to have a film thickness of 10 nm or so.
  • element isolation structures 3 are formed.
  • argon (Ar) is injected into element isolation regions of the compound semiconductor layer 2 .
  • the element isolation structures 3 are formed in the compound semiconductor layer 2 and portions of a surface layer of the SiC substrate 1 .
  • active regions are demarcated on the compound semiconductor layer 2 .
  • the element isolation may also be performed with the use of the STI (Shallow Trench Isolation) method, for example, in place of the above-described injection method.
  • STI Shallow Trench Isolation
  • a source electrode 4 and a drain electrode 5 are formed.
  • electrode trenches 2 A, 2 B are formed in the cap layer 2 e being formation planned positions for forming the source electrode and the drain electrode on the front surface of the compound semiconductor layer 2 .
  • a resist mask opening at the formation planned positions for forming the source electrode and the drain electrode on the front surface of the compound semiconductor layer 2 is formed.
  • the cap layer 2 e is dry-etched and is removed.
  • the electrode trenches 2 A, 2 B are formed.
  • an inert gas such as Ar
  • a chlorine-based gas such as Cl 2 are used as an etching gas.
  • the electrode trenches may also be formed in a manner that the dry etching is performed to a surface layer portion of the electron supply layer 2 d through the cap layer 2 e.
  • Ta/Al is used, for example.
  • a two-layer resist in an eaves structure suitable for the vapor deposition method and the lift-off method is used.
  • the above resist is applied on the compound semiconductor layer 2 and the resist mask opening at the electrode trenches 2 A, 2 B is formed.
  • Ta/Al is deposited.
  • the thickness of Ta is set to 20 nm or so
  • the thickness of Al is set to 200 nm or so.
  • the resist mask in an eaves structure and Ta/Al deposited thereon are removed. Thereafter, the SiC substrate 1 is subjected to a heat treatment at 550° C.
  • the source electrode 4 and the drain electrode 5 in which the electrode trenches 2 A, 2 B are filled with a lower portion of Ta/Al are formed.
  • a resist mask 10 for forming an electrode trench for a gate electrode is formed.
  • a resist is applied on the compound semiconductor layer 2 .
  • the resist is processed by the lithography, and an opening 10 a is formed at a formation planned position for forming the gate electrode.
  • the resist mask 10 in which the front surface of the cap layer 2 e to be the formation planned position for forming the gate electrode is exposed from the opening 10 a is formed.
  • an electrode trench 2 C is formed at the formation planned position for forming the gate electrode.
  • dry etching is performed so as to pass through the cap layer 2 e and leave one portion of the electron supply layer 2 d , and the cap layer 2 e is removed.
  • an inert gas such as Ar and a chlorine-based gas such as Cl 2 are used as an etching gas.
  • the thickness of the remaining portion of the electron supply layer 2 d is set to 0 nm to 20 nm or so, and is set to 1 nm or so, for example.
  • the electrode trench 2 C is formed.
  • methods of, for example, wet etching, ion milling, and so on can also be used in place of the above-described dry etching.
  • the resist mask 10 is removed by an ashing treatment.
  • a gate insulating film 6 is formed.
  • a silicon nitride film (SiN film) is deposited to have a film thickness in a range of 2 nm to 200 nm, which is 20 nm or so, for example, so as to cover the entire surface on the compound semiconductor layer 2 including the top of the source electrode 4 and the top of the drain electrode 5 .
  • the gate insulating film 6 is formed.
  • Concrete film forming conditions of the PECVD include source gas species, flow rates of the source gas species, pressure, RF power, and frequency of PF power.
  • a mixed gas of SiH 4 , NH 3 , N 2 , and He is used, and the flow rate of SiH 4 is set to 3 sccm, the flow rate of NH 3 is set to 1 sccm, the flow rate of N 2 is set to 150 sccm, and the flow rate of He is set to 1000 sccm.
  • the RF power in the PECVD is set relatively low within the limit of allowing plasma to be generated.
  • reaction rate determining state a state of an excess amount of source gas
  • pressure P and RF power P RF are set as follows.
  • the pressure is determined uniquely with the use of the constant ⁇ .
  • the pressure is set to, for example, 1500 mTorr or so
  • the RF power is set to, for example, 80 W or so
  • the frequency of RF power is set to 13.56 MHz.
  • a bonding state of SiN of the gate insulating film 6 formed according to this embodiment is depicted in FIG. 4 .
  • SiN of the gate insulating film 6 unbonded bonds caused by bonding defects of Si and N that are inevitably included in SiN are sufficiently terminated by hydrogen (H) (hereinafter, the bonding defects of Si and N are simply described as dangling bonds).
  • H hydrogen
  • the ratio of the unbonded bonds terminated by hydrogen to all the dangling bonds can be evaluated to be sufficient for reducing charge traps in the gate insulating film 6 .
  • collapse of terminated hydrogen bonding groups due to thermal change is expected to occur, so that excess interatomic hydrogen having a concentration sufficient to compensate the collapse is contained in SiN.
  • the disposition of high-concentration interatomic hydrogen makes it possible to cause the hydrogen termination again even in the case when a dehydrogenation reaction progresses by heating and then hydrogen is released to the outside from SiN.
  • SiN of the SiN film is represented as Si x N y
  • a composition ratio x/y of Si/N is set to
  • a hydrogen-terminated group concentration C H1 is set to a value within a range of
  • an interatomic hydrogen concentration C H2 is set to a value within a range of
  • composition ratio x/y of Si/N fall within the range of (3/4) ⁇ 15% means that SiN is allowed to slightly deviate from the composition of Si 3 N 4 and it is directed that the dangling bonds of SiN are compensated by hydrogen.
  • the hydrogen-terminated group concentration C H1 When the hydrogen-terminated group concentration C H1 is smaller than 2 ⁇ 10 22 /cm 3 , it becomes difficult to sufficiently terminate the above-described dangling bonds by hydrogen. When the hydrogen-terminated group concentration C H1 is larger than 5 ⁇ 10 22 /cm 3 , the hydrogen-terminated group concentration C H1 is not actual as SiN, and it becomes impossible to secure sufficient insulation performance as the gate insulating film. Thus, setting the hydrogen-terminated group concentration C H1 to a value within the above-described range makes it possible to sufficiently terminate the dangling bonds by hydrogen while maintaining the excellent property as the gate insulating film.
  • a relationship between the hydrogen-terminated group concentration C H1 and a current collapse ratio was examined.
  • a drain voltage Vd is applied to SiN to be the maximum value
  • a drain voltage Id in the predetermined drain voltage Vd (for example, 5 V) is set to Id 1 .
  • the drain voltage Vd is applied to SiN to be a value smaller than that in the above-described case
  • the drain voltage Id in the predetermined drain voltage Vd (for example, 5 V) is set to Id 2 .
  • the current collapse ratio is defined as (Id 1 /Id 2 ) ⁇ 100(%).
  • FIG. 5A A result of the experiment 1 is depicted in FIG. 5A
  • a result of the experiment 2 is depicted in FIG. 5B
  • a result of the experiment 3 is depicted in FIG. 5C respectively.
  • the leak current becomes a substantially constant low value.
  • the value of the hydrogen-terminated group concentration C H1 exceeds 5 ⁇ 10 22 /cm 3 , the value of the leak current steeply increases. From the above result, the upper limit value of the hydrogen-terminated group concentration C H1 of SiN according to this embodiment can be evaluated to be 5 ⁇ 10 22 /cm 3 or so in order to suppress the leak current to a low value.
  • the concentration corresponding to unpaired electrons becomes a substantially constant low value.
  • the value of the hydrogen-terminated group concentration C H1 falls short of 2 ⁇ 10 22 /cm 3
  • the value of the concentration corresponding to unpaired electrons steeply increases. From the above result, the lower limit value of the hydrogen-terminated group concentration C H1 of SiN according to this embodiment can be evaluated to be 2 ⁇ 10 22 /cm 3 or so in order to sufficiently terminate the dangling bonds of SiN by hydrogen.
  • the hydrogen-terminated group concentration C H1 when the value of the hydrogen-terminated group concentration C H1 is 2 ⁇ 10 22 /cm 3 or more, the high current collapse ratio of 95% or so or more is maintained.
  • the value of the hydrogen-terminated group concentration C H1 falls short of 2 ⁇ 10 22 /cm 3 , the current collapse ratio steeply reduces. From the above result, the lower limit value of the hydrogen-terminated group concentration C H1 of SiN according to this embodiment can be evaluated to be 2 ⁇ 10 22 /cm 3 or so in order to maintain the high current collapse ratio.
  • the hydrogen-terminated group concentration C H1 in SiN in this embodiment is prescribed to be not less than 2 ⁇ 10 22 /cm 3 nor more than 5 ⁇ 10 22 /cm 3 , and thereby it is confirmed that the excellent gate insulating film in which an amount of the leak current is reduced and the dangling bonds are reduced is obtained.
  • the interatomic hydrogen concentration C H2 When the interatomic hydrogen concentration C H2 is smaller than 2 ⁇ 10 21 /cm 3 , it becomes difficult to sufficiently compensate the collapse of terminated hydrogen bonding groups. When the interatomic hydrogen concentration C H2 is larger than 6 ⁇ 10 21 /cm 3 , it becomes impossible to secure sufficient insulation performance as the gate insulating film. Thus, setting the interatomic hydrogen concentration C H2 to a value within the above-described range makes it possible to sufficiently compensate the collapse of terminated hydrogen bonding groups without causing a problem when the gate insulating film is used.
  • the leak current becomes a substantially constant low value.
  • the value of the interatomic hydrogen concentration C H2 exceeds 6 ⁇ 10 21 /cm 3 , the value of the leak current steeply increases. From the above result, the upper limit value of the interatomic hydrogen concentration C H2 of SiN according to this embodiment can be evaluated to be 6 ⁇ 10 21 /cm 3 or so in order to suppress the leak current to a low value.
  • the lower limit value of the interatomic hydrogen concentration C H2 of SiN according to this embodiment can be evaluated to be 2 ⁇ 10 21 /cm 3 or so.
  • the interatomic hydrogen concentration C H2 in SiN in this embodiment is prescribed to be not less than 2 ⁇ 10 21 /cm 3 nor more than 6 ⁇ 10 21 /cm 3 , and thereby it is confirmed that the excellent gate insulating film in which the reduced dangling bonds are maintained even if the collapse of hydrogen bonding groups due to thermal change occurs is obtained.
  • the composition ratio x/y of Si/N is measured by the X-ray photoelectron spectroscopy method (X-ray Photoelectron Spectroscopy: XPS).
  • the hydrogen-terminated group concentration C H1 is measured by the infrared absorption method.
  • the interatomic hydrogen concentration C H2 is measured by the hydrogen forward scattering method (Hydrogen Forward Scattering: HFS) and the Rutherford backscattering spectrometry method (Rutherford Backscattering Spectrometry: RBS).
  • the composition ratio x/y of Si/N is set to, for example, (0.84) or so
  • the hydrogen-terminated group concentration C H1 is set to, for example, 2.1 ⁇ 10 22 /cm 3 or so
  • the interatomic hydrogen concentration C H2 is set to, for example, 3 ⁇ 10 21 /cm 3 or so.
  • a concentration corresponding to remaining unpaired electrons is measured by the electron spin resonance method (Electron Spin Resonance: ESR) and 2.6 ⁇ 10 18 /cm 3 or so is obtained.
  • the gate insulating film 6 formed of the above SiN film is a film in which its composition is close to Si 3 N 4 , the dangling bonds are sufficiently terminated by hydrogen (H), and interatomic hydrogen having a concentration sufficient to compensate the collapse of hydrogen bonding groups is contained.
  • the above gate insulating film 6 is formed in a state where the dangling bonds are quite reduced and charge traps are significantly reduced.
  • a gate electrode 7 is formed.
  • a lower-layer resist for example, brand name PMGI: made by MicroChem Corp, U.S.
  • an upper-layer resist for example, brand name PF132-A8: made by Sumitomo Chemical Company, Limited
  • An opening of, for example, 1.5 ⁇ m or so in diameter is formed in the upper-layer resist by ultraviolet exposure.
  • the upper-layer resist is used as a mask, and the lower-layer resist is wet etched with an alkaline developing solution.
  • the upper-layer resist and the lower-layer resist are used as a mask, and a gate metal (Ni: 10 nm or so in film thickness/Au: 300 nm or so in film thickness) is vapor deposited on the entire surface including the inside of the opening.
  • a gate metal Ni: 10 nm or so in film thickness/Au: 300 nm or so in film thickness
  • the SiC substrate 1 is soaked in N-methyl-pyrrolidinone heated to 80° C., and the lower-layer resist and the upper-layer resist and the unnecessary gate metal are removed by the lift-off method.
  • the gate electrode 7 in which the electrode trench 2 C is filled with part of the gate metal via the gate insulating film 6 is formed.
  • the MIS-type AlGaN/GaN-HEMT is formed.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film 6 (particularly, charge traps on an interface of the gate insulating film 6 with the gate electrode 7 and in a vicinity region of the interface, or on an interface of the gate insulating film 6 with the compound semiconductor layer 2 and in a vicinity region of the interface) are significantly reduced and a change in electric properties is suppressed.
  • a MIS-type AlGaN/GaN-HEMT is disclosed as a compound semiconductor device, but differs from that in the first embodiment in that the structure of the gate insulating film is slightly different.
  • FIG. 7A to FIG. 7C are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 1 in the first embodiment.
  • the MIS-type AlGaN/GaN-HEMT undergoes the various processes in FIG. 1A to FIG. 2B .
  • An electrode trench 2 C for a gate electrode is formed in a compound semiconductor layer 2 .
  • a gate insulating film 11 is formed.
  • a first insulating film 11 a is formed.
  • a SiN film is deposited to have a film thickness of 5 nm or so by the PECVD method so as to cover the entire surface on the compound semiconductor layer 2 including the top of a source electrode 4 and the top of a drain electrode 5 .
  • the first insulating film 11 a is formed.
  • the first insulating film 11 a is formed to have the same composition and property as those of the gate insulating film 6 in the first embodiment except that the film thickness is different.
  • a second insulating film 11 b is formed.
  • insulating material of the second insulating film 11 b As an insulating material of the second insulating film 11 b , a material having a band gap higher than that of SiN of the first insulating film 11 a is used. As the insulating material of the second insulating film 11 b , alumina (Al 2 O 3 ), aluminum nitride (AlN), tantalum oxide (TaO), and so on are cited. Here, the case of using Al 2 O 3 is described as an example.
  • the first insulating film 11 a Al 2 O 3 is deposited to have a film thickness of 15 nm or so by the atomic layer deposition method (Atomic Layer Deposition: ALD method), for example.
  • ALD method atomic layer deposition method
  • the second insulating film 11 b is formed.
  • the deposition of Al 2 O 3 may also be performed by, for example, the CVD method or the like in place of the ALD method.
  • the gate insulating film 11 in which the first insulating film 11 a and the second insulating film 11 b are sequentially layered is formed so as to cover the top of the compound semiconductor layer 2 including an internal surface of the electrode trench 2 C.
  • the gate insulating film 11 includes the first insulating film 11 a , so that dangling bonds are quite reduced and charge traps are significantly reduced. Further, the gate insulating film 11 includes the second insulating film 11 b , so that a gate withstand voltage of the gate electrode is improved. That is, the application of the gate insulating film 11 makes it possible to achieve a significant reduction in charge trap density while achieving the high gate withstand voltage of the gate electrode.
  • a gate electrode 7 is formed through the process in FIG. 3B .
  • the MIS-type AlGaN/GaN-HEMT is formed.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film 11 (particularly, charge traps on an interface of the gate insulating film 11 with the compound semiconductor layer 2 and in a vicinity region of the interface) are significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode 7 .
  • FIG. 8A to FIG. 8C are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 2 in the first embodiment.
  • the MIS-type AlGaN/GaN-HEMT undergoes the various processes in FIG. 1A to FIG. 2B .
  • An electrode trench 2 C for a gate electrode is formed in a compound semiconductor layer 2 .
  • a gate insulating film 21 is formed.
  • Al 2 O 3 is deposited to have a film thickness of 45 nm or so by the ALD method so as to cover the entire surface on the compound semiconductor layer 2 including the top of a source electrode 4 and the top of a drain electrode 5 . Thereby, a first insulating film 21 a is formed.
  • a SiC substrate 1 may also be subjected to a heat treatment.
  • the SiC substrate 1 is heated for 5 minutes or so in a range of 400° C. to 1200° C., for example. Thereby, a bonding state of the first insulating film 21 a is improved.
  • hydrogen termination collapse of the gate insulating film 21 is suppressed, and a state of a stable and low concentration corresponding to unpaired electrons is maintained.
  • Al 2 O 3 in which the bonding state is improved by the heat treatment is employed, and thereby a gate withstand voltage is further stabilized.
  • SiN is deposited on the first insulating film 21 a to have a film thickness of 5 nm or so by the PECVD method.
  • a second insulating film 21 b is formed.
  • the second insulating film 21 b is formed to have the same composition and property as those of the gate insulating film 6 in the first embodiment except that the film thickness is different.
  • the gate insulating film 21 in which the first insulating film 21 a and the second insulating film 21 b are sequentially layered is formed so as to cover the top of the compound semiconductor layer 2 including an internal surface of the electrode trench 2 C.
  • the gate insulating film 21 includes the second insulating film 21 b , so that dangling bonds are quite reduced and charge traps are significantly reduced. Further, the gate insulating film 21 includes the first insulating film 21 a , so that the gate withstand voltage of the gate electrode is improved. That is, the application of the gate insulating film 21 makes it possible to achieve a significant reduction in charge trap density while achieving the high gate withstand voltage of the gate electrode.
  • a gate electrode 7 is formed through the process in FIG. 3B .
  • the MIS-type AlGaN/GaN-HEMT is formed.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film 21 (particularly, charge traps on an interface of the gate insulating film 21 with the gate electrode 7 and in a vicinity region of the interface) are significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode 7 .
  • FIG. 9A and FIG. 9B and FIG. 10A and FIG. 10B are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 3 in the first embodiment.
  • the MIS-type AlGaN/GaN-HEMT undergoes the various processes in FIG. 1A to FIG. 2B .
  • An electrode trench 2 C for a gate electrode is formed in a compound semiconductor layer 2 .
  • a gate insulating film 31 is formed.
  • SiN is deposited to have a film thickness of 5 nm or so by the PECVD method so as to cover the entire surface on a SiC substrate 1 including the top of a source electrode 4 and the top of a drain electrode 5 .
  • a first insulating film 31 a is formed.
  • the first insulating film 31 a is formed to have the same composition and property as those of the gate insulating film 6 in the first embodiment except that the film thickness is different.
  • SiN is deposited on the second insulating film 31 b to have a film thickness of 5 nm or so by the PECVD method.
  • a third insulating film 31 c is formed.
  • the third insulating film 31 c is formed to have the same composition and property as those of the gate insulating film 6 in the first embodiment except that the film thickness is different.
  • the gate insulating film 31 in which the first insulating film 31 a , the second insulating film 31 b , and the third insulating film 31 c are sequentially layered is formed so as to cover the top of the compound semiconductor layer 2 including an internal surface of the electrode trench 2 C.
  • the gate insulating film 31 includes the first and third insulating films 31 a , 31 c , so that dangling bonds are quite reduced and charge traps are significantly reduced. Further, in the above case, the structure in which the second insulating film 31 b is sandwiched between the first insulating film 31 a and the third insulating film 31 c is made, so that a state where dangling bonds on the front surface and rear surface of the gate insulating film 31 are quite reduced and charge traps are significantly reduced is made. Further, the gate insulating film 31 includes the second insulating film 31 b , so that a gate withstand voltage of the gate electrode is improved. That is, the application of the gate insulating film 31 makes it possible to achieve a further significant reduction in charge trap density while achieving the high gate withstand voltage of the gate electrode.
  • a gate electrode 7 is formed through the process in FIG. 3B .
  • the MIS-type AlGaN/GaN-HEMT is formed.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film 31 (particularly, charge traps on an interface of the gate insulating film 31 with the gate electrode 7 and in a vicinity region of the interface, or on an interface of the gate insulating film 31 with the compound semiconductor layer 2 and in a vicinity region of the interface) are significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode 7 .
  • a MIS-type AlGaN/GaN-HEMT is disclosed as a compound semiconductor device, but differs from that of the first embodiment in that the structure of the gate insulating film is different.
  • FIG. 11A and FIG. 11B are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a second embodiment.
  • the MIS-type AlGaN/GaN-HEMT undergoes the various processes in FIG. 1A to FIG. 2B .
  • An electrode trench 2 C for a gate electrode is formed in a compound semiconductor layer 2 .
  • a gate insulating film 41 is formed.
  • a silicon oxynitride film (SiON film) is deposited to have a film thickness in a range of 2 nm to 200 nm, which is for example, 20 nm or so, so as to cover the entire surface on a SiC substrate 1 including the top of a source electrode 4 and the top of a drain electrode 5 .
  • the gate insulating film 41 is formed.
  • Concrete film forming conditions of the PECVD include source gas species, flow rates of the source gas species, pressure, RF power, and frequency of PF power.
  • a mixed gas of SiH 4 , NH 3 , N 2 O, and N 2 is used, and the flow rate of SiH 4 is set to 3 sccm, the flow rate of NH 3 is set to 3 sccm, the flow rate of N 2 O is set to 5 sccm, and the flow rate of N 2 is set to 1000 sccm respectively.
  • the RF power in the PECVD is set relatively low within the limit of allowing plasma to be generated.
  • reaction rate determining state a state of an excess amount of source gas (reaction rate determining state)
  • SiON is in the reaction rate determining state.
  • pressure P and RF power P RF are set as follows.
  • the pressure is determined uniquely with the use of the constant ⁇ .
  • the pressure is set to, for example, 1500 mTorr or so
  • the RF power is set to, for example, 50 W or so
  • the frequency of RF power is set to 13.56 MHz.
  • SiON has a property in which at the time when atomic bonding is produced, an effect of alleviating bond distortion is enhanced and bonding defects do not occur easily. Further, SiON deposited as described above do not have many unbonded bonds caused by bonding defects of Si, O, and N that are inevitably included in SiON (hereinafter, the bonding defects of Si, O, and N are simply described as dangling bonds). Further, remaining unbonded bonds are terminated by hydrogen (H). In other words, the ratio of the unbonded bonds terminated by hydrogen to all the dangling bonds can be evaluated to be sufficient for reducing charge traps in the gate insulating film 41 .
  • SiON contains excess interatomic hydrogen having a concentration sufficient to compensate the collapse.
  • the disposition of high-concentration interatomic hydrogen makes it possible to cause the hydrogen termination again even in the case when a dehydrogenation reaction progresses by heating and then hydrogen is released to the outside from SiON.
  • SiON film formed under the above-described forming conditions in the case when SiON of the SiON film is represented as Si x O y N z , a composition ratio x:y:z of Si:O:N is set to
  • x:y:z 0.32 ⁇ 20%:0.30 ⁇ 20%:0.38 ⁇ 20%, namely to a value within a range of
  • a hydrogen-terminated group concentration C H1 is set to a value within a range of
  • an interatomic hydrogen concentration C H2 is set to a value within a range of
  • composition ratio x:y:z of Si:O:N to an application range as described above means that it is directed that the dangling bonds are compensated by hydrogen.
  • the hydrogen-terminated group concentration C H1 When the hydrogen-terminated group concentration C H1 is smaller than 2 ⁇ 10 22 /cm 3 , it becomes difficult to sufficiently terminate the above-described dangling bonds by hydrogen. When the hydrogen-terminated group concentration C H1 is larger than 5 ⁇ 10 22 /cm 3 , the hydrogen-terminated group concentration C H1 is not actual as a SiON insulating film, and it becomes impossible to secure sufficient insulation performance as the gate insulating film. Thus, setting the hydrogen-terminated group concentration C H1 to a value within the above-described range makes it possible to sufficiently terminate the dangling bonds by hydrogen while maintaining the excellent property as the gate insulating film.
  • the interatomic hydrogen concentration C H2 When the interatomic hydrogen concentration C H2 is smaller than 2 ⁇ 10 21 /cm 3 , it becomes difficult to sufficiently compensate the collapse of terminated hydrogen bonding groups. When the interatomic hydrogen concentration C H2 is larger than 6 ⁇ 10 21 /cm 3 , it becomes impossible to secure sufficient insulation performance as the gate insulating film. Thus, setting the interatomic hydrogen concentration C H2 to a value within the above-described range makes it possible to sufficiently compensate the collapse of terminated hydrogen bonding groups without causing a problem when the gate insulating film is used.
  • the hydrogen-terminated group concentration C H1 in SiON in this embodiment is prescribed to be not less than 2 ⁇ 10 22 /cm 3 nor more than 5 ⁇ 10 22 /cm 3 , and thereby the excellent gate insulating film in which an amount of leak current is reduced and the dangling bonds are reduced is obtained.
  • the interatomic hydrogen concentration C H2 in SiON in this embodiment is prescribed to be not less than 2 ⁇ 10 21 /cm 3 nor more than 6 ⁇ 10 21 /cm 3 , and thereby the excellent gate insulating film in which the reduced dangling bonds are maintained even if the collapse of hydrogen bonding groups due to thermal change occurs is obtained.
  • composition ratio x:y:z of Si:O:N is measured by the XPS.
  • the hydrogen-terminated group concentration C H1 is measured by the infrared absorption method.
  • the interatomic hydrogen concentration C H2 is measured by the HFS and the RBS.
  • the composition ratio x:y:z of Si:O:N is set to, for example, 0.32:0.3:0.38 or so
  • the hydrogen-terminated group concentration C H1 is set to, for example, 3 ⁇ 10 22 /cm 3 or so
  • the interatomic hydrogen concentration C H2 is set to, for example, 3 ⁇ 10 21 /cm 3 or so.
  • a concentration corresponding to remaining unpaired electrons is measured by the ESR and 1.8 ⁇ 10 18 /cm 3 or so is obtained.
  • the gate insulating film 41 formed of the above SiON film is a film in which the dangling bonds are reduced in substance, the remaining dangling bonds are sufficiently terminated by hydrogen (H), and interatomic hydrogen having a concentration sufficient to compensate the collapse of hydrogen bonding groups is contained.
  • the above gate insulating film 41 is formed in a state where the dangling bonds are quite reduced and charge traps are significantly reduced.
  • a gate electrode 7 is formed through the process in FIG. 3B similarly to the first embodiment.
  • the MIS-type AlGaN/GaN-HEMT is formed.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film 41 (particularly, charge traps on an interface of the gate insulating film 41 with the gate electrode 7 and in a vicinity region of the interface, or on an interface of the gate insulating film 41 with the compound semiconductor layer 2 and in a vicinity region of the interface) are further significantly reduced and a change in electric properties is suppressed while achieving a high gate withstand voltage of the gate electrode 7 .
  • a MIS-type AlGaN/GaN-HEMT is disclosed as a compound semiconductor device, but differs from that in the second embodiment in that the structure of the gate insulating film is slightly different.
  • FIG. 12A to FIG. 12C are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 1 in the second embodiment.
  • the MIS-type AlGaN/GaN-HEMT undergoes the various processes in FIG. 1A to FIG. 2B .
  • An electrode trench 2 C for a gate electrode is formed in a compound semiconductor layer 2 .
  • a gate insulating film 51 is formed.
  • a first insulating film 51 a is formed.
  • a SiON film is deposited to have a film thickness of 5 nm or so by the PECVD method so as to cover the entire surface on a SiC substrate 1 including the top of a source electrode 4 and the top of a drain electrode 5 .
  • the first insulating film 51 a is formed.
  • the first insulating film 51 a is formed to have the same composition and property as those of the gate insulating film 41 in the second embodiment except that the film thickness is different.
  • a second insulating film 51 b is formed.
  • insulating material of the second insulating film 51 b As an insulating material of the second insulating film 51 b , a material having a band gap higher than that of SiON of the first insulating film 51 a is used. As the insulating material of the second insulating film 51 b , Al 2 O 3 , AlN, TaO, and so on are cited. Here, the case of using Al 2 O 3 is described as an example.
  • the first insulating film 51 a Al 2 O 3 is deposited to have a film thickness of 15 nm or so by the atomic layer deposition method (Atomic Layer Deposition: ALD method), for example.
  • ALD method atomic layer deposition method
  • the second insulating film 51 b is formed.
  • the deposition of Al 2 O 3 may also be performed by, for example, the CVD method or the like in place of the ALD method.
  • the gate insulating film 51 in which the first insulating film 51 a and the second insulating film 51 b are sequentially layered is formed so as to cover the top of the compound semiconductor layer 2 including an internal surface of the electrode trench 2 C.
  • the gate insulating film 51 includes the first insulating film 51 a , so that dangling bonds are quite reduced and charge traps are significantly reduced. Further, the gate insulating film 51 includes the second insulating film 51 b , so that a gate withstand voltage of the gate electrode is improved. That is, the application of the gate insulating film 51 makes it possible to achieve a significant reduction in charge trap density while achieving the high gate withstand voltage of the gate electrode.
  • a gate electrode 7 is formed through the process in FIG. 11B .
  • the MIS-type AlGaN/GaN-HEMT is formed.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film 51 (particularly, charge traps on an interface of the gate insulating film 51 with the compound semiconductor layer 2 and in a vicinity region of the interface) are further significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode 7 .
  • FIG. 13A to FIG. 13C are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 2 in the second embodiment.
  • the MIS-type AlGaN/GaN-HEMT undergoes the various processes in FIG. 1A to FIG. 2B .
  • An electrode trench 2 C for a gate electrode is formed in a compound semiconductor layer 2 .
  • a gate insulating film 61 is formed.
  • Al 2 O 3 is deposited to have a film thickness of 15 nm or so by the ALD method so as to cover the entire surface on the compound semiconductor layer 2 including the top of a source electrode 4 and the top of a drain electrode 5 .
  • a first insulating film 61 a is formed.
  • a SiC substrate 1 may also be subjected to a heat treatment.
  • the SiC substrate 1 is heated for 5 minutes or so in a range of 400° C. to 1200° C., for example.
  • a bonding state of the first insulating film 61 a is improved.
  • hydrogen termination collapse of the gate insulating film 61 is suppressed, and a state of a stable and low concentration corresponding to unpaired electrons is maintained.
  • Al 2 O 3 in which the bonding state is improved by the heat treatment is employed, and thereby a gate withstand voltage is further stabilized.
  • SiON is deposited on the first insulating film 61 a to have a film thickness of 5 nm or so by the PECVD method.
  • a second insulating film 61 b is formed.
  • the second insulating film 61 b is formed to have the same composition and property as those of the gate insulating film 41 in the second embodiment except that the film thickness is different.
  • the gate insulating film 61 in which the first insulating film 61 a and the second insulating film 61 b are sequentially layered is formed so as to cover the top of the compound semiconductor layer 2 including an internal surface of the electrode trench 2 C.
  • the gate insulating film 61 includes the second insulating film 61 b , so that dangling bonds are quite reduced and charge traps are significantly reduced. Further, the gate insulating film 61 includes the first insulating film 61 a , so that the gate withstand voltage of the gate electrode is improved. That is, the application of the gate insulating film 61 makes it possible to achieve a significant reduction in charge trap density while achieving the high gate withstand voltage of the gate electrode.
  • a gate electrode 7 is formed through the process in FIG. 9B .
  • the MIS-type AlGaN/GaN-HEMT is formed.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film 61 (particularly, charge traps on an interface of the gate insulating film 61 with the gate electrode 7 and in a vicinity region of the interface) are further significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode 7 .
  • FIG. 14A and FIG. 14B and FIG. 15A and FIG. 15B are schematic cross-sectional views depicting main processes of a MIS-type AlGaN/GaN-HEMT according to a modified example 3 in the second embodiment.
  • the MIS-type AlGaN/GaN-HEMT undergoes the various processes in FIG. 1A to FIG. 2B .
  • An electrode trench 2 C for a gate electrode is formed in a compound semiconductor layer 2 .
  • a gate insulating film 71 is formed.
  • SiON is deposited to have a film thickness of 5 nm or so by the PECVD method so as to cover the entire surface on the compound semiconductor layer 2 including the top of a source electrode 4 and the top of a drain electrode 5 .
  • a first insulating film 71 a is formed.
  • the first insulating film 71 a is formed to have the same composition and property as those of the gate insulating film 41 in the second embodiment except that the film thickness is different.
  • SiON is deposited on the second insulating film 71 b to have a film thickness of 5 nm or so by the PECVD method. Thereby, a third insulating film 71 c is formed.
  • the gate insulating film 71 in which the first insulating film 71 a , the second insulating film 71 b , and the third insulating film 71 c are sequentially layered is formed so as to cover the top of the compound semiconductor layer 2 including an internal surface of the electrode trench 2 C.
  • the third insulating film 71 c is formed to have the same composition and property as those of the gate insulating film 41 in the second embodiment except that the film thickness is different.
  • the gate insulating film 71 includes the first and third insulating films 71 a , 71 c , so that dangling bonds are quite reduced and charge traps are significantly reduced. Further, in the above case, the structure in which the second insulating film 71 b is sandwiched between the first insulating film 71 a and the third insulating film 71 c is made, so that a state where dangling bonds on the front surface and rear surface of the gate insulating film 71 are quite reduced and charge traps are significantly reduced is made. Further, the gate insulating film 71 includes the second insulating film 71 b , so that a gate withstand voltage of the gate electrode is improved. That is, the application of the gate insulating film 71 makes it possible to achieve a further significant reduction in charge trap density while achieving the high gate withstand voltage of the gate electrode.
  • a gate electrode 7 is formed through the process in FIG. 3B .
  • the MIS-type AlGaN/GaN-HEMT is formed.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film 71 (particularly, charge traps on an interface of the gate insulating film 71 with the gate electrode 7 and in a vicinity region of the interface, or on an interface of the gate insulating film 71 with the compound semiconductor layer 2 and in a vicinity region of the interface) are further significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode 7 .
  • the SiC substrate 1 is used as a substrate, but the substrate is not limited to the SiC substrate 1 .
  • a nitride semiconductor is used in a portion of the epitaxial structure having a function of a field-effect transistor, it does not matter even if another substrate made of sapphire, Si, GaAs, or the like is used.
  • the conductivity of the substrate whether it is semi-insulating or conducting is not taken into consideration.
  • each of the source electrode 4 , the drain electrode 5 , and the gate electrode 7 in the first and second embodiments, and their various modified examples is one example, and it does not matter even if another layer structure is employed regardless of a single layer or a multilayer.
  • the method of forming each of the electrodes is also one example, and it does not matter even if any one of other forming methods is employed.
  • the heat treatment is performed at the time of forming the source electrode 4 and the drain electrode 5 , but the heat treatment does not have to be performed as long as ohmic characteristics are obtained, and further, the heat treatment may also be further performed after the formation of the gate electrode 7 .
  • the cap layer 2 e is described as a single layer, but a cap layer composed of a plurality of compound semiconductor layers may also be employed.
  • the electrode trench 2 C in which the gate electrode 7 is formed is formed, but a structure without using the electrode trench 2 C may also be made.
  • a power supply device provided with one type of the AlGaN/GaN-HEMTs selected from the first and second embodiments, and their various modified examples is disclosed.
  • FIG. 16 is a connection diagram depicting a schematic structure of a power supply device according to a fourth embodiment.
  • the power supply device in this embodiment is structured to include: a high-voltage primary side circuit 81 ; a low-voltage secondary side circuit 82 ; and a transformer 83 provided between the primary side circuit 81 and the secondary side circuit 82 .
  • the primary side circuit 81 is configured to include: an AC power supply 84 ; what is called a bridge rectifying circuit 85 ; and a plurality of (four, here) switching elements 86 a , 86 b , 86 c , and 86 d . Further, the bridge rectifying circuit 85 has a switching element 86 e.
  • the secondary side circuit 82 is configured to include a plurality of (three, here) switching elements 87 a , 87 b , and 87 c.
  • each of the switching elements 86 a , 86 b , 86 c , 86 d , and 86 e in the primary side circuit 81 is one type of the AlGaN/GaN-HEMTs selected from the first and second embodiments, and their various modified examples.
  • each of the switching elements 87 a , 87 b , and 87 c in the secondary side circuit 82 is a normal MIS-FET using silicon.
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film (particularly, charge traps on an interface of the gate insulating film with the gate electrode and in a vicinity region of the interface, or on an interface of the gate insulating film with the compound semiconductor layer 2 and in a vicinity region of the interface) are further significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode to the high-voltage circuit.
  • the highly-reliable power supply device with high power is fabricated.
  • a high-frequency amplifier provided with one type of the AlGaN/GaN-HEMTs selected from the first and second embodiments, and their various modified examples is disclosed.
  • FIG. 17 is a connection diagram depicting a schematic structure of a high-frequency amplifier according to a fifth embodiment.
  • the high-frequency amplifier in this embodiment is structured to include: a digital-predistortion circuit 91 ; mixers 92 a and 92 b ; and a power amplifier 93 .
  • the digital-predistortion circuit 91 is to compensate nonlinear distortion of an input signal.
  • the mixer 92 a is to mix the input signal in which the nonlinear distortion is compensated and an AC signal.
  • the power amplifier 93 is to amplify an input signal mixed with the AC signal, and has one type of the AlGaN/GaN-HEMTs selected from the first and second embodiments, and their various modified examples.
  • the high-frequency amplifier is structured such that by switching a switch, for example, a signal on an output side is mixed with an AC signal in the mixer 92 b and the mixed signal is allowed to be transmitted to the digital-predistortion circuit 91 .
  • the highly-reliable AlGaN/GaN-HEMT in which charge traps in the gate insulating film (particularly, charge traps on an interface of the gate insulating film with the gate electrode and in a vicinity region of the interface, or on an interface of the gate insulating film with the compound semiconductor layer 2 and in a vicinity region of the interface) are further significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode to the high-frequency amplifier.
  • the highly-reliable high-frequency amplifier with a high withstand voltage is fabricated.
  • the AlGaN/GaN-HEMT is described as an example.
  • HEMTs as below can be employed other than the AlGaN/GaN-HEMT.
  • an InAlN/GaN-HEMT is disclosed as the compound semiconductor device.
  • InAlN and GaN are compound semiconductors in which their lattice constants are allowed to be close to each other according to their compositions.
  • the electron transit layer is formed of i-GaN
  • the intermediate layer is formed of i-InAlN
  • the electron supply layer is formed of n-InAlN
  • the cap layer is formed of n-GaN.
  • piezoelectric polarization hardly occurs, so that a two-dimensional electron gas mainly occurs by spontaneous polarization of InAlN.
  • the highly-reliable InAlN/GaN-HEMT in which charge traps in the gate insulating film (particularly, charge traps on an interface of the gate insulating film with the gate electrode and in a vicinity region of the interface, or on an interface of the gate insulating film with the compound semiconductor layer 2 and in a vicinity region of the interface) are further significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode.
  • an InAlGaN/GaN-HEMT is disclosed as the compound semiconductor device.
  • GaN and InAlGaN are compound semiconductors, in which a lattice constant of the latter compound semiconductor is smaller than that of the former compound semiconductor.
  • the electron transit layer is formed of i-GaN
  • the intermediate layer is formed of i-InAlGaN
  • the electron supply layer is formed of n-InAlGaN
  • the cap layer is formed of n + -GaN.
  • the highly-reliable InAlGaN/GaN-HEMT in which charge traps in the gate insulating film (particularly, charge traps on an interface of the gate insulating film with the gate electrode and in a vicinity region of the interface, or on an interface of the gate insulating film with the compound semiconductor layer 2 and in a vicinity region of the interface) are further significantly reduced and a change in electric properties is suppressed while achieving the high gate withstand voltage of the gate electrode.
  • the highly-reliable compound semiconductor device in which charge traps in the gate insulating film are significantly reduced and a change in electric properties is suppressed is fabricated.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
US13/278,392 2010-12-10 2011-10-21 Compound semiconductor device and method of manufacturing the same Abandoned US20120146728A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010276294A JP6035007B2 (ja) 2010-12-10 2010-12-10 Ｍｉｓ型の窒化物半導体ｈｅｍｔ及びその製造方法
JP2010-276294 2010-12-10

Publications (1)

Publication Number Publication Date
US20120146728A1 true US20120146728A1 (en) 2012-06-14

Family

ID=46198755

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/278,392 Abandoned US20120146728A1 (en) 2010-12-10 2011-10-21 Compound semiconductor device and method of manufacturing the same

Country Status (4)

Country Link
US (1) US20120146728A1 (zh)
JP (1) JP6035007B2 (zh)
CN (1) CN102544088B (zh)
TW (1) TWI450342B (zh)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130258719A1 (en) * 2012-03-29 2013-10-03 Fujitsu Limited Compound semiconductor device and manufacturing method of the same
US20140016360A1 (en) * 2012-07-10 2014-01-16 Fujitsu Limted Compound semiconductor device and method of manufacturing the same
US20140091424A1 (en) * 2012-09-28 2014-04-03 Fujitsu Limited Compound semiconductor device and manufacturing method thereof
US20140291775A1 (en) * 2013-03-28 2014-10-02 Toyoda Gosei Co., Ltd. Semiconductor device
US20150034957A1 (en) * 2013-08-01 2015-02-05 Taiwan Semiconductor Manufacturing Co., Ltd. Normally-off enhancement-mode misfet
US9153601B2 (en) 2013-05-08 2015-10-06 Au Optronics Corporation Semiconductor device
US9514930B2 (en) 2013-01-17 2016-12-06 Fujitsu Limited Method for manufacturing semiconductor HEMT device with stoichiometric silicon nitride layer
US9818855B2 (en) 2015-09-14 2017-11-14 Kabushiki Kaisha Toshiba Semiconductor device
US10043883B2 (en) 2014-09-22 2018-08-07 Kabushiki Kaisha Toshiba Semiconductor device, and method of manufacturing semiconductor device
US20180277650A1 (en) * 2017-03-21 2018-09-27 Kabushiki Kaisha Toshiba Semiconductor device
US20190355580A1 (en) * 2018-05-18 2019-11-21 Kabushiki Kaisha Toshiba Semiconductor element and method for manufacturing the same
US11489050B2 (en) * 2020-01-16 2022-11-01 Shinichiro Takatani Vertical nitride semiconductor transistor device

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5680987B2 (ja) * 2011-02-18 2015-03-04 株式会社アドバンテスト 半導体装置、試験装置、および製造方法
KR20140026257A (ko) * 2012-08-23 2014-03-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치
JP2014138111A (ja) * 2013-01-17 2014-07-28 Fujitsu Ltd 半導体装置及びその製造方法、電源装置、高周波増幅器
US9178016B2 (en) * 2013-03-01 2015-11-03 Infineon Technologies Austria Ag Charge protection for III-nitride devices
JPWO2014185034A1 (ja) * 2013-05-13 2017-02-23 パナソニックＩｐマネジメント株式会社 半導体装置
US9425301B2 (en) * 2014-04-30 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Sidewall passivation for HEMT devices
JP6591169B2 (ja) 2015-02-04 2019-10-16 株式会社東芝 半導体装置及びその製造方法
JP6591168B2 (ja) * 2015-02-04 2019-10-16 株式会社東芝 半導体装置及びその製造方法
CN106469750A (zh) * 2015-08-19 2017-03-01 昆山工研院新型平板显示技术中心有限公司 薄膜晶体管及其制造方法
JP6536318B2 (ja) * 2015-09-24 2019-07-03 三菱電機株式会社 半導体装置及びその製造方法
JP6649586B2 (ja) * 2016-07-12 2020-02-19 富士通株式会社 化合物半導体装置及びその製造方法
JP6771669B2 (ja) * 2017-05-31 2020-10-21 三菱電機株式会社 半導体装置の製造方法
JP6930010B2 (ja) * 2018-03-06 2021-09-01 株式会社東芝 半導体装置、電源回路、及び、コンピュータ
JP6767411B2 (ja) 2018-03-06 2020-10-14 株式会社東芝 半導体装置、電源回路、及び、コンピュータ
JP7450446B2 (ja) 2020-04-13 2024-03-15 株式会社アドバンテスト 半導体装置、半導体装置の製造方法、および試験装置

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010029069A1 (en) * 1998-08-21 2001-10-11 Semiconductor Energy Laboratory Semiconductor device provided with semiconductor circuit made of semiconductor element and method of fabricating the same
US20030020092A1 (en) * 2001-07-24 2003-01-30 Primit Parikh Insulating gate AlGaN/GaN HEMT
US20070048957A1 (en) * 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device
US20070212804A1 (en) * 2006-03-13 2007-09-13 Kabushiki Kaisha Toshiba Solid-state imaging device and method for manufacturing thereof
US20080026514A1 (en) * 2003-11-28 2008-01-31 Atsushi Nakagawa Method for producing nitride semiconductor device
US20090059110A1 (en) * 2007-09-04 2009-03-05 Hitachi Displays, Ltd. Liquid crystal display device
US20090167411A1 (en) * 2007-12-26 2009-07-02 Sanken Electric Co., Ltd. Normally-off electronic switching device
US20100117126A1 (en) * 2008-11-07 2010-05-13 Sony Corporation Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic apparatus
US20110278590A1 (en) * 2010-05-12 2011-11-17 Van Mieczkowski Semiconductor Devices Having Gates Including Oxidized Nickel and Related Methods of Fabricating the Same
US20120217586A1 (en) * 2011-02-25 2012-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits with resistors and methods of forming the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076336A (ja) * 2000-09-01 2002-03-15 Mitsubishi Electric Corp 半導体装置およびｓｏｉ基板
JP2004134687A (ja) * 2002-10-15 2004-04-30 Toshiba Corp 半導体装置及びその製造方法
JP4455381B2 (ja) * 2005-03-28 2010-04-21 住友電工デバイス・イノベーション株式会社 半導体装置およびその製造方法、容量素子およびその製造方法、並びにｍｉｓ型半導体装置およびその製造方法。
JP4823671B2 (ja) * 2005-12-13 2011-11-24 日本電信電話株式会社 窒化物半導体を用いたヘテロ構造電界効果トランジスタ
JP5207598B2 (ja) * 2006-05-24 2013-06-12 パナソニック株式会社 窒化物半導体材料、半導体素子およびその製造方法
JP5105842B2 (ja) * 2006-12-05 2012-12-26 キヤノン株式会社 酸化物半導体を用いた表示装置及びその製造方法
JP5186776B2 (ja) * 2007-02-22 2013-04-24 富士通株式会社 半導体装置及びその製造方法
JP4719210B2 (ja) * 2007-12-28 2011-07-06 富士通株式会社 半導体装置及びその製造方法
JP2009176930A (ja) * 2008-01-24 2009-08-06 Toshiba Corp 半導体装置およびその製造方法
JP5345328B2 (ja) * 2008-02-22 2013-11-20 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP5704790B2 (ja) * 2008-05-07 2015-04-22 キヤノン株式会社 薄膜トランジスタ、および、表示装置
JP5212414B2 (ja) * 2010-04-05 2013-06-19 富士通株式会社 半導体装置及びその製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010029069A1 (en) * 1998-08-21 2001-10-11 Semiconductor Energy Laboratory Semiconductor device provided with semiconductor circuit made of semiconductor element and method of fabricating the same
US20030020092A1 (en) * 2001-07-24 2003-01-30 Primit Parikh Insulating gate AlGaN/GaN HEMT
US20080026514A1 (en) * 2003-11-28 2008-01-31 Atsushi Nakagawa Method for producing nitride semiconductor device
US20070048957A1 (en) * 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device
US20070212804A1 (en) * 2006-03-13 2007-09-13 Kabushiki Kaisha Toshiba Solid-state imaging device and method for manufacturing thereof
US20090059110A1 (en) * 2007-09-04 2009-03-05 Hitachi Displays, Ltd. Liquid crystal display device
US20090167411A1 (en) * 2007-12-26 2009-07-02 Sanken Electric Co., Ltd. Normally-off electronic switching device
US20100117126A1 (en) * 2008-11-07 2010-05-13 Sony Corporation Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic apparatus
US20110278590A1 (en) * 2010-05-12 2011-11-17 Van Mieczkowski Semiconductor Devices Having Gates Including Oxidized Nickel and Related Methods of Fabricating the Same
US20120217586A1 (en) * 2011-02-25 2012-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits with resistors and methods of forming the same

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9224848B2 (en) * 2012-03-29 2015-12-29 Transphorm Japan, Inc. Compound semiconductor device and manufacturing method of the same
US20130258719A1 (en) * 2012-03-29 2013-10-03 Fujitsu Limited Compound semiconductor device and manufacturing method of the same
US8933489B2 (en) * 2012-03-29 2015-01-13 Transphorm Japan, Inc. Compound semiconductor device and manufacturing method of the same
US20150078038A1 (en) * 2012-03-29 2015-03-19 Transphorm Japan, Inc. Compound semiconductor device and manufacturing method of the same
US20140016360A1 (en) * 2012-07-10 2014-01-16 Fujitsu Limted Compound semiconductor device and method of manufacturing the same
CN103545362A (zh) * 2012-07-10 2014-01-29 富士通株式会社 化合物半导体器件及其制造方法
US9368359B2 (en) 2012-07-10 2016-06-14 Fujitsu Limited Method of manufacturing compound semiconductor device
US9184272B2 (en) * 2012-07-10 2015-11-10 Fujitsu Limited Compound semiconductor device having overhang-shaped gate
US20140091424A1 (en) * 2012-09-28 2014-04-03 Fujitsu Limited Compound semiconductor device and manufacturing method thereof
CN103715243A (zh) * 2012-09-28 2014-04-09 富士通株式会社 化合物半导体器件及其制造方法
US9514930B2 (en) 2013-01-17 2016-12-06 Fujitsu Limited Method for manufacturing semiconductor HEMT device with stoichiometric silicon nitride layer
US20140291775A1 (en) * 2013-03-28 2014-10-02 Toyoda Gosei Co., Ltd. Semiconductor device
US9508822B2 (en) * 2013-03-28 2016-11-29 Toyoda Gosei Co., Ltd. Semiconductor device
US10074728B2 (en) 2013-03-28 2018-09-11 Toyoda Gosei Co., Ltd. Semiconductor device
US9153601B2 (en) 2013-05-08 2015-10-06 Au Optronics Corporation Semiconductor device
US20150034957A1 (en) * 2013-08-01 2015-02-05 Taiwan Semiconductor Manufacturing Co., Ltd. Normally-off enhancement-mode misfet
US9564330B2 (en) * 2013-08-01 2017-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. Normally-off enhancement-mode MISFET
US10043883B2 (en) 2014-09-22 2018-08-07 Kabushiki Kaisha Toshiba Semiconductor device, and method of manufacturing semiconductor device
US9818855B2 (en) 2015-09-14 2017-11-14 Kabushiki Kaisha Toshiba Semiconductor device
US20180277650A1 (en) * 2017-03-21 2018-09-27 Kabushiki Kaisha Toshiba Semiconductor device
US20190355580A1 (en) * 2018-05-18 2019-11-21 Kabushiki Kaisha Toshiba Semiconductor element and method for manufacturing the same
US10923349B2 (en) * 2018-05-18 2021-02-16 Kabushiki Kaisha Toshiba Semiconductor element and method for manufacturing the same
US11489050B2 (en) * 2020-01-16 2022-11-01 Shinichiro Takatani Vertical nitride semiconductor transistor device

Also Published As

Publication number Publication date
CN102544088A (zh) 2012-07-04
JP6035007B2 (ja) 2016-11-30
JP2012124436A (ja) 2012-06-28
TWI450342B (zh) 2014-08-21
CN102544088B (zh) 2016-02-17
TW201234495A (en) 2012-08-16

Similar Documents

Publication Publication Date Title
US20120146728A1 (en) Compound semiconductor device and method of manufacturing the same
US9685338B2 (en) Compound semiconductor device and method of manufacturing the same
US9035353B2 (en) Compound semiconductor device comprising electrode above compound semiconductor layer and method of manufacturing the same
EP2575178B1 (en) Compound semiconductor device and manufacturing method therefor
TWI517382B (zh) 化合物半導體裝置、其製造方法、電源電路及高頻放大器
KR101357477B1 (ko) 화합물 반도체 장치 및 그 제조 방법
US9224848B2 (en) Compound semiconductor device and manufacturing method of the same
US8912571B2 (en) Compound semiconductor device including first film on compound semiconductor layer and second film on first film and method of manufacturing the same
US8722476B2 (en) Compound semiconductor device and manufacture process thereof
TWI523221B (zh) 化合物半導體裝置及其製造方法
US20140092638A1 (en) Compound semiconductor device and method of manufacturing the same
US9496380B2 (en) Compound semiconductor device comprising compound semiconductor layered structure having buffer layer and method of manufacturing the same
TWI546957B (zh) 化合物半導體裝置及其製造方法
US20120320642A1 (en) Compound semiconductor device and method of manufacturing the same
US20150333135A1 (en) Compound semiconductor device and method of manufacturing the same
US20140092636A1 (en) Compound semiconductor device and method of manufacturing the same
US20140084345A1 (en) Compound semiconductor device and method of manufacturing the same
JP5942371B2 (ja) 化合物半導体装置及びその製造方法
US9691890B2 (en) Compound semiconductor device and manufacturing method thereof
JP6905197B2 (ja) 化合物半導体装置及びその製造方法
US20240006493A1 (en) Semiconductor device, method for manufacturing semiconductor device, and electronic device
US20240006526A1 (en) Semiconductor device, method for manufacturing semiconductor device, and electronic device
JP6561610B2 (ja) 化合物半導体装置及びその製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MAKIYAMA, KOZO;KIKKAWA, TOSHIHIDE;SIGNING DATES FROM 20111003 TO 20111004;REEL/FRAME:027262/0483

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION