US20120127148A1 - Display substrate, display panel and display device - Google Patents

Display substrate, display panel and display device Download PDF

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Publication number
US20120127148A1
US20120127148A1 US13/283,409 US201113283409A US2012127148A1 US 20120127148 A1 US20120127148 A1 US 20120127148A1 US 201113283409 A US201113283409 A US 201113283409A US 2012127148 A1 US2012127148 A1 US 2012127148A1
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United States
Prior art keywords
pixel region
pixel
slit pattern
lower electrode
data
Prior art date
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Abandoned
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US13/283,409
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English (en)
Inventor
Seong-Jun Lee
Jin-Oh PARK
Mu-kyung Jeon
Yong-kyu Jang
Dong-Hoon Lee
Chi-Woo Kim
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Samsung Display Co Ltd
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Individual
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Publication date
Priority claimed from KR1020100117361A external-priority patent/KR20120055909A/ko
Priority claimed from KR1020110076840A external-priority patent/KR20130015048A/ko
Application filed by Individual filed Critical Individual
Assigned to SAMSUNG MOBILE DISPLAY CO., LTD. reassignment SAMSUNG MOBILE DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JANG, YONG-KYU, Jeon, Mu-Kyung, KIM, CHI-WOO, LEE, DONG-HOON, LEE, SEONG-JUN, PARK, JIN-OH
Publication of US20120127148A1 publication Critical patent/US20120127148A1/en
Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: SAMSUNG MOBILE DISPLAY CO., LTD.
Priority to US16/003,055 priority Critical patent/US11333937B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • Example embodiments of the present invention relate to display substrates, display panels, and display devices. More particularly, example embodiments of the present invention relate to liquid crystal display substrates, liquid crystal display panels, and liquid crystal display devices.
  • a liquid crystal display (LCD) device typically includes a liquid crystal layer disposed between two insulating substrates on which electric field generating electrodes are formed, respectively.
  • the LCD device may display an image by adjusting the transmittance of light passing through the liquid crystal layer, through realignment of liquid crystal molecules in the liquid crystal layer, in response to a voltage applied to the electric field generating electrodes.
  • An LCD device having a general structure may be a display device of a twisted nematic (“TN”) mode, in which the electric field forming electrodes are formed on the two insulating substrates, respectively.
  • the LCD device of TN mode has a problem in that a viewing angle is narrow.
  • the LCD device of the PLS mode includes a pair of electric field generating electrodes, for example, a pixel electrode and a common electrode insulated from each other and disposed on a substrate (example for an array substrate) on which thin-film transistors (TFTs) are formed.
  • TFTs thin-film transistors
  • Liquid crystal molecules arranged along a fringe field between the pixel electrode and the common electrode control the light transmittance of the liquid crystal layer so that the LCD device of the PLS mode displays an image.
  • Example embodiments provide a display substrate capable of improving a viewing angle and visibility with a high light-transmittance.
  • Example embodiments provide a display panel capable of improving a viewing angle and visibility with a high light-transmittance.
  • Example embodiments provide a display device capable of improving a viewing angle and visibility with a high light-transmittance.
  • a display substrate including an insulating substrate, a first gate line, a first lower electrode, a second lower electrode, a first upper electrode, and a second upper electrode.
  • the insulating substrate may include a first pixel region and a second pixel region disposed in a first direction from the first pixel region.
  • the first gate line may extend in a second direction crossing the first direction on the insulating substrate.
  • the first lower electrode may be disposed in the first pixel region.
  • the second lower electrode may be disposed in the second pixel region.
  • the first upper electrode may overlap the first lower electrode in the first pixel region, and may include a first slit pattern extending in a third direction different from the first and the second directions.
  • the second upper electrode may overlap the second lower electrode in the second pixel region, and may include a second slit pattern extending in a fourth direction different from the first to the third directions.
  • the display subtrate may further include an alignment layer on the insulating substrate on which the first and the second upper electrodes may be located.
  • the alignment direction of the alignment layer in the first pixel region may be same as that of the alignment layer in the second pixel region.
  • the alignment direction of the alignment layer may be the first direction or the second direction.
  • the second direction may be perpendicular to the first direction.
  • the third direction and the fourth direction may be symmetric to each other with respect to the second direction.
  • the insulating substrate may further include a third pixel region disposed in the second direction from the first pixel region and a fourth pixel region disposed in the second direction from the second pixel region.
  • the display substrate may further include a third lower electrode, a fourth lower electrode, a third upper electrode and a fourth upper electrode.
  • the third lower electrode may be disposed in the third pixel region.
  • the fourth lower electrode may be disposed in the fourth pixel region.
  • the third upper electrode may overlap the third lower electrode in the third pixel region, and may include a third slit pattern extending in the third direction.
  • the fourth upper electrode may overlap the fourth lower electrode in the fourth pixel region, and may include a fourth slit pattern extending in the fourth direction.
  • the display substrate may further include a second gate line, a first date line, a first switching element and a second switching element.
  • the second gate line may be disposed in parallel with the first gate line.
  • the first data line may cross the first and the second gate lines.
  • the first switching element may be disposed in the first pixel region, and may be electrically coupled to the first gate line and the first data line.
  • the second switching element may be disposed in the second pixel region, and may be electrically coupled to the second gate line and the first data line.
  • the first lower electrode or the first upper electrode may be electrically coupled to the first switching element
  • the second lower electrode or the second upper electrode may be electrically coupled to the second switching element.
  • the first gate line may be disposed between the first and the second pixel regions.
  • the second pixel region may be disposed between the first and the second gate lines.
  • the first and the second pixel regions may be disposed between the first and the second gate lines.
  • the display substrate may further include a second gate line, a first data line, a second data line, a first switching element and a second switching element.
  • the second gate line may be disposed in parallel with the first gate line.
  • the first data line may cross the first and the second gate lines.
  • the second data line may be disposed in parallel with the first data line, and may cross the first and the second gate lines.
  • the first switching element may be disposed in the first pixel region, and may be electrically coupled to the first gate line and the second data line.
  • the second switching element may be disposed in the second pixel region, and may be electrically coupled to the second gate line and the first data line.
  • the first lower electrode or the first upper electrode may be electrically coupled to the first switching element
  • the second lower electrode or the second upper electrode may be electrically coupled to the second switching element.
  • the first and the second pixel regions may be between the first and the second gate lines.
  • the first and the second upper electrodes may have an integral structure where the first and the second upper electrodes are coupled to each other, and the first and the second slit patterns may be coupled to each other.
  • the insulating substrate may further include a third pixel region disposed in the first direction from the second pixel region.
  • the display substrate may further include a third gate line, a third lower electrode, a third upper electrode and a third switching element.
  • the third gate line may extend in the second direction, and may be between the third pixel region and the second gate line.
  • the third lower electrode may be disposed in the third pixel region.
  • the third upper electrode may overlap the third lower electrode in the third pixel region, and may include a third slit pattern extending in the third direction.
  • the third switching element may be disposed in the third pixel region, and may be electrically coupled to the third gate line, the third switching element being adjacent to the third gate line.
  • the display substrate may further include first and second data lines crossing the first gate line, the first and the second data lines may be disposed in parallel with each other.
  • the first and the second pixel regions may be between the first and the second data lines.
  • Sides of the first and the second upper electrodes adjacent to the first data line may be disposed in parallel with the first data line, and sides of the first and the second upper electrodes adjacent to the second data line may be disposed in parallel with the second data line.
  • each of the first and the second data lines may include a first extension portion in parallel with the first slit pattern and a second extension portion in parallel with the second slit pattern.
  • Each of the first and the second data lines may have a straight line shape extending along the first direction.
  • the first slit pattern may include a first curved portion having an inclined angle smaller than an angle between the second direction and the third direction, and the first curved portion may be in at least one of both edge portions of the first slit pattern.
  • the second slit pattern may include a second curved portion having an inclined angle smaller than an angle between the second direction and the fourth direction, and the second curved portion may be in at least one of both edge portions of the second slit pattern.
  • a display substrate including an insulating substrate, a first gate line, a first lower electrode, a second lower electrode, a first upper electrode and a second upper electrode.
  • the insulating substrate may include a first pixel region and a second pixel region disposed in a first direction from the first pixel region.
  • the first gate line may be disposed between the first and the second pixel regions, the first gate line may extend in a second direction crossing the first direction on the insulating substrate.
  • the first lower electrode may be disposed in the first pixel region.
  • the second lower electrode may be disposed in the second pixel region.
  • the first upper electrode may overlap the first lower electrode in the first pixel region, and may include a first slit pattern sequentially extending in a third direction and in a fourth direction, the third and the fourth directions being different from each other, and each of the third and the fourth directions being different from the first and the second directions.
  • the second upper electrode may overlap the second lower electrode in the second pixel region, and may include a second slit pattern sequentially extending in the fourth direction and the third direction.
  • the display substrate may further include an alignment layer formed on the insulating substrate on which the first and the second upper electrodes may be formed.
  • the alignment direction of the alignment layer in the first pixel region may be same as that of the alignment layer in the second pixel region.
  • the alignment direction of the alignment layer may be the first direction or the second direction.
  • the second direction may be perpendicular to the first direction, and the third direction and the fourth direction may be symmetric to each other with respect to the second direction.
  • the display substrate may further include a second gate line, a first data line, a second data line, a first switching element and a second switching element.
  • the second gate line may be disposed in parallel with the first gate line.
  • the first data line may cross the first and the second gate lines.
  • the second data line may cross the first and the second gate lines, and may be disposed in parallel with the first data line.
  • the first switching element may be disposed in the first pixel region, and may be electrically coupled to the first gate line and the second data line.
  • the second switching element may be disposed in the second pixel region, and may be electrically coupled to the second gate line and the first data line. Then, the first lower electrode or the first upper electrode may be electrically coupled to the first switching element, and the second lower electrode or the second upper electrode may be electrically coupled to the second switching element.
  • the first and the second pixel regions may be between the first and the second data lines.
  • the first switching element may be located adjacently to the second data line, and the second switching element may be located adjacently to the first data line.
  • each of the first and the second data lines may include a first extension portion in parallel with the first slit pattern; and a second extension portion in parallel with the second slit pattern.
  • a display panel including a display substrate, an opposing substrate and liquid crystal layer.
  • the display substrate may include an insulating substrate, a first gate line, a first lower electrode, a first upper electrode, a second lower electrode and a second upper electrode.
  • the insulating substrate may include a first pixel region and a second pixel region disposed in a first direction from the first pixel region.
  • the first gate line may extend in a second direction crossing the first direction.
  • the first lower electrode and the first upper electrode may be disposed in the first pixel region, the first upper electrode may overlap the first lower electrode, and may include a first slit pattern extending in a third direction different from the first and the second directions.
  • the second lower electrode and the second upper electrode may be disposed in the second pixel region, the second upper electrode may overlap the second lower electrode, and may include a second slit pattern extending in a fourth direction different from the first to the third direction.
  • the opposing substrate may face the display substrate, and may include color filters overlapping the first and the second pixel regions.
  • the liquid crystal layer may be disposed between the display substrate and the opposing substrate.
  • the opposing substrate may further include a second alignment layer formed on the opposing substrate on which the color filters are formed.
  • the second alignment layer may have a single alignment direction in regions of the opposing substrate facing the first and the second pixel regions. Then, the alignment direction of the second alignments layer may be same as that of the first alignment layer.
  • the display panel may further include a first polarizing plat and a second polarizing plate.
  • the first polarizing plate may be disposed on a lower surface of the display substrate, and may have a polarizing axis that is same as the alignment direction of the first alignment layer.
  • the second polarizing plate may be disposed on an upper surface of the opposing substrate, and may have a polarizing axis perpendicular to the polarizing axis of the first polarizing plate.
  • the opposing substrate may further include a light-blocking pattern overlapping the first and the second switching elements.
  • a width of the light-blocking pattern between the second and the third pixel regions may be smaller than a distance from a distant end of the second switching element to a distant end of the third switching element.
  • a display panel including a display substrate, an opposing substrate and liquid crystal layer.
  • the display substrate may include an insulating substrate, a first gate line, a first lower electrode, a first upper electrode, a second lower electrode and a second upper electrode.
  • the insulating substrate may include a first pixel region and a second pixel region disposed in a first direction from the first pixel region.
  • the first gate line may be disposed between the first and the second pixel regions, and the first gate line may extend in a second direction crossing the first direction.
  • the first lower electrode and the first upper electrode may be disposed in the first pixel region.
  • the first upper electrode may overlap the first lower electrode, and may include a first slit pattern sequentially extending in a third direction and in a fourth direction.
  • the third and the fourth directions may be different from each other, and each of the third and the fourth directions may be different from the first and the second directions.
  • the second lower electrode and the second upper electrode may be disposed in the second pixel region.
  • the second upper electrode may overlap the second lower electrode, and may include a second slit pattern sequentially extending in the fourth direction and in the third direction.
  • the opposing substrate may face the display substrate, and may include color filters overlapping the first and the second pixel regions.
  • the liquid crystal layer may be disposed between the display substrate and the opposing substrate.
  • the display panel may further include a first polarizing plat and a second polarizing plate.
  • the first polarizing plate may be disposed on a lower surface of the display substrate, and may have a polarizing axis that is same as the alignment direction of the first alignment layer.
  • the second polarizing plate may be disposed on an upper surface of the opposing substrate, and may have a polarizing axis that is perpendicular to the polarizing axis of the first polarizing plate.
  • a display device including a display panel, a gamma voltage generating unit, a controlling unit and a data driving unit.
  • the display panel may include a first pixel, a second pixel and a first gate line.
  • the first pixel may include a first lower electrode and a first upper electrode overlapping the first lower electrode, the first upper electrode may have a first slit pattern.
  • the second pixel may be disposed in a first direction from the first pixel, the second pixel may include a second lower electrode and a second upper electrode overlapping the second lower electrode, the second upper electrode may have a second slit pattern extending in a direction different from a longitudinal direction of the first slit pattern.
  • the first gate line may extend in a second direction different from the first direction.
  • the gamma voltage generating unit may be configured to generate a first gamma reference voltage group and a second gamma reference voltage group, the first and the second gamma reference voltage groups having different voltage levels.
  • the controlling unit may be configured to output first and the second pixel data corresponding to the first and the second pixels.
  • the data driving unit may be configured to convert the first pixel data to a first pixel voltage based on the first gamma reference voltage group, to convert the second pixel data to a second pixel voltage based on the second gamma reference voltage group, and to output the first pixel voltage and the second pixel voltage to the first pixel and the second pixel, respectively.
  • the controlling unit may be configured to receive image data from an external image source, to generate the first and the second pixel data based on the received image data, and to output the first and the second pixel data and a gamma selecting signal for controlling a selection of the first gamma reference voltage group or the second gamma reference voltage group.
  • the data driving unit may include a gamma voltage selector that selects one of the first and the second gamma reference voltage groups in response to the gamma selecting signal.
  • the controlling unit may be configured to receive image data from an external image source, to generate the first and the second pixel data based on the received image data, and to output the first and the second pixel data and a gamma selecting signal for controlling a selection of the first gamma reference voltage group or the second gamma reference voltage group.
  • the gamma voltage generating unit may be configured to selectively output one of the first and the second gamma reference voltage groups in response to the gamma selecting signal.
  • the gamma voltage generating unit may include a first gamma unit, a second gamma unit and a gamma voltage selector.
  • the first gamma unit may include a first resistor-string, and may be configured to generate the first gamma reference voltage group using a power supply voltage.
  • the second gamma unit may include a second resistor-string, and may be configured to generate the second gamma reference voltage group using the power supply voltage, the second resistor-string having resistances different from those of the first resistor-string.
  • the gamma voltage selector may be configured to selectively output one of the first and the second gamma reference voltage groups in response to the gamma selecting signal.
  • gamma values of the first and the second gamma reference voltage groups may be different from each other.
  • an extending direction of the first slit pattern may be symmetrical to that of the second slit pattern with respect to the second direction.
  • the display panel may further include a first data line extending in the first direction to cross the first gate line, and coupled to at least one of the first and the second pixels.
  • the first and the second pixels may be sequentially operated, and a selection period of the first and the second gamma reference voltages groups may be same as an operating period of the first and the second pixels.
  • FIG. 1 is a block diagram illustrating a display device in accordance with example embodiments
  • FIG. 2 is block diagram illustrating a data driving unit included in a display device of FIG. 1 ;
  • FIG. 3A is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 3B is a cross-sectional view of an example embodiment of a display panel taken along a line I-I′ of FIG. 3A ;
  • FIG. 4 is a block diagram illustrating a display device in accordance with example embodiments
  • FIG. 5 is a block diagram illustrating a gamma voltage generating unit included in a display device of FIG. 4 ;
  • FIG. 6 is a block diagram illustrating a data driving unit included in a display device of FIG. 4 ;
  • FIG. 7 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 8 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 9 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 10 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 11A is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 11B is a cross-sectional view of an example embodiment of a display panel taken along a line II-II′ of FIG. 11A ;
  • FIG. 12 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 13 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 14 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 15 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 16A is a block diagram illustrating a display panel in accordance with example embodiments.
  • FIG. 16B is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 17 is a plan view illustrating a light-blocking pattern of an opposing substrate included in a display panel of FIG. 16B ;
  • FIG. 18 is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 19A is a block diagram illustrating a display panel in accordance with example embodiments.
  • FIG. 19B is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 20 is a plan view illustrating a display panel in accordance with example embodiments.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers, patterns and/or sections, these elements, components, regions, layers, patterns and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, pattern, or section from another element, component, region, layer, pattern, or section. Thus, a first element, component, region, layer, pattern, or section discussed below could be termed a second element, component, region, layer, pattern, or section without departing from the teachings of example embodiments.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • Example embodiments are described herein with reference to cross sectional illustrations that are schematic illustrations of illustratively idealized example embodiments (and intermediate structures) of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include variations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
  • a domain is formed along a direction of an electric field formed between the two electrodes.
  • an LCD device having a single domain structure has high light transmittance, a color shift may occur according to a viewing direction, and thus a viewing angle may be reduced.
  • an LCD device having a multi-domain structure has been developed, in which at least two domains are formed in a pixel.
  • light transmittance may be reduced due to a texture generated in a boundary between the domains.
  • FIG. 1 is a block diagram illustrating a display device 10 in accordance with example embodiments.
  • FIG. 2 is a block diagram illustrating a data driving unit 14 included in the display device 10 of FIG. 1 .
  • the display device 10 includes a display panel 100 , a gamma voltage generating unit (or a gamma voltage generator) 12 , a data driving unit (or a data driver) 14 , a controlling unit (or a controller) 16 , and a gate driving unit (or a gate driver) 18 .
  • the gamma voltage generating unit 12 , the data driving unit 14 , the controlling unit 16 , and the gate driving unit 18 may drive the display panel 100 to display an image based on an image signal provided from an image source, such as an external graphics device.
  • the display device 10 may further include a backlight assembly that emits light to the display panel 100 .
  • the backlight assembly may be located behind the display panel 100 .
  • a display direction of an image may be defined as a light emitting direction from the backlight assembly to the display panel 100 .
  • the display panel 100 includes a display substrate (or a lower substrate), an opposing substrate (or an upper substrate) and a liquid crystal layer.
  • the opposing substrate may face the display substrate.
  • the liquid crystal layer is interposed between the display substrate and the opposing substrate.
  • the display panel 100 may include a plurality of pixels PX 1 , PX 2 , PX 3 , and PX 4 , and a plurality of signal lines GL 1 , GL 2 , DL 1 , and DL 2 coupled to the pixels PX 1 , PX 2 , PX 3 , and PX 4 .
  • the display panel 100 may include a first pixel PX 1 , a second pixel PX 2 , a third pixel PX 3 and a fourth pixel PX 4 that are arranged in a matrix form.
  • the second pixel PX 2 may be located in a first direction D 1 from the first pixel PX 1 .
  • the first direction D 1 may be a vertical direction (or a column direction).
  • PX 4 may be located in a second direction D 2 from the first and second pixels PX 1 and PX 2 , respectively.
  • the second direction D 2 may cross the first direction D 1 .
  • the second direction D 2 may be a horizontal direction (or a row direction).
  • the signal lines GL 1 , GL 2 , DL 1 , and DL 2 may include gate lines GL 1 and GL 2 , and data lines DL 1 and DL 2 crossing the gate lines GL 1 and GL 2 .
  • the signal lines GL and DL may include first and second gate lines GL 1 and GL 2 and first and second data lines DL 1 and DL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2 , and may be in parallel with each other.
  • the first and second data lines DL 1 and DL may extend in the first direction D 1 , and may be in parallel with each other.
  • the signal lines GL 1 , GL 2 , DL 1 , and DL 2 may be coupled to the pixels PX 1 , PX 2 , PX 3 , and PX 4 .
  • each of the pixels PX 1 , PX 2 , PX 3 , and PX 4 may be coupled to a corresponding one of the gate lines GL 1 and GL 2 and a corresponding one of the data lines DL 1 and DL 2 .
  • each of the pixels PX 1 , PX 2 , PX 3 , and PX 4 may include a pair of electric field generating electrodes and the liquid crystal layer.
  • the pair of the electric field generating electrodes may include a lower electrode and an upper electrode overlapping the lower electrode.
  • the upper electrode may include a slit pattern for forming a domain.
  • the domain may be formed by an electric field generated by the slit pattern of the upper electrode in each of the pixels PX 1 , PX 2 , PX 3 , and PX 4 .
  • the first and second pixels PX 1 and PX 2 may have different domains from each other.
  • the first and second pixels PX 1 and PX 2 may have a symmetric structure to each other with respect to one of the gate lines GL 1 and GL 2 , or with respect to the second direction D 2 as an extension direction of the gate lines GL 1 and GL 2 .
  • the third and fourth pixels PX 3 and PX 4 may have different domains from each other.
  • the third and fourth pixels PX 3 and PX 4 may have a symmetric structure to each other with respect to one of the gate lines GL 1 and GL 2 , or with respect to the second direction D 2 as the extension direction of the gate lines GL 1 and GL 2 .
  • the domains of the third and fourth pixels PX 3 and PX 4 may be substantially the same as those of the first and second pixels PX 1 and PX 2 .
  • adjacent pixels PX 1 and PX 3 arranged along the second direction D 2 as the extension direction of the gate lines GL 1 and GL 2 may have the same domain
  • adjacent pixels PX 1 and PX 2 arranged along the first direction D 1 as the extension direction of the data lines DL 1 and DL 2 may have different domains.
  • the gamma voltage generating unit 12 may generate a plurality of gamma reference voltage groups VREF 1 and VREF 2 , each including gamma voltages provided to the pixels PX 1 , PX 2 , PX 3 , and PX 4 of the display panel 100 .
  • the gamma voltage generating unit 12 may generate a first gamma reference voltage group VREF 1 and a second gamma reference voltage group VREF 2 .
  • the first and second gamma reference voltage groups VREF 1 and VREF 2 may have different voltage levels from each other.
  • the first gamma reference voltage group VREF 1 may be a group of gamma voltages according to a first gamma curve having a first gamma value.
  • the second gamma reference voltage group VREF 2 may be a group of gamma voltages according to a second gamma curve having a second gamma value different from the first gamma value.
  • the first and second gamma values may be set to compensate for a deviation according to the domains of the first and second pixels PX 1 and PX 2 .
  • the first gamma reference voltage group VREF 1 may have voltage levels for compensating the deviation of the first pixel PX 1
  • the second gamma reference voltage group VREF 2 may have voltage levels for compensating the deviation of the second pixel PX 2 .
  • the first and second gamma reference voltage groups VREF 1 and VREF 2 may be alternately provided to the pixels PX 1 and PX 2 arranged along the first direction D 1 on a row-by-row basis.
  • the first gamma reference voltage group VREF 1 may be provided to odd rows of the pixels PX 1 and PX 3
  • the second gamma reference voltage group VREF 2 may be provided to even rows of the pixels PX 2 and PX 4 .
  • the gamma voltage generating unit 12 may include a first gamma unit that generates the first gamma reference voltage group VREF 1 and a second gamma unit that generates the second gamma reference voltage group VREF 2 .
  • the first gamma unit may include a first resistor-string (e.g., a resistive divider or a series of resistors) for voltage division
  • the second gamma unit may include a second resistor-string (e.g., resistive divider or a series of resistors) for voltage division.
  • Each of the first and second resistor-strings may include a plurality of resistors.
  • the first and second resistor-strings may receive a power supply voltage from a power generating unit (not shown), and may divide the power supply voltage to generate the first and second gamma reference voltage groups VREF 1 and VREF 2 , respectively.
  • the first and second gamma reference voltage groups VREF 1 and VREF 2 generated in the gamma voltage generating unit 12 may be provide to the data driving unit 14 .
  • the data driving unit 14 may receive pixel data DATA′ and control signals CONT 1 and GSEL from the controlling unit 16 .
  • the data driving unit 14 may convert the pixel data DATA′ into analog pixel voltages based on the first and second gamma reference voltage groups VREF 1 and VREF 2 , and may output the pixel voltages to the pixels PX 1 , PX 2 , PX 3 , and PX 4 through the data lines DL 1 and DL 2 .
  • a first pixel data corresponding to the first pixel PX 1 may be converted into a first pixel voltage based on the first gamma reference voltage group VREF 1 , and the first pixel voltage may be provided to the first pixel PX 1 .
  • a second pixel data corresponding to the second pixel PX 2 may be converted into a second pixel voltage base on the second gamma reference voltage group VREF 2 , and the second pixel voltage may be provided to the second pixel PX 2 .
  • the pixel data DATA′ provided from the controlling unit 16 may be a digital signal.
  • the data driving unit 14 may convert the pixel data DATA′ of the digital type into the pixel voltages of the analog type.
  • the control signals CONT 1 and GSEL may include a data control signal CONT 1 and a gamma selecting signal GSEL.
  • the data control signal CONT 1 may include a horizontal start signal STH indicating a start of data transmission for a row of the pixels PX 1 and PX 3 arranged along the second-direction D 2 , a load signal LOAD for applying the pixel voltages to the data lines, and a data clock signal DCLK for timing synchronization.
  • the data control signal CONT 1 may further include a polarity inverse signal for inverting a polarity of the pixel voltages.
  • the gamma selecting signal GSEL may control a selection of the first reference voltage group VREF 1 or the second reference voltage group VREF 2 .
  • the gamma selecting signal GSEL may have substantially the same period as the horizontal start signal STH.
  • the first and second pixels PX 1 and PX 2 arranged along the first direction D 1 may be sequentially operated, and a selection period of the first and second gamma reference voltage groups VREF 1 and VREF 2 may be substantially the same as an operating period of the first and second pixels PX 1 and PX 2 .
  • the data driving unit 14 may include a shift register 14 a , a latch 14 b , a digital-to-analog converter 14 c , a buffer 14 d , and a gamma voltage selector 14 e .
  • the shift register 14 a may receive the pixel data DATA′, the horizontal start signal STH and the data clock signal DCLK.
  • the shift register 14 a may sequentially shift the received pixel data DATA′ in response to the data clock signal DCLK, and may provide the pixel data DATA′ to the latch 14 b .
  • the latch 14 b may temporarily store the pixel data DATA′ provided from the shift register 14 a , and may concurrently (e.g., substantially simultaneously) output the stored pixel data DATA′ to the digital-analog converter 14 c in response to the load signal LOAD.
  • the digital-to-analog converter 14 c may convert the pixel data DATA′ into the pixel voltages of the analog type based on the first gamma reference voltage group VREF 1 or the second gamma reference voltage group VREF 2 provided from the gamma voltage selector 14 e , and may output the pixel voltages to the buffer 14 d .
  • the digital-to-analog converter 14 c may receive the polarity inverse signal and may output the pixel voltages that are inverted in response to the polarity inverse signal.
  • the buffer 14 d may output the pixel voltages provided from the digital-to-analog converter 14 c to the data lines DL 1 and DL 2 , and thus the buffer 14 d may provide the pixel voltages to the pixels PX 1 , PX 2 , PX 3 , and PX 4 .
  • the gamma voltage selector 14 e may receive the first and second gamma reference voltage groups VREF 1 and VREF 2 from the gamma voltage generating unit 12 , and may select one of the first and second gamma reference voltage groups VREF 1 and VREF 2 in response to the gamma selecting signal GSEL.
  • the gamma voltage selector 14 e may output the selected gamma reference voltage group to the digital-to-analog converter 14 c .
  • the gamma voltage selector 14 e may select and output the first gamma reference voltage group VREF 1 when driving the first pixel PX 1 , and may select and output the second reference voltage group VREF 2 when driving the second pixel PX 2 .
  • the gamma voltage selector 14 e may include a multiplexer for outputting one of the first and second gamma reference voltage groups VREF 1 and VREF 2 .
  • the controlling unit 16 may receive an image data DATA and synchronization signals CONT from an external image source, such as a graphics device.
  • the synchronization signals CONT may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE) and a main clock signal (MCLK).
  • the controlling unit 16 may generate the gamma selecting signal GSEL, the data control signal CONT 1 and a gate control signal CONT 2 for driving the display panel 100 based on the synchronization signals CONT.
  • the controlling unit 16 may output the data control signal CONT 1 and the gate control signal CONT 2 to the data driving unit 14 and the gate driving unit 18 , respectively.
  • the pixel data DATA′ output to the data driving unit 14 may include pixel data of three colors corresponding to a red pixel, a green pixel and a blue pixel.
  • the gate driving unit 18 may sequentially output gate signals in response to the gate control signal CONT 2 to activate the gate lines GL 1 and GL 2 . Since the gate driving unit 18 sequentially outputs the gate signals, the pixels PX 1 , PX 2 , PX 3 , and
  • the gate control signal CONT 2 may include a scanning start signal STV indicating a start of scanning and a clock signal CLK for controlling an output time of a gate-on voltage VON.
  • the gate driving unit 18 may receive the gate-on voltage VON and a gate-off voltage VOFF for generating the gate signals from a power generating unit (not shown).
  • FIG. 3A is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 3B is a cross-sectional view of an example embodiment of a display panel taken along a line I-I′ of FIG. 3A .
  • a display panel 100 includes a display substrate 110 , an opposing substrate 120 and a liquid crystal layer 130 .
  • the opposing substrate 120 may be opposed to the display substrate 110
  • the liquid crystal layer 130 may be interposed between the display substrate 110 and the opposing substrate 120 .
  • the liquid crystal layer 130 may include a plurality of liquid crystal molecules LC.
  • the display panel 100 may further include a first polarizing plate 102 and a second polarizing plate 104 .
  • the display substrate 110 may include a first insulating substrate 111 , a plurality of signal lines and electric field generating electrodes for forming an electric field.
  • the plurality of signal lines and the electric field generating electrodes may be formed on the first insulating substrate 111 .
  • the display substrate 110 may further include switching elements SW 1 , SW 2 , SW 3 , and SW 4 for controlling an operation of the electric field generating electrodes, and a first alignment layer 112 for initially aligning the liquid crystal molecules LC.
  • the first insulating substrate 111 may include a transparent insulating material, such as glass, plastic, etc.
  • the first insulating substrate 111 may include a plurality of pixel regions PA 1 , PA 2 , PA 3 , and PA 4 corresponding to pixels PX 1 , PX 2 , PX 3 , and PX 4 illustrated in FIGS. 1 and 2 .
  • the pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may include a first pixel region PA 1 , a second pixel region PA 2 , a third pixel region PA 3 and a fourth pixel region PA 4 .
  • the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may be defined as regions for forming the first to fourth pixels PX 1 , PX 2 , PX 3 , and PX 4 illustrated in FIGS. 1 and 2 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the first direction D 1 may be a vertical direction (or a column direction).
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the second direction D 2 may be a horizontal direction (or a row direction).
  • the pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may be arranged in a matrix form.
  • the signal lines may include first and second gate lines GL 1 and GL 2 , and first and second data lines DL 1 and DL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2 .
  • the first gate line GL 1 may be located between the first and second pixel regions PA 1 and PA 2 and between the third and fourth pixel regions PA 3 and PA 4 .
  • the second gate line GL 2 may extend in parallel with the first gate line GL 1 .
  • the second and fourth pixel regions PA 2 and PA 4 may be located between the first and second gate lines GL 1 and GL 2 .
  • the first and second data lines DL 1 and DL 2 may extend in the first direction D 1 .
  • the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 , and the zigzag shape may be defined by shapes of the electric field generating electrodes.
  • the display substrate 100 may further include pad portions (not shown) formed at end portions of the first and second gate lines GL 1 and GL 2 .
  • the pad portions may be electrically coupled to a gate driving unit 18 illustrated in FIG. 1 .
  • the electric field generating electrodes may include first to fourth lower electrodes 113 _ 1 , 113 _ 2 , 113 _ 3 , and 113 _ 4 and first to fourth upper electrodes 114 _ 1 , 114 _ 2 , 114 _ 3 , and 114 _ 4 .
  • the first to fourth lower electrodes 113 _ 1 , 113 _ 2 , 113 _ 3 , and 113 _ 4 and the first to fourth upper electrodes 114 _ 1 , 114 _ 2 , 114 _ 3 , and 114 _ 4 may be transparent electrodes including a transparent conductive material.
  • the first to fourth upper electrodes 114 _ 1 , 114 _ 2 , 114 _ 3 , and 114 _ 4 may be the transparent electrodes including the transparent conductive material
  • the first to fourth lower electrodes 113 _ 1 , 113 _ 2 , 113 _ 3 , and 113 _ 4 may be opaque electrodes including an opaque conductive material.
  • the first lower electrode 113 _ 1 may be formed in the first pixel region PA 1 .
  • the first lower electrode 113 _ 1 may have a plate shape.
  • the first lower electrode 113 _ 1 may partially overlap the first gate line GL 1 and the first and second data lines DL 1 and DL 2 .
  • the second lower electrode 113 _ 2 may be formed in the second pixel region PA 2 .
  • the second lower electrode 113 _ 2 may have a plate shape.
  • the second lower electrode 113 _ 2 may partially overlap the first and second gate lines GL 1 and GL 2 and the first and second data lines DL 1 and DL 2 .
  • the first and second lower electrodes 113 _ 1 and 113 _ 2 may be integrally formed. Edge portions of the first and second lower electrodes 113 _ 1 and 113 _ 2 may be coupled to each other.
  • the first and second lower electrodes 113 _ 1 and 113 _ 2 may be coupled to each other in a region on which the first gate line GL 1 is formed.
  • the first and second lower electrodes 113 _ 1 and 113 _ 2 may be a common electrode to which a common voltage is applied.
  • the first and second lower electrodes 113 _ 1 and 113 _ 2 may be spaced apart from each other, and may have a separate structure where the common voltage is applied through a separate common electrode line (not shown).
  • the separate structure may have an island shape.
  • the third lower electrode 113 _ 3 may be formed in the third pixel region PA 3
  • the fourth lower electrode 113 _ 4 may be formed in the fourth pixel region PA 4
  • the third and fourth lower electrodes 113 _ 3 and 113 _ 4 may be integrally formed, in which edge portions of the third and fourth lower electrodes 113 _ 3 and 113 _ 4 are coupled to each other.
  • the third and fourth lower electrodes 113 _ 3 and 113 _ 4 may have a separate structure where the common voltage is applied through separate common electrode lines.
  • the third and fourth lower electrodes 113 _ 3 and 113 _ 4 may have substantially the same structure as the first and second lower electrodes 113 _ 1 and 113 _ 2 .
  • the first and second lower electrodes 113 _ 1 and 113 _ 2 may have an integral structure
  • the third and fourth lower electrodes 113 _ 3 and 113 _ 4 may have an integral structure
  • the first to fourth lower electrodes 113 _ 1 , 113 _ 2 , 113 _ 3 , and 113 _ 4 may have a stripe structure where the first and second lower electrodes 113 _ 1 and 113 _ 2 are integrally formed and the third and fourth lower electrodes 113 _ 3 and 113 _ 4 are integrally formed.
  • the first to fourth lower electrodes 113 _ 1 , 113 _ 2 , 113 _ 3 , and 113 _ 4 may have an entirely integral structure.
  • a shared electrode of the integral structure may be formed in a region except for at least contact regions of the switching elements SW 1 , SW 2 , SW 3 , and SW 4 .
  • the first upper electrode 114 _ 1 may be formed in the first pixel region PA 1 .
  • the first upper electrode 114 _ 1 may overlap the first lower electrode 113 _ 1 , and may be insulated from the first lower electrode 113 _ 1 .
  • the first upper electrode 114 _ 1 may include a first slit pattern 115 _ 1 for forming a domain of the liquid crystal layer 130 .
  • the first slit pattern 115 _ 1 may extend in a third direction different from the first and second directions D 1 and D 2 .
  • the third direction may be a direction inclined (e.g., inclined by a predetermined angle) with respect to the first direction D 1 or the second direction D 2 .
  • Slits of the first slit pattern 115 _ 1 may be spaced apart from each other (e.g., spaced apart by a predetermined distance), and may be arranged in parallel.
  • the first upper electrode 114 _ 1 may be electrically coupled to a first switching element SW 1 .
  • the first switching element SW 1 may be electrically coupled to the first gate line GL 1 and the first data line DL 1 .
  • the first switching element SW 1 may be disposed in the first pixel region PA 1 .
  • the first switching element SW 1 may include a gate electrode GE coupled to the first gate line GL 1 , a source electrode SE coupled to the first data line DL 1 , an active pattern AP including a semiconductor layer 116 a and an ohmic contact layer 116 b formed on the semiconductor layer 116 a , and a drain electrode DE spaced apart from the source electrode SE.
  • the drain electrode DE may make contact with the first upper electrode 114 _ 1 such that the first upper electrode 114 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the first upper electrode 114 _ 1 may be a pixel electrode for receiving a pixel voltage from the first data line DL 1 according to a switching operation of the first switching element SW 1 .
  • Each of the second to fourth upper electrodes 114 _ 2 114 _ 3 , and 114 _ 4 may be substantially similar to the first upper electrode 114 _ 1 except for a position and an extending direction of a slit pattern, and each of the second to fourth switching elements SW 2 , SW 3 , and SW 4 may be substantially similar to the first switching element SW 1 except for an electrical connection.
  • differences will be briefly described hereinafter, and any repetitive descriptions may be omitted.
  • the second upper electrode 114 _ 2 may be formed in the second pixel region PA 2 .
  • the second upper electrode 114 _ 2 may overlap the second lower electrode 113 _ 2 , and may be insulated from the second lower electrode 113 _ 2 .
  • the second upper electrode 114 _ 2 may include a second slit pattern 115 _ 2 for forming the domain of the liquid crystal layer 130 .
  • the second slit pattern 115 _ 2 may extend in a fourth direction different from the first and second directions D 1 and D 2 and the third direction.
  • the third and fourth directions may be symmetrical to each other with respect to the first gate line GL 1 , or with respect to the second direction D 2 .
  • Slits of the second slit pattern 115 _ 2 may be spaced apart from each other (e.g., spaced apart by a predetermined distance), and may be arranged in parallel.
  • the second upper electrode 114 _ 2 may be electrically coupled to a second switching element SW 2 .
  • the second switching element SW 2 may be electrically coupled to the second gate line GL 2 and the first data line DL 1 .
  • the second switching element SW 2 may be located in the second pixel region PA 2 . Since the second upper electrode 114 _ 2 is electrically coupled to the second switching element SW 2 , the second upper electrode 114 _ 2 may serve as a pixel electrode for receiving a pixel voltage from the first data line DL 1 according to a switching operation of the second switching element SW 2 .
  • Sides of the first and second upper electrodes 114 _ 1 and 114 _ 2 that are adjacent to the first and second data lines DL 1 and DL 2 may extend in an extending direction of the first and second slit patterns 115 _ 1 and 115 _ 2 .
  • the sides of the first upper electrode 114 _ 1 may be in parallel with the first slit pattern 115 _ 1
  • the sides of the second upper electrode 114 _ 2 may be in parallel with the second slit pattern 115 _ 2 .
  • the second data line DL 2 may have a bent structure.
  • the second data line DL 2 may have a zigzag pattern where the bent structure is repeated along the first direction D 1 .
  • the second data line DL 2 may include extension portions in parallel with the first and second slit patterns 115 _ 1 and 115 _ 2 .
  • the second data line DL 2 may include an extension portion extending in the third direction that is substantially the same as the extending direction of the first slit pattern 115 _ 1 between the first and third pixel regions PA 1 and PA 3 , and an extension portion extending in the fourth direction that is substantially the same as the extending direction of the second slit pattern 115 _ 2 between the second and fourth pixel regions PA 2 and PA 4 .
  • the first data line DL 1 may have substantially the same bent structure as the second data line DL 2 .
  • the first data line DL 1 may have a zigzag pattern where the bent structure is repeated along the first direction D 1 .
  • the first and second data lines DL 1 and DL 2 may be arranged such that the first and second pixel regions PA 1 and PA 2 are interposed therebetween.
  • the first data line DL 1 may have substantially the same shape as the second data line DL 2 such that the first and second data lines DL 1 and DL 2 are in parallel with each other.
  • Sides of the first and second upper electrodes 114 _ 1 and 114 _ 2 that are adjacent to the first and second data lines DL 1 and DL 2 may be in parallel with the first and second data lines DL 1 and DL 2 .
  • the third upper electrode 114 _ 3 may be formed in the third pixel region PA 3 to overlap the third lower electrode 113 _ 3 .
  • the third upper electrode 114 _ 3 may include a third slit pattern 115 _ 3 extending in substantially the same direction as the first slit pattern 115 _ 1 .
  • the third upper electrode 114 _ 3 may include the third slit pattern 115 _ 3 extending in the third direction.
  • the third upper electrode 114 _ 3 may be coupled to the third switching element SW 3 .
  • the third switching element SW 3 may be electrically coupled to the first gate line GL 1 and the second data line DL 2 .
  • the third switching element SW 3 may be located in the third pixel region PA 3 . Since the third upper electrode 114 _ 3 is electrically coupled to the third switching elements SW 3 , the third upper electrode 114 _ 3 may serve as a pixel electrode for receiving a pixel voltage from the first data line DL 2 according to a switching operation of the third switching element SW 3 .
  • the fourth upper electrode 114 _ 4 may be formed in the fourth pixel region PA 4 to overlap the fourth lower electrode 113 _ 4 .
  • the fourth upper electrode 114 _ 4 may include a fourth slit pattern 115 _ 4 extending in substantially the same direction as the second slit pattern 115 _ 2 .
  • the fourth upper electrode 114 _ 4 may include the fourth slit pattern 115 _ 4 extending in the fourth direction.
  • the fourth upper electrode 114 _ 4 may be coupled to the fourth switching element SW 4 .
  • the fourth switching element SW 4 may be electrically coupled to the second gate line GL 2 and the second data line DL 2 .
  • the fourth switching element SW 4 may be located in the fourth pixel region PA 4 . Since the fourth upper electrode 114 _ 4 is electrically coupled to the fourth switching element SW 4 , the fourth upper electrode 114 _ 4 may serve as a pixel electrode receiving the pixel voltage from the first data line DL 2 according to a switching operation of the fourth switching element SW 4 .
  • the third upper electrode 114 _ 3 includes the third slit pattern 115 _ 3 that is in parallel with the first slit pattern 115 _ 1 of the first upper electrode 114 _ 1 , the third upper electrode 114 _ 3 may form the domain of the liquid crystal layer 130 in a direction that is substantially the same as that of the domain that the first upper electrode 114 _ 1 forms. Further, since the fourth upper electrode 114 _ 4 includes the fourth slit pattern 115 _ 4 that is in parallel with the second slit pattern 115 _ 2 of the second first upper electrode 114 _ 2 , the fourth upper electrode 114 _ 4 may form the domain of the liquid layer 130 in a direction that is substantially the same as that of the domain that the second upper electrode 114 _ 2 forms.
  • adjacent upper electrodes 114 _ 1 and 114 _ 3 that are arranged along the second direction D 2 may form the same domain, and adjacent upper electrodes 114 _ 2 and 114 _ 4 that are arranged along the first direction D 1 may form different domains.
  • the first alignment layer 112 may be formed on the first insulating layer 111 on which the first to fourth upper electrodes 114 _ 1 , 114 _ 2 , 114 _ 3 , and 114 _ 4 are formed.
  • the first alignment layer 112 may be treated such that a surface alignment of the first alignment layer 112 is substantially the same with respect to the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 when viewed from the top.
  • the first alignment layer 112 in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may be treated to have a single alignment direction.
  • the first alignment layer 112 may be formed on an entire surface of the first insulating layer 111 , and may have a single alignment direction on the entire surface of the first insulating layer 111 .
  • an alignment direction of the first alignment layer 112 may be defined as a direction in which the first alignment layer 112 arranges the liquid crystal molecules LC.
  • the first alignment layer 112 may have the alignment direction by a rubbing treatment or a photo alignment treatment.
  • the first alignment layer 112 may have the alignment direction by various processes different from the above treatments.
  • the alignment direction of the first alignment layer 112 may be the first direction D 1 or the second direction D 2 . Since the first alignment layer 112 may have substantially the same alignment direction of the first direction D 1 or the second direction D 2 with respect to the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , the alignment direction of the first alignment layer 112 may be balanced between extending directions of the first and second slit patterns 115 _ 1 and 115 _ 2 . Thus, the liquid crystal molecules LC in the first pixel region PA 1 and the second pixel region PA 2 may be driven in directions that are symmetrical to each other, and the liquid crystal molecules LC in the third pixel region PA 3 and the fourth pixel region PA 4 may be driven in directions that are symmetrical to each other. Therefore, in a display device including the display substrate 110 according to example embodiments, a color shift according to a viewing direction may not occur, and a wide viewing angle may be achieved.
  • a gate metal layer may be formed on the first insulating layer 111 and may be patterned to form a gate pattern including the first and second gate lines GL 1 and GL 2 and the gate electrodes GE.
  • the gate metal layer may include aluminum (Al), silver (Ag), molybdenum (Mo), chrome (Cr), etc.
  • the gate insulating layer 117 may be formed on the first insulating substrate 111 on which the gate pattern is formed.
  • the gate insulating layer 117 may be formed from silicon nitride (SiNx), silicon oxide (SiOx), etc.
  • the active pattern AP may be formed on the gate insulating layer 117 and may overlap the gate electrode GE.
  • the active pattern AP may include a semiconductor layer 116 a and the ohmic contact layer 116 b formed on the semiconductor layer 116 a .
  • a data metal layer may be formed on the first insulating layer 111 on which the active pattern AP is formed, and may be patterned to form a source pattern including the first and second data lines DL 1 and DL 2 , the source electrode SE, and the drain electrode DE.
  • a first passivation layer 118 may be formed on the first insulating layer 111 on which the source pattern is formed.
  • a first transparent electrode layer may be formed on the first passivation layer 118 and may be patterned to form the first to fourth lower electrodes 113 _ 1 , 113 _ 2 , 113 _ 3 , and 113 _ 4 in the first to fourth pixel regions PA 1 , PA 2 , PA 3 and PA 4 .
  • a second passivation layer 119 may be formed on the first insulating layer 111 on which the first to fourth electrodes 113 _ 1 , 113 _ 2 , 113 _ 3 , and 113 _ 4 are formed.
  • the second passivation layer 119 may cover the first to fourth electrodes 113 _ 1 , 113 _ 2 , 113 _ 3 , and 113 _ 4 .
  • the first and second passivation layers 118 and 119 may be etched to form a contact hole.
  • the drain electrode DE may be partially exposed through the contact hole.
  • a second transparent electrode layer may be formed on the second passivation layer 119 in which the contact hole is formed, and may be patterned to form the first to fourth upper electrodes 114 _ 1 , 114 _ 2 , 114 _ 3 , and 114 _ 4 .
  • the first to fourth upper electrodes 114 _ 1 , 114 _ 2 , 114 _ 3 , and 114 _ 4 may have the first to fourth slit patterns 115 _ 1 , 115 _ 2 , 115 _ 3 , and 115 _ 4 for forming the domain, respectively.
  • the first and third slit patterns 115 _ 1 and 115 _ 3 may extend in the third direction, and the second and fourth slit patterns 115 _ 2 and 115 _ 4 may extend in the fourth direction.
  • the third and fourth directions may be different from each other.
  • the third direction may be symmetrical to the fourth direction with respect to the first gate line GL 1 , for example, the second direction D 2 .
  • a preliminary layer may be formed on the first insulating layer 111 on which the first to fourth upper electrodes 114 _ 1 , 114 _ 2 , 114 _ 3 , and 114 _ 4 are formed.
  • the rubbing treatment or the photo-alignment treatment may be performed on a surface of the preliminary layer in the first direction D 1 to form the first alignment layer 112 .
  • the surface of the preliminary layer may be rubbed in the second direction D 2 .
  • the first alignment layer 112 may have substantially the same alignment direction with respect to the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the display substrate 110 may be manufactured by a different method from the above described processes and the present invention should not be construed as limited to the examples set forth herein.
  • the opposing substrate 120 may include a second insulating layer 121 , a light-blocking pattern BM and color filters CF.
  • the light-blocking pattern BM and the color filters CF may be formed on the second insulating substrate 121 .
  • the opposing substrate 120 may further include a second alignment layer 122 for initially aligning the liquid crystal molecules LC.
  • the light-blocking pattern BM may overlap the switching elements SW 1 , SW 2 , SW 3 and SW 4 and the signal lines GL 1 , GL 2 , DL 1 , and DL 2 of the display substrate 110 .
  • the color filters CF may overlap the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 of the display substrate 110 , respectively.
  • the color filters CF may include a red color filter R, a green color filter G and a blue color filter B.
  • the color filters CF may include color filters other than the red, green and blue color filters R, G and B.
  • the opposing substrate 120 may include various color filters CF according to example embodiments.
  • the second alignment layer 122 may be formed on the second insulating layer 120 on which the light-blocking pattern BM and the color filters are formed.
  • the second alignment layer 122 may face the first display substrate 110 , and may be located on a surface of the second insulating substrate 120 adjacent to the liquid crystal layer 130 .
  • the second alignment layer 122 may be formed by a method that is substantially the same as the method by which the first alignment layer 112 is formed.
  • the second alignment layer 122 may be treated such that a surface alignment of the second alignment layer 122 is substantially the same in the regions corresponding to the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 when viewed from the top.
  • the second alignment layer 112 may have a single alignment direction in an entire surface of the second insulating substrate 120 .
  • the second alignment layer 122 may have an alignment direction by a rubbing treatment or a photo alignment treatment.
  • the alignment direction of the second alignment layer 122 may be defined as a direction in which the second alignment layer 122 arranges the liquid crystal molecules LC.
  • the alignment direction of the second alignment layer 122 may be substantially the same as the alignment direction of the first alignment layer 112 .
  • the alignment direction of the second alignment layer 122 may be the first direction D 1 or the second direction ‘D 2 .
  • the alignment direction of the second alignment layer 122 may be the first direction D 1 .
  • the alignment direction of the second alignment layer 122 may be the second direction D 2 .
  • the first polarizing plate 102 may be located on an outer surface of the display substrate 110
  • a second polarizing plate 104 may be located on an outer surface of the opposing substrate 120 .
  • the first polarizing plate 102 may be located on a lower surface of the display substrate 110 , for example, an opposing surface of the first insulating substrate 111 to a surface adjacent to the liquid crystal layer 130 .
  • the first polarizing plate 102 may have a polarizing axis that is substantially the same as the alignment direction of the first alignment layer 112 included in the display substrate 110 .
  • the first polarizing plate 102 may have the polarizing axis of the first direction D 1 .
  • the first polarizing plate 102 may have the polarizing axis of the second direction D 2 .
  • the second polarizing plate 104 may be located on an opposing surface of the second insulating substrate 121 to a surface adjacent to the liquid crystal layer 130 .
  • a polarizing axis of the second polarizing plate 104 may be perpendicular to the polarizing axis of the first polarizing plate 102 .
  • the second polarizing plate 104 may have the polarizing axis perpendicular to the alignment direction of the second alignment layer 122 included in the opposing substrate 120 .
  • the first to fourth pixels PX 1 , PX 2 , PX 3 , and PX 4 of the display panel 100 may be defined by the electric field generating electrodes formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 and the liquid crystal layer 130 .
  • the first pixel PX may be defined by the first lower electrode 113 _ 1 , the first upper electrode 114 _ 1 and the liquid crystal layer 130 disposed in the first pixel region PA 1 .
  • the second pixel PX 2 may be defined by the second lower electrode 113 _ 2 , the second upper electrode 114 _ 2 and the liquid crystal layer 130 disposed in the second pixel region PA 2 .
  • the third pixel PX 3 may be defined by the third lower electrode 113 _ 3 , the third upper electrode 114 _ 3 and the liquid crystal layer 130 disposed in the third pixel region PA 3 .
  • the fourth pixel PX 4 may be defined by the fourth lower electrode 113 _ 4 , the fourth upper electrode 114 _ 4 and the liquid crystal layer 130 disposed in the fourth pixel region PA 4 .
  • the first to fourth upper electrodes 114 _ 1 , 114 _ 2 , 114 _ 3 , and 114 _ 4 as the electric field generating electrodes may include the first to fourth slit patterns 115 _ 1 , 115 _ 2 , 115 _ 3 , and 115 _ 4 .
  • Each of the first to fourth pixels PX 1 , PX 2 , PX 3 , and PX 4 may have a single domain.
  • the domain direction of the first pixel PX 1 may be different from that of the second pixel PX 2
  • the domain direction of the third pixel PX 3 may be different from that of the fourth pixel PX 4
  • the domain of the first pixel PX 1 may be symmetrical to the domain of the second pixel PX 2 with respect to the first gate line GL 1
  • the domain of the third pixel PX 3 may be symmetrical to the domain of the fourth pixel PX 4 with respect to the first gate line GL 1
  • the alignment direction of the first alignment layer 112 may be a single direction with respect to the entire display substrate 110 . Therefore, light transmittance may be improved by a single domain, and a viewing angle and visibility may be improved by a multi-domain.
  • different gamma reference voltage groups serving as a basis of driving voltages may be used in the first and second pixels PX 1 and PX 2 , and thus a luminance difference that may occur between adjacent row lines having different domains, may be compensated to improve visibility.
  • FIG. 4 is a block diagram illustrating a display device in accordance with example embodiments.
  • FIG. 5 is a block diagram illustrating a gamma voltage generating unit included in a display device of FIG. 4 .
  • FIG. 6 is a block diagram illustrating a data driving unit included in a display device of FIG. 4 .
  • a display device 20 includes a display panel 200 , a gamma voltage generating unit 22 , a data driving unit 24 , a controlling unit 26 and a gate driving unit 28 .
  • the gamma voltage generating unit 22 , the data driving unit 24 , the controlling unit 26 , and the gate driving unit 28 may drive the display panel 200 to display an image based on an image signal provided from an image source, such as an external graphics device.
  • the display device 20 may be substantially the same as the display device 10 illustrated in FIGS. 1 and 2 , except for the gamma voltage generating unit 22 and the data driving unit 24 . Thus, any repetitive descriptions may be omitted.
  • the gamma voltage generating unit 22 may generate gamma reference voltage groups VREF 1 and VREF 2 , each including gamma voltages provided to pixels PX 1 , PX 2 , PX 3 , and PX 4 of the display panel 200 .
  • the gamma voltage generating unit 22 may generate a first gamma reference voltage group VREF 1 and a second gamma reference voltage group VREF 2 .
  • the first and second gamma reference voltage groups VREF 1 and VREF 2 may have different voltage levels from each other.
  • the first gamma reference voltage group VREF 1 may be a group of gamma voltages according to a first gamma curve having a first gamma value
  • the second gamma reference voltage group VREF 2 may be a group of gamma voltages according to a second gamma curve having a second gamma value different from the first gamma value.
  • Each of the first and second gamma values may be set to compensate for a variation according to domains of the pixels PX 1 , PX 2 , PX 3 , and PX 4 .
  • the first gamma reference voltage group VREF 1 may have voltage levels for compensating for the variation of the first and third pixels PX 1 and PX 3
  • the second gamma reference voltage group VREF 2 may have voltage levels for compensating for the variation of the second and fourth pixels PX 2 and PX 4 .
  • the gamma voltage generating unit 22 may receive a gamma selecting signal GSEL.
  • the gamma selecting signal GSEL may control a selection of the first reference voltage group VREF 1 or the second reference voltage group VREF 2 . Since the first and second gamma reference voltage groups VREF 1 and VREF 2 may be alternately used in converting pixel data DATA’ on a row-by-row basis, the gamma selecting signal GSEL may have substantially the same period as a horizontal start signal STH.
  • the first and second pixels PX 1 and PX 2 arranged along the first direction D 1 may be sequentially operated, and a selection period of the first and second gamma reference voltage groups VREF 1 and VREF 2 may be substantially the same as an operating period of the first and second pixels PX 1 and PX 2 .
  • the gamma voltage generating unit 22 may include a first gamma unit 22 a , a second gamma unit 22 b , and a gamma voltage selector 22 c.
  • the first gamma unit 22 a may receive a power supply voltage, and may divide the power supply voltage to generate the first gamma reference voltage group VREF 1 .
  • the first gamma unit 22 a may include a first resistor-string (e.g., a resistive divider or a series of resistors) for voltage division.
  • the first resistor-string may include a plurality of resistors.
  • the second gamma unit 22 b may receive the power supply voltage, and may divide the power supply voltage to generate the second gamma reference voltage group VREF 2 .
  • the second gamma unit 22 b may include a second resistor-string (e.g., a resistive divider or a series of resistors) for voltage division.
  • the second resistor-string may include a plurality of resistors.
  • the resistors of second resistor-string may have resistances different from resistances of the resistors of the first resistor-string.
  • the gamma voltage selector 22 c may receive the first and second gamma reference voltage group VREF 1 and VREF 2 from the first and second gamma unit 22 a and 22 b , and may receive the gamma selecting signal GSEL from the controlling unit 26 .
  • the gamma voltage selector 24 c may select one of the first and second gamma reference voltage groups VREF 1 and VREF 2 in response to the gamma selecting signal GSEL, and may output the selected gamma reference voltage group to the data driving unit 24 .
  • the gamma voltage selector 24 c may select and output the first gamma reference voltage group VREF 1 when driving the first pixel PX 1 , and may select and output the second reference voltage group VREF 2 when driving the second pixel PX 2 .
  • the gamma voltage selector 22 c may include a multiplexer for outputting one of the first and second gamma reference voltage group VREF 1 and VREF 2 .
  • the gamma voltage generating unit 22 may output one of the first and second gamma reference voltage groups VREF 1 and VREF 2 at a given time point.
  • the data driving unit 24 may receive pixel data DATA′ and a data control signal CONT 1 from the controlling unit 26 .
  • the data driving part 14 may convert the pixel data DATA′ into analog pixel voltages based on the first and second gamma reference voltage groups VREF 1 and VREF 2 , and may output the pixel voltages to the pixels PX 1 , PX 2 , PX 3 , and PX 4 through the data lines DL 1 and DL 2 .
  • a first pixel data corresponding to the first pixel PX 1 may be converted into a first pixel voltage based on the first gamma reference voltage group VREF 1 , and the first pixel voltage may be provided to the first pixel PX 1 .
  • a second pixel data corresponding to the second pixel PX 2 may be converted into a second pixel voltage base on the second gamma reference voltage group VREF 2 , and the second pixel voltage may be provided to the second pixel PX 2 .
  • the pixel data DATA′ provided from the controlling unit 26 may be a digital signal.
  • the data driving unit 24 may convert the pixel data DATA′ of the digital type into the pixel voltages of the analog type.
  • the data control signal CONT 1 may include a horizontal start signal STH indicating a start of data transmission for a row of the pixels PX 1 and PX 3 arranged along the second direction D 2 , a load signal LOAD for applying the pixel voltages to the data lines, and a data clock signal DCLK for timing synchronization.
  • the data control signal CONT 1 may further include a polarity inverse signal for inverting a polarity of the pixel voltages.
  • the data driving unit 24 may include a shift register 24 a , a latch 24 b , a digital-to-analog converter 24 c and a buffer 24 d .
  • the data driving unit 24 may be substantially the same as the data driving unit 14 illustrated in FIG. 2 , except for the digital-to-analog converter 24 c . Thus, any repetitive descriptions may be omitted.
  • the digital-to-analog converter 24 c may receive the first gamma reference voltage group VREF 1 or the second gamma reference voltage group VREF 2 from the gamma voltage generating unit 22 .
  • the digital-to-analog converter 24 c may convert the pixel data DATA′ into the pixel voltages of the analog type based on the first gamma reference voltage group VREF 1 or the second gamma reference voltage group VREF 2 provided from the gamma voltage generating unit 22 , and may output the pixel voltages to the buffer 24 d.
  • FIG. 7 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 300 of FIG. 7 may be included in a display device 10 illustrated in FIGS. 1 and 2 , or in a display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 300 may be substantially the same as a display panel 100 illustrated in FIGS. 3A and 3B , except for a display substrate 310 .
  • the display substrate 310 in FIG. 7 may be substantially the same as a display substrate 110 illustrated in FIGS. 3A and 3B , except for a structure of a slit pattern in each upper electrode.
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 310 may include an insulating substrate, a plurality of signal lines and electric field generating electrodes for forming an electric field.
  • the display substrate 310 may further include switching elements SW 1 , SW 2 , SW 3 , and SW 4 for controlling an operation of the electric field generating electrodes, and a first alignment layer for initially aligning liquid crystal molecules.
  • the insulating substrate may include first to fourth pixel regions PA 1 , PA 2 ,
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the signal lines may include first and second gate lines GL 1 and GL 2 and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2
  • the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 .
  • a first lower electrode 313 _ 1 , a second lower electrode 313 _ 2 , a third lower electrode 313 _ 3 and a fourth lower electrode 313 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • a first upper electrode 314 _ 1 , a second upper electrode 314 _ 2 , a third upper electrode 314 _ 3 and a fourth upper electrode 314 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrodes 314 _ 1 , 314 _ 2 , 314 _ 3 , and 314 _ 4 may overlap the first to fourth lower electrodes 313 _ 1 , 313 _ 2 , 313 _ 3 , and 313 _ 4 , respectively.
  • the first to fourth upper electrodes 314 _ 1 , 314 _ 2 , 314 _ 3 , and 314 _ 4 may have a first slit pattern 315 _ 1 , a second slit pattern 315 _ 2 , a third slit pattern 315 _ 3 and fourth slit pattern 315 _ 4 , respectively.
  • the first and third slit patterns 315 _ 1 and 315 _ 3 may extend in a third direction different from the first and second directions D 1 and D 2 .
  • the second and fourth slit patterns 315 _ 2 and 315 _ 4 may extend in a fourth direction different from the first and second directions D 1 and D 2 and the third direction.
  • the first slit pattern 315 _ 1 formed in the first upper electrode 314 _ 1 may include a first curved portion 315 _ 1 a located at an edge portion of the first slit pattern 315 _ 1 and having an inclined angle with respect to the second direction D 2 .
  • the inclined angle of the first curved portion 315 _ 1 a to the second direction D 2 may decrease in a direction toward an end of the first slit pattern 315 _ 1 .
  • the first curved portion 315 _ 1 a may have a curved structure in which the edge portion of the first slit pattern 315 _ 1 is bent toward the second direction D 2 .
  • an.electrical distortion may occur in a region corresponding to the edge portion of the first slit pattern 315 _ 1 , so that an aperture ratio may be reduced.
  • the electrical distortion may be reduced or minimized by the first curved portion 315 _ 1 a having the curved structure, and the aperture ratio may be improved in the region corresponding to the edge portion of the first slit pattern 315 _ 1 .
  • the second slit pattern 315 _ 2 formed in the second upper electrode 314 _ 2 may include a second curved portion 315 _ 2 a located at an edge portion of the second slit pattern 315 _ 2 a and having an inclined angle with respect to the second direction D 2 .
  • the second curved portion 315 _ 2 a may have a curved structure in which the edge portion of the second slit pattern 315 _ 2 is bent toward the second direction D 2 . The electrical distortion may be reduced or minimized by the second curved portion 315 _ 2 a.
  • the third slit pattern 315 _ 3 may include a third curved portion 315 _ 3 a such that an edge portion of the third slit pattern 315 _ 3 is bent toward the second direction D 2 .
  • the third curved portion 3153 a may have substantially the same structure as the first curved portion 315 _ 1 a.
  • the fourth slit pattern 315 _ 4 includes a fourth curved portion 315 4 a such that an edge portion of the fourth slit pattern 315 4 is bent toward the second direction D 2 .
  • the fourth curved portion 315 _ 4 a may have substantially the same structure as the second curved portion 315 _ 2 a.
  • the first and second curved portions 3151 a and 315 _ 2 a may have a symmetric structure to each other with respect to the first gate line GL 1 .
  • the first curved portion 315 _ 1 a may be located at the edge portion of the first slit pattern 315 _ 1 which is distant from the first gate line GL 1
  • the second curved portion 315 _ 2 a may be located at the edge portion of the second slit pattern 315 _ 2 which is distant from the first gate line GL 1
  • the third and fourth curved portions 315 _ 3 a and 315 _ 4 a may be substantially the same as the first and second curved portions 315 _ 1 a and 315 _ 2 a , respectively.
  • each curved portion 315 _ 1 a , 315 _ 2 a , 315 _ 3 a and 315 _ 4 a may be located at one edge portion of a corresponding slit pattern 315 _ 1 , 3152 , 315 _ 3 , and 315 _ 4 .
  • the curved portion 315 _ 1 a , 315 _ 2 a , 315 _ 3 a , and 315 _ 4 a may be located at both edge portions of the corresponding slit pattern 315 _ 1 , 315 _ 2 , 315 _ 3 , and 315 _ 4 .
  • FIG. 8 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 400 of FIG. 8 may be included in the display device 10 illustrated referring to FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 400 may be substantially the same as the display panel 100 illustrated in FIGS. 3A and 3B , except for a display substrate 410 .
  • the display substrate 410 in FIG. 8 may be substantially the same as the display substrate 110 illustrated in FIGS. 3A and 3B , except for a structure of a slit pattern in each upper electrode and an arrangement of switching elements.
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 410 may include an insulating substrate, a plurality of signal lines and electric field generating electrodes for forming an electric field.
  • the plurality of signal lines and the electric field generating electrodes may be formed on the insulating substrate.
  • the display substrate 410 may further include switching elements SW 1 , SW 2 , SW 3 , and SW 4 for controlling an operation of the electric field generating electrodes, and a first alignment layer for initially aligning the liquid crystal molecules.
  • the insulating substrate may have a first pixel region PA 1 , a second pixel region PA 2 , a third pixel region PA 3 and a fourth pixel region PA 4 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the signal lines may include first and second gate lines GL 1 and GL 2 and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2 ,
  • the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 .
  • a first lower electrode 413 _ 1 , a second lower electrode 4132 , a third lower electrode 4133 , and a fourth lower electrode 413 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • a first upper electrode 414 _ 1 , a second upper electrode 4142 , a third upper electrode 414 _ 3 and a fourth upper electrode 414 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrodes 414 _ 1 , 414 _ 2 , 414 _ 3 , and 414 _ 4 may overlap the first to fourth lower electrodes 413 _ 1 , 413 _ 2 , 413 _ 3 , and 413 _ 4 , respectively.
  • the first to fourth upper electrodes 414 _ 1 , 414 _ 2 , 414 _ 3 , and 414 _ 4 may have a first slit pattern 415 _ 1 , a second slit pattern 415 _ 2 , a third slit pattern 415 _ 3 , and a fourth slit pattern 415 _ 4 , respectively.
  • the first and third slit patterns 415 _ 1 and 415 _ 3 may extend in a third direction different from the first and second directions D 1 and D 2 .
  • the second and fourth slit patterns 415 _ 2 and 415 _ 4 may extend in a fourth direction different from the first and second directions D 1 and D 2 and the third direction.
  • the first slit pattern 415 _ 1 formed in the first upper electrode 414 _ 1 may include a first curved portion 415 _ 1 a located at both edge portions of the first slit pattern 415 _ 1 . That is, the first curved portion 415 _ 1 a may be located at a first edge portion of the first slit pattern 415 _ 1 , and may be located at a second edge portion of the first slit pattern 415 _ 1 opposed to the first edge portion.
  • the first curved portion 415 _ 1 a may have an inclined angle with respect to the second direction D 2 , and the inclined angle of the first curved portion 415 _ 1 a to the second direction D 2 may decrease in a direction toward an end of the first slit pattern 415 _ 1 .
  • the first curved portion 415 _ 1 a may have a curved structure in which the first and second edge portions of the first slit pattern 415 _ 1 are bent toward the second direction D 2 .
  • a function of the first curved portion 415 _ 1 a is substantially the same as that of the first curved portion 315 _ 1 a illustrated in FIG. 7 .
  • the second slit pattern 415 _ 2 formed in the second upper electrode 414 _ 2 may include a second curved portion 415 _ 2 a located at each of a first edge portion of the second slit pattern 415 _ 2 and a second edge portion of the second slit pattern 415 _ 2 opposed to the first edge portion.
  • the second curved portion 415 _ 2 a may have an inclined angle with respect to the second direction D 2 , and the inclined angle of the second curved portion 415 _ 2 a to the second direction D 2 may decrease in a direction toward an end of the second slit pattern 415 _ 2 .
  • the second curved portion 415 _ 2 a may have a curved structure in which the first and second edge portions of the second slit pattern 415 _ 2 are bent toward the second direction D 2 .
  • a function of the second curved portion 415 _ 2 a may be substantially the same as that of the second curved portion 315 _ 2 a illustrated in FIG. 7 .
  • the third slit pattern 415 _ 3 formed in the third upper electrode 414 _ 3 may include a third curved portion 415 _ 3 a located at each of a first edge portion of the third slit pattern 415 _ 3 and a second edge portion of the third slit pattern 415 _ 3 opposed to the first edge portion.
  • the third slit pattern 415 _ 3 may extend in the same direction as the first slit pattern 415 _ 1 , and the third curved portion 415 _ 3 a may have substantially the same structure as the first curved portion 415 _ 1 a.
  • the fourth slit pattern 415 _ 4 formed in the fourth upper electrode 415 _ 4 a may include a fourth curved portion 415 _ 4 a located at each of a first edge portion of the fourth slit pattern 415 _ 4 and a second edge portion of the fourth slit pattern 415 _ 4 opposed to the first edge portion.
  • the fourth slit pattern 415 _ 4 may extend in the same direction as the second slit pattern 415 _ 2
  • the fourth curved portion 415 _ 4 a may have substantially the same structure as the second curved portion 415 _ 2 a.
  • the first and second curved portions 415 _ 1 a and 415 _ 2 a may have symmetric patterns to each other with respect to the first gate line GL 1 .
  • the third and fourth curved portions 415 _ 3 a and 415 _ 4 a may have symmetric patterns to each other with respect to the first gate line GL 1
  • the first upper electrode 414 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the switching element SW 1 may be coupled to the first gate line GL 1 and the second data line DL 2 .
  • the first and second data lines DL 1 and DL 2 may be in parallel with each other, and the first and second pixel regions PA 1 and PA 2 may be located between the first and second data lines DL 1 and DL 2 .
  • the second upper electrode 414 _ 2 may be electrically coupled to the second switching element SW 2 .
  • the switching element SW 2 may be coupled to the second gate line GL 2 and the first data line DL 1 .
  • the first switching element SW 1 may be coupled to the second data line DL 2
  • the second switching element SW 2 may be coupled to the first data line DL 1 that is different from the second data line DL 2 to which the first switching element SW 1 is coupled.
  • the first switching element SW 1 may be located adjacently to the second data line DL 2
  • the second switching element SW 2 may be located adjacently to the first data line DL 1 .
  • an arrangement of the first and second switching elements SW 1 and SW 2 may be symmetric.
  • the first switching element SW 1 may be located at a right portion adjacent to the second data line DL 2 in the first pixel region PA 1
  • the second switching element SW 2 may be located at a left portion adjacent to the first data line DL 1 in the second pixel region PA 2 .
  • the third and fourth upper electrodes 414 _ 3 and 414 _ 4 may be electrically coupled to third and fourth switching elements SW 3 and SW 4 .
  • the third and fourth switching elements SW 3 and SW 4 may have substantially the same structure as the first and second switching elements SW 1 and SW 2 .
  • an arrangement of the first to fourth switching elements SW 1 , SW 2 , SW 3 and SW 4 may be changed along the first direction D 1 . Therefore, light-blocking regions may be alternately disposed, so that the display device including the display panel 400 may have balanced visibility in the left and right viewing directions.
  • FIG. 9 is a plan view illustrating a display Panel in accordance with example embodiments.
  • a display panel 500 of FIG. 9 may be included in the display device 10 illustrated in FIGS. 1 and 2 or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 500 may be substantially the same as the display panel 100 illustrated in FIGS. 3A and 3B , except for at least one element of a display substrate 510 .
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 510 may include an insulating substrate, a plurality of signal lines and electric field generating electrodes for forming an electric field.
  • the plurality of signal lines and the electric field generating electrodes may be formed on the insulating substrate.
  • the display substrate 510 may further include switching elements SW 1 , SW 2 , SW 3 , and SW 4 for controlling an operation of the electric field generating electrodes, and a first alignment layer for initially aligning the liquid crystal molecules.
  • the insulating substrate may have a first pixel region PA 1 , a second pixel region PA 2 , a third pixel region PA 3 , and a fourth pixel region PA 4 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the signal lines may include first and second gate lines GL 1 and GL 2 and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2 .
  • the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 .
  • a first lower electrode 513 _ 1 , a second lower electrode 513 _ 2 , a third lower electrode 5133 , and a fourth lower electrode 513 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • a first upper electrode 514 _ 1 , a second upper electrode 514 _ 2 , a third upper electrode 514 _ 3 , and a fourth upper electrode 514 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrodes 514 _ 1 , 514 _ 2 , 514 _ 3 , and 514 _ 4 may overlap the first to fourth lower electrodes 513 _ 1 , 513 _ 2 , 513 _ 3 , and 513 _ 4 , respectively.
  • the first to fourth upper electrodes 514 _ 1 , 514 _ 2 , 514 _ 3 , and 514 _ 4 may have a first slit pattern 515 _ 1 , a second slit pattern 515 _ 2 , a third slit pattern 515 _ 3 , and fourth slit pattern 515 _ 4 , respectively.
  • the first and third slit pattern 515 _ 1 and 515 _ 3 may extend in a third direction different from the first and second directions D 1 and D 2 .
  • the second and fourth slit pattern 515 _ 2 and 515 _ 4 may extend in a fourth direction different from the first and second directions D 1 and D 2 and the third direction.
  • the third and fourth directions may be symmetrical to each other with respect to the first gate line GL 1 .
  • the first slit pattern 515 _ 1 formed in the first upper electrode 514 _ 1 may include a first curved portion 515 _ 1 a located at each of a first edge portion of the first slit pattern 515 _ 1 and a second edge portion of the first slit pattern 515 _ 1 opposed to the first edge portion.
  • the first curved portion 515 _ 1 a may have an inclined angle with respect to the second direction D 2 , and the inclined angle of the first curved portion 515 _ 1 a to the second direction D 2 may decrease in a direction toward an end of the first slit pattern 515 _ 1 .
  • the first curved portion 515 _ 1 a may have a curved structure in which the first and second edge portions of the first slit pattern 515 _ 1 are bent toward the second direction D 2 .
  • a function of the first curved portion 515 _ 1 a may be substantially the same as that of the first curved portion 315 _ 1 a illustrated in FIG. 7 .
  • the second slit pattern 515 _ 2 formed in the second upper electrode 514 _ 2 may include a second curved portion 515 _ 2 a located at each of a first edge portion of the second slit pattern 515 _ 2 and a second edge portion of the second slit pattern 515 _ 2 opposed to the first edge portion.
  • the second curved portion 515 _ 2 a may have an inclined angle with respect to the second direction D 2 , and the inclined angle of the second curved portion 515 _ 2 a to the second direction D 2 may decrease in a direction toward an end of the second slit pattern 515 _ 2 .
  • the second curved portion 515 _ 2 a may have a curved structure in which the first and second edge portions of the second slit pattern 515 _ 2 are bent toward the second direction D 2 .
  • a function of the second curved portion 515 _ 2 a may be substantially the same as that of the second curved portion 3152 a illustrated in FIG. 7 .
  • the third slit pattern 515 _ 3 formed in the third upper electrode 514 _ 3 may include a third curved portion 515 _ 3 a located at each of a first edge portion of the third slit pattern 515 _ 3 and a second edge portion of the third slit pattern 515 _ 3 opposed to the first edge portion.
  • the third slit pattern 515 _ 3 may extend in the same direction as the first slit pattern 515 _ 1 , and the third curved portion 515 _ 3 a may have substantially the same structure as the first curved portion 515 _ 1 a.
  • the fourth slit pattern 515 _ 4 formed in the fourth upper electrode 515 _ 4 a may include a fourth curved portion 515 _ 4 a located at each of a first edge portion of the fourth slit pattern 515 _ 4 and a second edge portion of the fourth slit pattern 515 _ 4 opposed to the first edge portion.
  • the fourth slit pattern 515 _ 4 may extend in the same direction as the second slit pattern 515 _ 2
  • the fourth curved portion 515 _ 4 a may have substantially the same structure as the second curved portion 515 _ 2 a.
  • the first and second curved portions 515 _ 1 a and 515 _ 2 a may have symmetric patterns to each other with respect to the first gate line GL 1 .
  • the third and fourth curved portions 515 _ 3 a and 515 _ 4 a ′ may have symmetric patterns to each other with respect to the first gate line GL 1
  • the first upper electrode 514 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the switching element SW 1 may be coupled to the first gate line GL 1 and the second data line DL 2 .
  • the first and second data lines DL 1 and DL 2 may be in parallel with each other, and the first and second pixel regions may be located between the first and second data lines DL 1 and DL 2 .
  • the second upper electrode 514 _ 2 may be electrically coupled to the second switching element SW 2 .
  • the switching element SW 2 may be coupled to the second gate line GL 2 and the first data line DL 1 .
  • the first switching element SW 1 may be coupled to the second data line DL 2
  • the second switching element SW 2 may be coupled to the first data line DL 1 that is different from the second data line DL 2 to which the first switching element SW 1 is coupled.
  • an arrangement of the first and second switching elements SW 1 and SW 2 are substantially the same as that of the first and second switching elements SW 1 and SW 2 illustrated in FIG. 8 .
  • the third and fourth upper electrodes 514 _ 3 and 514 _ 4 may be electrically coupled to third and fourth switching elements SW 3 and SW 4 , respectively.
  • the third and fourth switching elements SW 3 and SW 4 may have substantially the same structure as the first and second switching elements SW 1 and SW 2 .
  • first and second slit patterns 115 _ 1 and 115 _ 2 extend in the third and fourth directions
  • sides of the first and second upper electrodes 514 _ 1 and 514 _ 2 that are adjacent to the first and second data lines DL 1 and DL 2 may extend in parallel with the first and second data lines DL 1 and DL 2 .
  • each of the first and second upper electrodes 514 _ 2 and 514 _ 2 may have a rectangular shape.
  • each of the third and fourth upper electrodes 514 _ 3 and 514 _ 4 may have a rectangular shape.
  • each of the first to fourth pixel regions PA 1 , PA 2 , PA 3 and PA 4 may have a rectangular shape
  • the first to fourth lower electrodes 513 _ 1 , 513 _ 2 , 513 _ 3 , and 513 _ 4 and the first to fourth upper electrodes 514 _ 1 , 514 _ 2 , 514 _ 3 , and 514 _ 4 as electric field generating electrodes may have shapes corresponding to the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the pixels may be easily divided.
  • domains in the first and second pixel regions PA 1 and PA 2 may be formed in different directions, thereby improving a viewing angle, visibility and an aperture ratio.
  • FIG. 10 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 600 of FIG. 10 may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 600 may be substantially the same as the display panel 100 illustrated in FIGS. 3A and 3B , except for at least one element of a display substrate 610 .
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 610 may include an insulating substrate, a plurality of signal lines, and electric field generating electrodes for forming an electric field.
  • the plurality of signal lines and the electric field generating electrodes may be formed on the insulating substrate.
  • the display substrate 610 may further include switching elements SW 1 , SW 2 , SW 3 , and SW 4 for controlling an operation of the electric field generating electrodes, and a first alignment layer for initially aligning the liquid crystal molecules.
  • the insulating substrate may have a first pixel region PA 1 , a second pixel region PA 2 , a third pixel region PA 3 , and a fourth pixel region PA 4 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the signal lines may include first and second gate lines GL 1 and GL 2 and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2 .
  • the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 , and the first and second data lines DL 1 and DL 2 may be bent at least once in a region between two adjacent pixel regions PX 1 and PX 3 .
  • a first lower electrode 613 _ 1 , a second lower electrode 613 _ 2 , a third lower electrode 613 _ 3 , and a fourth lower electrode 613 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • a first upper electrode 614 _ 1 , a second upper electrode 614 _ 2 , a third upper electrode 614 _ 3 , and a fourth upper electrode 514 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 and PA 4 , respectively.
  • the first to fourth upper electrodes 614 _ 1 , 614 _ 2 , 614 _ 3 , and 614 _ 4 may overlap the first to fourth lower electrodes 613 _ 1 , 613 _ 2 , 613 _ 3 , and 613 _ 4 , respectively.
  • the first to fourth upper electrodes 614 _ 1 ′, 614 _ 2 , 614 _ 3 , and 614 _ 4 may have a first slit pattern 615 _ 1 , a second slit pattern 615 _ 2 , a third slit pattern 615 _ 3 and fourth slit pattern 615 _ 4 , respectively.
  • the first slit pattern 615 _ 1 may include an extension portion extending in a third direction different from the first and second directions D 1 and D 2 , and an extension portion extending in a fourth direction different from the first and second directions D 1 and D 2 and the third direction.
  • the first slit pattern 615 _ 1 may sequentially extend in the third direction, and in the fourth direction toward the first direction D 1 .
  • the first slit pattern 615 _ 1 may include a first extension portion extending in the third direction, a second extension portion extending in the fourth direction, and a curved portion between the first and second extension portions.
  • the third and fourth directions may be symmetric with respect to the second direction D 2 .
  • the second slit pattern 615 _ 2 may include extension portions extending in the fourth direction and the third direction.
  • the second slit pattern 615 _ 2 may sequentially extend in the fourth direction, and in the third direction toward the first direction D 1 .
  • the second slit pattern 615 _ 2 may have a curved structure opposite to the first slit pattern 615 _ 1
  • the third slit pattern 615 _ 3 may have a structure in parallel with the first slit pattern 615 _ 1
  • the fourth slit pattern 615 _ 4 may have a structure in parallel with the second slit pattern 615 _ 2 .
  • the third and fourth slit patterns 615 _ 3 and 615 _ 4 may have the same structure as the first and second slit patterns 615 _ 1 and 615 _ 2 , respectively.
  • the first slit pattern 615 _ 1 may include a first curved portion 615 _ 1 a located at a first edge portion of the first slit pattern 615 _ 1 , and a second curved portion 615 _ 1 b located at a second edge portion of the first slit pattern 615 _ 1 .
  • the first curved portion 615 _ 1 a may have an inclined angle that is smaller than an angle between the second direction D 2 and the third direction
  • the second curved portion 615 _ 1 b may have an inclined angle that is smaller than an angle between the second direction D 2 and the fourth direction.
  • the second slit pattern 615 _ 2 may include a third curved portion 615 _ 2 a located at a first edge portion of the second slit pattern 615 _ 2 and a fourth curved portion 615 _ 2 b located at a second edge portion of the second slit pattern 615 _ 2 .
  • the third curved portion 615 _ 2 a may have an inclined angle that is smaller than an angle between the second direction D 2 and the third direction
  • the fourth curved portion 615 _ 2 b may have an inclined angle that is smaller than an angle between the second direction D 2 and the fourth direction.
  • the first edge portion of the first slit pattern 615 _ 1 in which the first curved portion 615 _ 1 a is formed may be opposite to the first edge portion of the second slit pattern 615 _ 2 in which the second curved portion 615 _ 2 a is formed. That is, the first edge portions of the first and second slit patterns 615 _ 1 and 615 _ 2 may be distal edge portions of the first and second slit patterns 615 _ 1 and 615 _ 2 .
  • An edge portion of the third slit pattern 615 _ 3 may include a fifth curved portion 615 _ 3 a
  • the other edge portion of the third slit pattern 615 _ 3 may include a sixth curved portion 615 _ 3 b
  • the fifth and sixth curved portions 615 _ 3 a and 615 _ 3 b may be substantially the same as the first and second curved portions 615 _ 1 a and 615 _ 1 b.
  • An edge portion of the fourth slit pattern 615 _ 4 may include a seventh curved portion 615 _ 4 a
  • the other edge portion of the fourth slit pattern 615 _ 4 may include an eighth curved portion 615 _ 4 b
  • the seventh and eighth curved portions 615 _ 4 a and 615 _ 4 b may be substantially the same as the third and fourth curved portions 615 _ 2 a and 615 _ 2 b.
  • the first upper electrode 614 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the first switching element SW 1 may be electrically coupled to the first gate line GL 1 and the second data line DL 2 .
  • the second upper electrode 614 _ 2 may be electrically coupled to the second switching element SW 2 .
  • the second switching element SW 2 may be coupled to the second gate line GL 2 and the first data line DL 1 .
  • the first and second switching elements SW 1 and SW 2 are coupled to the different data lines DL 1 and DL 2 .
  • the first switching element SW 1 may be located at the right region of the first pixel region PA 1 adjacent to the second data line DL 2
  • the second switching element SW 2 may be located at the left region of the second pixel region PA 2 adjacent to the first data line DL 1 .
  • the third and fourth upper electrodes 614 _ 3 and 614 _ 4 may be electrically coupled to third and fourth switching elements SW 3 and SW 4 .
  • the third and fourth switching elements SW 3 and SW 4 may have substantially the same structure as the first and second switching elements SW 1 and SW 2 .
  • the first and second pixel regions PA 1 and PA 2 may be located between the first and second data lines DL 1 and DL 2 .
  • Each of the first and second data lines DL 1 and DL 2 may include a first extension portion in parallel with the first slit pattern 615 _ 1 , and a second extension portion in parallel with the second slit pattern 615 _ 2 .
  • each of the first and second data lines DL 1 and DL 2 may have a zigzag structure.
  • each of the first and second pixel regions PA 1 and PA 2 may form double domains, and the domains of the first and second pixel regions PA 1 and PA 2 may be symmetrical to each other with respect to the first gate line GL 1 . Accordingly, a viewing angle, visibility and an aperture ratio may be improved.
  • FIG. 11A is a plan view illustrating a display panel in accordance with example embodiments.
  • FIG. 11B is a cross-sectional view of an example embodiment of a display panel taken along a line II-II′ of FIG. 11A .
  • a display panel 700 of FIGS. 11A and 11B may be included in the display device 10 illustrated in FIGS. 1 and 2 or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 700 may be substantially the same as the display panel 100 illustrated in FIGS. 3A and 3B , except for at least one element of a display substrate 710 .
  • lower electrodes may be electrically coupled to switching elements.
  • a display panel 700 includes a display substrate 710 , an opposing substrate 720 and a liquid crystal layer 730 .
  • the opposing substrate 720 may face the display substrate 710 , and the liquid crystal layer 730 may be interposed between the display substrate 710 and the opposing substrate 720 .
  • the display panel 700 may further include a first polarizing plate 702 and a second polarizing plate 704 .
  • the display substrate 710 may include an insulating substrate 711 , a plurality of signal lines and electric field generating electrodes for forming an electric field.
  • the display substrate 710 may further include switching elements SW 1 , SW 2 , SW 3 , and SW 4 for controlling an operation of the electric field generating electrodes, and a first alignment layer 712 for initially aligning the liquid crystal molecules.
  • the insulating substrate 711 may include,first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the signal lines may include first and second gate lines GL 1 and GL 2 and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2
  • the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 .
  • the display substrate 710 may include first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 and first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 .
  • the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 may be insulated from the first and second gate lines GL 1 and GL 2 by forming a gate insulating layer 717 between the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 , and the first and second gate lines GL 1 and GL 2 .
  • the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 may not overlap adjacent signal lines. In this case, sides of the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 may be spaced apart from the signal lines (e.g., spaced apart by a predetermined distance). In other example embodiments, the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 may partially overlap adjacent gate lines to form a storage capacitor.
  • storage electrodes may be formed to overlap the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 .
  • the storage electrodes may be electrically coupled to a storage line that is in parallel with a gate line, and may be formed in a metal layer including the gate line.
  • the first lower electrode 713 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the first switching element SW 1 may be electrically coupled to the first gate line GL 1 and the first data line DL 1 .
  • the first lower electrode 713 _ 1 may be a pixel electrode for receiving a pixel voltage from the first data line DL 1 according to a switching operation of the first switching element SW 1 .
  • the second lower electrode 713 _ 2 may be electrically coupled to the second switching element SW 2 .
  • the second switching element SW 2 may be electrically coupled to the second gate line GL 2 and the first data line DL 1 .
  • the second lower electrode 713 _ 2 may be a pixel electrode for receiving a pixel voltage from the first data line DL 1 according to a switching operation of the second switching element SW 2 .
  • the third and fourth lower electrodes 713 _ 3 and 714 _ 4 may be electrically coupled to the second data line DL 2 through the third and fourth switching elements SW 3 and SW 4 , respectively.
  • Each of the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 may have a plate shape.
  • the first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 may overlap the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 , respectively.
  • a first passivation layer 718 may be located between the first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 , and the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 to insulate the first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 from the first to fourth lower electrodes 713 _ 1 , 713 _ 2 , 713 _ 3 , and 713 _ 4 .
  • the first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 may have first to fourth slit patterns 715 _ 1 , 715 _ 2 , 715 _ 3 , and 715 _ 4 , respectively.
  • the first to fourth slit patterns 715 _ 1 , 715 _ 2 , 715 _ 3 , and 715 _ 4 may form the domain of the liquid crystal.
  • the first to fourth slit patterns 715 _ 1 , 715 _ 2 , 715 _ 3 , and 715 _ 4 may be substantially the same as the first to fourth slit patterns 115 _ 1 , 115 _ 2 , 115 _ 3 , and 115 _ 4 illustrated in FIGS. 3A and 3B .
  • Each of the first and fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 may be a common electrode for receiving a common voltage.
  • the first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 may have a stripe structure such that the first and second upper electrodes 714 _ 1 and 714 _ 2 may have an integral structure and the third and fourth upper electrodes 714 _ 3 and 714 _ 4 may have an integral structure.
  • first through fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 may have an entirely integral structure.
  • first through fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 may have a separate structure (e.g., an island structure) where the common voltage is applied through separate common electrode lines.
  • the display panel 700 may form the domain of the liquid crystal using the first to fourth slit patterns 715 _ 1 , 715 _ 2 , 715 _ 3 , and 715 _ 4 formed in the first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 .
  • a single domain may be formed in each pixel region, and the domains of adjacent pixel regions located in the first direction D 1 may have different directions (e.g., symmetrical directions with respect to the second direction D 2 ). Accordingly, the display panel 700 according to example embodiments may form at least two single domains having different directions, thereby improving an aperture ratio, a viewing angle and visibility
  • the first alignment layer 712 may be formed on the first insulating layer 711 on which the first to fourth upper electrodes 714 _ 1 , 714 _ 2 , 714 _ 3 , and 714 _ 4 are formed.
  • the first alignment layer 712 in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may be treated to have a single alignment direction such that a surface alignment of the first alignment layer 712 is substantially the same with respect to the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 when viewed from the top.
  • An alignment direction of the first alignment layer 712 may be defined as a direction in which the first alignment layer 712 arranges the liquid crystal molecules LC.
  • the alignment direction of the first alignment layer 712 may be the first direction D 1 or the second direction D 2 .
  • the first alignment layer 712 may be formed on a surface of the first insulating substrate 711 adjacent to the liquid crystal layer 730 .
  • the opposing substrate 720 may include a second insulating layer 721 , a light-blocking pattern BM, and color filters CF.
  • the light-blocking pattern BM and the color filters may be formed on the second insulating substrate 721 .
  • the opposing substrate 720 may further include a second alignment layer 722 for initially aligning the liquid crystal molecules LC.
  • the light-blocking pattern BM may overlap the switching elements SW 1 , SW 2 , SW 3 , and SW 4 , and the signal lines GL 1 , GL 2 , DL 1 , and DL 2 of the display substrate 710
  • the color filters CF may overlap the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 of the display substrate 710 , respectively.
  • Each of the color filters CF may be one of three color filters.
  • the color filters CF may include a white color filter (or a transparent filter) as well as the three color filters.
  • the second alignment layer 722 may face the first display substrate 710 , and may be located on a surface of the second insulating substrate 721 adjacent to the liquid crystal layer 730 .
  • the second alignment layer 722 may be treated to have a single alignment direction such that a surface alignment of the second alignment layer 722 is substantially the same in the regions corresponding to the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 when viewed from the top.
  • the second alignment layer 722 may have an alignment direction by a rubbing treatment or a photo alignment treatment.
  • the alignment direction of the second alignment layer 722 may be substantially the same as the alignment direction of the first alignment layer 712 .
  • the first polarizing plate 702 may be located on a lower surface of the display substrate 710 , for example, an opposing surface of the first insulating substrate 711 , to a surface adjacent to the liquid crystal layer 730 .
  • the first polarizing plate 702 may have a polarizing axis that is substantially the same as the alignment direction of the first alignment layer 712 included in the display substrate 710 .
  • the second polarizing plate 704 may be located on an upper surface of the opposing substrate 720 , for example, an opposing surface of the second insulating substrate 721 , to a surface adjacent to the liquid crystal layer 730 .
  • a polarizing axis of the second polarizing plate 704 may be substantially perpendicular to the polarizing axis of the first polarizing plate 702 .
  • FIG. 12 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 800 of FIG. 12 may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 800 may be substantially the same as the display panel 700 illustrated in FIGS. 11A and 11B , except for a display substrate 810 .
  • the display substrate 810 illustrated in FIG. 12 may be substantially the same as the display substrate 710 illustrated in FIGS. 11A and 11B , except for a structure of a slit pattern in each upper electrode.
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 810 includes an insulating substrate, a plurality of signal lines, electric field generating electrodes, a plurality of switching elements SW 1 , SW 2 , SW 3 , and SW 4 , and a first alignment layer.
  • the insulating substrate may include first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the signal lines may include first and second gate lines GL 1 and GL 2 , and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2
  • the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 .
  • the display substrate 810 may include first to fourth lower electrodes 813 _ 1 , 813 _ 2 , 813 _ 3 , and 813 _ 4 , and first to fourth upper electrodes 814 _ 1 , 814 _ 2 , 814 _ 3 , and 814 _ 4 .
  • the first to fourth lower electrodes 813 _ 1 , 813 _ 2 , 813 _ 3 , and 813 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrode 814 _ 1 , 814 _ 2 , 814 _ 3 , and 814 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrodes 814 _ 1 , 814 _ 2 , 814 _ 3 , and 814 _ 4 may overlap the first to fourth lower electrodes 813 _ 1 , 813 _ 2 , 813 _ 3 , and 813 _ 4 , respectively.
  • the first lower electrode 813 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the first switching element SW 1 may be electrically coupled to the first gate line GL 1 and the first data line DL 1 .
  • the first lower electrode 813 _ 1 may be a pixel electrode for receiving a pixel voltage.
  • the second lower electrode 813 _ 2 may be electrically coupled to the second switching element SW 2 .
  • the second switching element SW 2 may be electrically coupled to the second gate line GL 2 and the first data line DL 1 .
  • the second lower electrode 813 _ 2 may be a pixel electrode for receiving a pixel voltage.
  • Each of third and fourth lower electrodes 813 _ 3 and 813 _ 4 may be electrically coupled to the second data line DL 2 through the third and fourth switching elements SW 3 and SW 4 .
  • Each of the third and fourth lower electrodes 813 _ 3 and 813 _ 4 may be a pixel electrode for receiving a pixel voltage.
  • the first to fourth upper electrodes 814 _ 1 , 814 _ 2 , 814 _ 3 , and 814 _ 4 have the first to fourth slit patterns 815 _ 1 , 815 _ 2 , 815 _ 3 , and 815 _ 4 for forming the domain of the liquid crystal, respectively.
  • the first to fourth slit patterns 815 _ 1 , 815 _ 2 , 815 _ 3 , and 815 _ 4 may be substantially the same as the first to fourth slit patterns 315 _ 1 , 315 _ 2 , 315 _ 3 , and 315 _ 4 illustrated in FIG. 7 .
  • Each of the first through fourth upper electrodes 814 _ 1 , 814 _ 2 , 814 _ 3 , and 814 _ 4 may be a common electrode for receiving a common voltage.
  • the first through fourth upper electrodes 814 _ 1 , 814 _ 2 , 814 _ 3 , and 814 _ 4 may have a stripe structure, an integral structure, a separate structure, etc.
  • FIG. 13 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel of FIG. 13 may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 900 may be substantially the same as the display panel 700 illustrated in FIGS. 11A and 11B , except for a display substrate 910 .
  • the display substrate 910 in FIG. 13 may be substantially the same as the display substrate 710 illustrated in FIGS. 11A and 11B , except for a structure of a slit pattern in each upper electrode and an arrangement of switching elements.
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 910 may include an insulating substrate, a plurality of signal lines, electric field generating electrodes, a plurality of switching elements SW 1 , SW 2 , SW 3 , and SW 4 , and a first alignment layer.
  • the insulating substrate may include first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • thefourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the signal lines may include first and second gate lines GL 1 and GL 2 , and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2 , and the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 .
  • the first and second data lines DL 1 and DL 2 may be in parallel with each other, and the first and second pixel regions PA 1 and PA 2 may be located between the first and second data lines DL 1 and DL 2 .
  • the display substrate 910 may include first to fourth lower electrodes 913 _ 1 , 913 _ 2 , 9133 , and 913 _ 4 , and first to fourth upper electrodes 914 _ 1 , 914 _ 2 , 914 _ 3 , and 914 _ 4 .
  • the first to fourth lower electrodes 913 _ 1 , 913 _ 2 , 913 _ 3 , and 913 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrode 914 _ 1 , 9142 , 914 _ 3 , and 914 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrodes 914 _ 1 , 914 _ 2 , 914 _ 3 , and 914 _ 4 may overlap the first to fourth lower electrodes 913 _ 1 , 9132 , 913 _ 3 , and 913 _ 4 , respectively.
  • the first lower electrode 913 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the first switching element SW 1 may be electrically coupled to the first gate line GL 1 and the second data line DL 2 .
  • the first lower electrode 913 _ 1 may be a pixel electrode for receiving a pixel voltage.
  • the second lower electrode 913 _ 2 may be electrically coupled to the second switching element SW 2 .
  • the second switching element SW 2 may be electrically coupled to the second gate line GL 2 and the first data line DL 1 .
  • the second lower electrode 913 _ 2 may be a pixel electrode for receiving a pixel voltage.
  • the first and second switching elements SW 1 and SW 2 may be coupled to the different data lines DL 1 and DL 2 .
  • the first switching element SW 1 may be located adjacently to the second data line DL 2
  • the second switching element SW 2 may be located adjacently to the first data line DL 1 .
  • an arrangement of the first and second switching elements SW 1 and SW 2 may be symmetric.
  • the third and fourth lower electrodes 913 _ 3 and 913 _ 4 may be electrically coupled to the third and fourth switching elements SW 3 and SW 4 .
  • the third and fourth switching elements SW 3 and SW 4 may have substantially the same structure as the first and second switching elements SW 1 and SW 2 .
  • the first to fourth upper electrodes 914 _ 1 , 914 _ 2 , 914 _ 3 , and 914 _ 4 may have first to fourth slit patterns 915 _ 1 , 915 _ 2 , 915 _ 3 , and 915 _ 4 , respectively.
  • the first to fourth slit patterns 915 _ 1 , 915 _ 2 , 915 _ 3 , and 915 _ 4 may be substantially the same as the first to fourth slit patterns 415 _ 1 , 415 _ 2 , 415 _ 3 , and 415 _ 4 illustrated in FIG. 8 .
  • Each of the first to fourth upper electrodes 914 _ 1 , 914 _ 2 , 914 _ 3 , and 914 _ 4 may be a common electrode for receiving a common voltage.
  • the first and fourth upper electrodes 914 _ 1 , 914 _ 2 , 914 _ 3 , and 914 _ 4 may have a stripe structure, an integral structure, a separate structure, etc.
  • FIG. 14 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 1000 of FIG. 14 may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 1000 may be substantially the same as the display panel 700 illustrated in FIGS. 11A and 11B , except for at least one element of a display substrate 1010 .
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 1010 may include an insulating substrate, a plurality of signal lines, electric field generating electrodes, a plurality of switching elements SW 1 , SW 2 , SW 3 , and SW 4 , and a first alignment layer.
  • the insulating substrate may include first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may have rectangular shapes, respectively.
  • the signal lines may include first and second gate lines GL 1 and GL 2 , and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2
  • the first and second data lines DL 1 and DL 2 may extend in the first direction D 1 .
  • the first and second data lines DL 1 and DL 2 may extend in a straight line shape along the first direction D 1 , and may be in parallel with each other.
  • the first and second pixel regions PA 1 and PA 2 may be located between the first and second data lines DL 1 and DL 2 .
  • the display substrate 1010 may include first to fourth lower electrodes 1013 _ 1 , 1013 _ 2 , 1013 _ 3 , and 1013 _ 4 , and first to fourth upper electrodes 1014 _ 1 , 1014 _ 2 , 1014 _ 3 , and 1014 _ 4 .
  • the first to fourth lower electrodes 1013 _ 1 , 1013 _ 2 , 1013 _ 3 , and 1013 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrode 1014 _ 1 , 1014 _ 2 , 1014 _ 3 , and 1014 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrodes 1014 _ 1 , 1014 _ 2 , 1014 _ 3 , and 1014 _ 4 may overlap the first to fourth lower electrodes 1013 _ 1 , 1013 _ 2 , 1013 _ 3 , and 1013 _ 4 , respectively.
  • the first to fourth upper electrodes 1014 _ 1 , 1014 _ 2 , 1014 _ 3 , and 1014 _ 4 may have first to fourth slit patterns 1015 _ 1 , 10152 , 10153 , and 1015 _ 4 , respectively.
  • the first to fourth slit patterns 1015 _ 1 , 10152 , 1015 _ 3 , and 1015 _ 4 may be substantially the same as the first to fourth slit patterns 515 _ 1 , 515 _ 2 , 515 _ 3 , and 515 _ 4 illustrated in FIG. 9 .
  • the first lower electrode 1013 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the first switching element SW 1 may be electrically coupled to the first gate line GL 1 and the second data line DL 2 .
  • the first lower electrode 1013 _ 1 may be a pixel electrode for receiving a pixel voltage.
  • the second lower electrode 1013 _ 2 may be electrically coupled to the second switching element SW 2 .
  • the second switching element SW 2 may be electrically coupled to the second gate line GL 2 and the first data line DL 1 .
  • the second lower electrode 1013 _ 2 may be a pixel electrode for receiving a pixel voltage.
  • the first switching element SW 1 may be located adjacently to the second data line DL 2
  • the second switching element SW 2 may be located adjacently to the first data line DL 1 .
  • an arrangement of the first and second switching elements SW 1 and SW 2 may be symmetric.
  • the third and fourth lower electrodes 1013 _ 3 and 1013 _ 4 may be electrically coupled to the third and fourth switching elements SW 3 and SW 4 .
  • the third and fourth switching elements SW 3 and SW 4 may have substantially the same structure as the first and second switching elements SW 1 and SW 2 .
  • first to fourth upper electrodes 1014 _ 1 , 1014 _ 2 , 1014 _ 3 , and 1014 _ 4 may have first to fourth slit patterns 1015 _ 1 , 1015 _ 2 , 1015 _ 3 , and 1015 _ 4 that extend in the third and fourth directions
  • sides of the first to fourth upper electrodes 1014 _ 1 , 1014 _ 2 , 1014 _ 3 , and 1014 _ 4 that are adjacent to the first and second data lines DL 1 and DL 2 may extend in parallel with the first and second data lines DL 1 and DL 2 .
  • each of the first to fourth upper electrodes 1014 _ 1 , 1014 _ 2 , 1014 _ 3 , and 1014 _ 4 may have a rectangular shape.
  • FIG. 15 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 1100 of FIG. 15 may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 1100 may be substantially the same as the display panel 700 illustrated in FIGS. 11A and 11B , except for partial elements of a display substrate 1110 .
  • differences will be briefly described hereinafter, and any repetitive descriptions may be omitted.
  • a display substrate 1110 may include an insulating substrate, a plurality of signal lines, electric field generating electrodes, a plurality of switching elements SW 1 , SW 2 , SW 3 , and SW 4 , and a first alignment layer.
  • the insulating substrate may include first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the second pixel region PA 2 may be located in a first direction D 1 from the first pixel region PA 1 .
  • the third pixel region PA 3 may be located in a second direction D 2 from the first pixel region PA 1
  • the fourth pixel region PA 4 may be located in the second direction D 2 from the second pixel region PA 2 .
  • the signal lines may include first and second gate lines GL 1 and GL 2 , and first and second data lines DL 1 and DL 2 .
  • the data lines DL 1 and DL 2 may cross the gate lines GL 1 and GL 2 .
  • the first and second gate lines GL 1 and GL 2 may extend in the second direction D 2 , and the first gate line GL 1 may be located between the first and second pixel regions PA 1 and PA 2 .
  • the first and second data lines DL 1 and DL 2 may extend in a zigzag shape along the first direction D 1 , and the first and second data lines DL 1 and DL 2 may be bent at least once in a region between two adjacent pixel regions PX 1 and PX 3 .
  • the display substrate 1110 may include first to fourth lower electrodes 1113 _ 1 , 1113 _ 2 , 1113 _ 3 , and 1113 _ 4 , and first to fourth upper electrodes 1114 _ 1 , 1114 _ 2 , 1114 _ 3 , and 1114 _ 4 .
  • the first to fourth lower electrodes 1113 _ 1 , 1113 _ 2 , 1113 _ 3 , and 1113 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrode 1114 _ 1 , 1114 _ 2 , 1114 _ 3 , and 1114 _ 4 may be formed in the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the first to fourth upper electrodes 1114 _ 1 , 1114 _ 2 , 1114 _ 3 , and 1114 _ 4 may overlap the first to fourth lower electrodes 1113 _ 1 , 1113 _ 2 , 1113 _ 3 , and 1113 _ 4 , respectively.
  • the first to fourth upper electrodes 1114 _ 1 , 1114 _ 2 , 1114 _ 3 , and 1114 _ 4 may have first to fourth slit patterns 1115 _ 1 , 1115 _ 2 , 1115 _ 3 , and 1115 _ 4 , respectively.
  • the first to fourth slit patterns 1115 _ 1 , 1115 _ 2 , 1115 _ 3 , and 1115 _ 4 may be substantially the same as the first to fourth slit patterns 615 _ 1 , 615 _ 2 , 615 _ 3 , and 615 _ 4 illustrated in FIG. 10 .
  • the first lower electrode 113 _ 1 may be electrically coupled to the first switching element SW 1 .
  • the first switching element SW 1 may be electrically coupled to the first gate line GL 1 and the second data line DL 2 .
  • the first lower electrode 113 _ 1 may be a pixel electrode for receiving a pixel voltage.
  • the second lower electrode 113 _ 2 may be electrically coupled to the second switching element SW 2 .
  • the second switching element SW 2 may be electrically coupled to the second gate line GL 2 and the first data line DL 1 .
  • the second lower electrode 113 _ 2 may be a pixel electrode for receiving a pixel voltage.
  • the first and second switching elements SW 1 and SW 2 may be coupled to the different data lines DL 1 and DL 2 .
  • the first switching element SW 1 may be located adjacently to the second data line DL 2
  • the second switching element SW 2 may be located adjacently to the first data line DL 1 .
  • an arrangement of the first and second switching elements SW 1 and SW 2 may be symmetric.
  • the third and fourth lower electrodes 1113 _ 3 and 1113 _ 4 may be electrically coupled to the third and fourth switching elements SW 3 and SW 4 .
  • the third and fourth switching elements SW 3 and SW 4 may have substantially the same structure as the first and second switching elements SW 1 and SW 2 .
  • Shapes of the first and second data lines DL 1 and DL 2 may be substantially the same as those of the first and second data lines DL 1 and DL 2 illustrated in FIG. 10 .
  • FIG. 16A is a block diagram illustrating a display panel in accordance with example embodiments.
  • FIG. 16B is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 1200 may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 1200 may be substantially the same as the display panel 100 illustrated in FIGS. 3A and 3B , except for a display substrate 1210 .
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • the display panel 1200 may include a display substrate 1210 (or a lower substrate), an opposing substrate (or an upper substrate), and a liquid crystal layer.
  • the opposing substrate faces the display substrate 1210 .
  • the liquid crystal layer is interposed between the display substrate 1210 and the opposing substrate
  • the display panel 1200 may include a plurality of pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 , and a plurality of signal lines GL 1 , GL 2 , GL 3 , GL 4 , DL 1 , DL 2 , and DL 3 , coupled to the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 .
  • the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 may be arranged in a matrix form.
  • first to fourth pixels PX 1 , PX 2 , PX 3 , and PX 4 may be arranged in a first direction D 1 .
  • the first direction D 1 may be a vertical direction (or a column direction).
  • Fifth to eighth pixels PX 5 , PX 6 , PX 7 , and PX 8 may be located in a second direction D 2 from the first to fourth pixels PX 1 , PX 2 , PX 3 , and PX 4 , respectively.
  • the second direction D 2 may be a horizontal direction (or a row direction).
  • Each of the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 may include a pair of electric field generating electrodes and the liquid crystal layer formed on the display substrate 1210 .
  • the first pixel PX 1 may include, as the pair of electric field generating electrodes, a first lower electrode 1213 _ 1 and a first upper electrode 1214 _ 1 overlapping the first lower electrode 1213 _ 1 .
  • the first upper electrode 1214 _ 1 may include a first slit pattern 1215 _ 1 for forming the domain.
  • Each of the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 may form the domain using a slit pattern formed in a corresponding upper electrode.
  • the first and second pixels PX 1 and PX 2 may have different domains.
  • the domains of the first and second pixels PX 1 and PX 2 may be symmetric with respect to the second direction D 2 .
  • the third and fourth pixels PX 3 and PX 4 may have different domains.
  • the domains of the third and fourth pixels PX 3 and PX 4 may be symmetric with respect to the second direction D 2 .
  • the fifth and sixth pixels PX 5 and PX 6 may have different domains.
  • the domains of the fifth and sixth pixels PX 5 and PX 6 may be symmetric with respect to the second direction D 2 .
  • the seventh and eighth pixels PX 7 and PX 8 may have different domains.
  • the domains of the seventh and eighth pixels PX 7 and PX 8 may be symmetric with respect to the second direction D 2 .
  • the first, third, fifth and seventh pixels PX 1 , PX 3 , PX 5 , and PX 7 may have the same domain
  • the second, fourth , sixth, and eighth pixels PX 2 , PX 4 , PX 6 , and PX 8 may have the same domain.
  • adjacent pixels located along the second direction D 2 may have the same domain
  • adjacent pixels located along the first direction D 1 may have different domains.
  • the signal lines GL 1 , GL 2 , GL 3 , GL 4 , DL 1 , DL 2 , and DL 3 may include first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 , and first to third data lines DL 1 , DL 2 , and DL 3 crossing the gate lines GL 1 , GL 2 , GL 3 , and GL 4 .
  • the signal lines GL 1 , GL 2 , GL 3 , GL 4 , DL 1 , DL 2 , and DL 3 may be coupled to the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 .
  • each of the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 may be coupled to a corresponding one of the gate lines GL 1 , GL 2 , GL 3 , and GL 4 and a corresponding one of the data lines DL 1 , DL 2 , and DL 3 .
  • the display substrate 1210 may include an insulating layer, the signal lines GL 1 , GL 2 , GL 3 , GL 4 , DL 1 , DL 2 , and DL 3 , the electric field generating electrodes, a plurality of switching elements, and a first alignment layer.
  • the insulating substrate may include first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 .
  • the first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 may be arranged in a form substantially the same as a form in which the first to eighth pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 are arranged.
  • the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may be arranged in the first direction D 1 .
  • the fifth to eighth pixel regions PA 5 , PA 6 , PA 7 , and PA 8 may be located in the second direction D 2 from the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 may extend in the second direction D 2 , and may be arranged in parallel with each other.
  • the first and second pixel regions PA 1 and PA 2 may be located between the first and second gate lines GL 1 and GL 2
  • the fifth and sixth pixel regions PA 5 and PA 6 may be located between the first and second gate lines GL 1 and GL 2 .
  • the first gate line GL 1 may be located adjacently to edge portions (e.g., upper edge portions) of the first and fifth pixel regions PA 1 and PA 5
  • the second gate line GL 2 may be located adjacently to edge portions (e.g., lower edge portions) of the second and sixth pixel regions PA 2 and PA 6
  • the second gate line GL 2 may be located between the second and third pixel regions PA 2 and PA 3 , and between the sixth and seventh pixel regions PA 6 and PA 7
  • the third and fourth pixel regions PA 3 and PA 4 may be located between the third and fourth gate lines GL 3 and GL 4
  • the seventh and eighth pixel regions PA 7 and PA 8 may be located between the third and fourth gate lines GL 3 and GL 4 .
  • the third gate line GL 3 may be located adjacently to edge portions (e.g., upper edge portions) of the third and sixth pixel regions PA 3 and PA 7
  • the fourth gate line GL 4 may be located adjacently to edge portions (e.g., lower edge portions) of the fourth and eighth pixel regions PA 4 and PA 8
  • the third gate line GL 3 may be located between the second and third pixel regions PA 2 and PA 3 , and between the sixth and seventh pixel regions PA 6 and PA 7 .
  • no gate line may be located between the first and second pixel regions PA 1 and PA 2 , and between the first and sixth pixel regions PA 5 and PA 6
  • two gate lines GL 2 and GL 3 may be located between the second and third pixel regions PA 2 and PA 3 , and between the sixth and seventh pixel regions PA 6 and PA 7 .
  • two gate lines may be located in every other pixel region along the first direction D 1 .
  • the first to third data lines DL 1 , DL 2 , and DL 3 may extend in the first direction D 1 , and may be arranged in parallel with each other.
  • each of the first to third data lines DL 1 , DL 2 , and DL 3 may be located in an edge portion (e.g., a left edge portion or a right edge portion) of the corresponding pixel region.
  • the electric field generating electrodes may include first to eighth lower electrodes 1213 _ 1 , 1213 _ 2 , 1213 _ 3 , 12134 , 1213 _ 5 , 1213 _ 6 , 1213 _ 7 , and 1213 _ 8 , and first to eighth upper electrodes 1214 _ 1 , 1214 _ 2 , 1214 _ 3 , 1214 _ 4 , 1214 _ 5 , 1214 _ 6 , 1214 _ 7 , and 1214 _ 8 .
  • the first to eighth lower electrodes 1213 _ 1 , 1213 _ 2 , 1213 _ 3 , 1213 _ 4 , 1213 _ 5 , 1213 _ 6 , 1213 _ 7 , and 1213 _ 8 may be formed in the first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 , respectively.
  • the first to eighth upper electrodes 1214 _ 1 , 1214 _ 2 , 1214 _ 3 , 1214 _ 4 , 1214 _ 5 , 1214 _ 6 , 1214 _ 7 , and 1214 _ 8 may be formed to overlap the first to eighth lower electrodes 1213 _ 1 , 1213 _ 2 , 1213 _ 3 , 1213 _ 4 , 12135 , 1213 _ 6 , 1213 _ 7 , and 1213 _ 8 in the first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 , respectively.
  • the first to eighth upper electrodes 1214 _ 1 , 1214 _ 2 , 1214 _ 3 , 1214 _ 4 , 1214 _ 5 , 1214 _ 6 , 1214 _ 7 , and 1214 _ 8 may have first to eighth silt patterns 1215 _ 1 , 1215 _ 2 , 1215 _ 3 , 1215 _ 4 , 1215 _ 5 , 1215 _ 6 , 1215 _ 7 , and 1215 _ 8 , respectively.
  • the first, third, fifth and seventh silt patterns 1215 _ 1 , 12153 , 1215 _ 5 , and 1215 _ 7 may extend in a third direction that is different from the first and second directions D 1 and D 2 .
  • the second, fourth, sixth and eighth silt patterns 1215 _ 2 , 1215 _ 4 , 1215 _ 6 , and 1215 _ 8 may extend in a fourth direction that is different from the first and second directions D 1 and D 2 , and the third direction.
  • the third and fourth directions may be symmetric with respect to the second direction D 2 .
  • the first to eighth upper electrodes 1214 _ 1 , 1214 _ 2 , 1214 _ 3 , 1214 _ 4 , 1214 _ 5 , 1214 _ 6 , 1214 _ 7 , and 1214 _ 8 may be coupled to the signal lines through the first to eighth switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 .
  • the first to eighth upper electrodes 1214 _ 1 , 1214 _ 2 , 1214 _ 3 , 1214 _ 4 , 1214 _ 5 , 1214 _ 6 , 1214 _ 7 , and 1214 _ 8 may be pixel electrodes for receiving pixel voltages.
  • the first to fourth switching elements SW 1 , SW 2 , SW 3 , and SW 4 may be electrically coupled to the first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 , respectively, and may be coupled to the first data line DL 1 .
  • the fifth to eighth switching elements SW 5 , SW 6 , SW 7 , and SW 8 may be electrically coupled to the first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 , respectively, and may be coupled to the second data line DL 2 .
  • the first to eighth switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 may be located adjacently to the signal lines.
  • the data lines, the lower electrodes, the upper electrodes, and slit patterns of the display substrate 1210 may be substantially similar to those of the display substrates 310 , 410 , 510 , and 610 illustrated in FIGS. 7 to 10 .
  • the opposing substrate may include a light-blocking pattern, color filters, and a second alignment layer.
  • FIG. 17 is a plan view illustrating a light-blocking pattern of an opposing substrate included in the display panel of FIG. 16B .
  • a light-blocking pattern BM may be formed to overlap signal lines GL 1 , GL 2 , GL 3 , GL 4 , DL 1 , DL 2 , and DL 3 , and switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 .
  • the light-blocking pattern BM may have a width dl that is narrower than that of an object where incident light is to be blocked.
  • the width dl of the light-blocking pattern BM may be narrower than a width d 2 of a gate pattern including gate lines GL and switching elements SW.
  • the width dl of the light-blocking pattern BM between the second and third pixel regions PA 2 and PA 3 may be narrower than the width d 2 of a gate pattern including the second and third gate lines GL 2 and GL 3 , and the second and third switching elements SW 2 and SW 3 .
  • the width d 2 of the gate pattern may be defined as a distance from a distant end of the second switching element SW 2 to a distant end of the third switching element SW 3 .
  • the light-blocking pattern BM may be formed to have a width that is narrower than that of the gate pattern, a sufficient alignment margin may be obtained between the display substrate 1210 and the opposing substrate. Accordingly, a reduction of an aperture ratio due to an alignment error may be reduced or prevented.
  • FIG. 18 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 1300 of FIG. 18 may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 1300 may be substantially the same as the display panel 1200 illustrated in FIGS. 16A and 16B , except for at least one element of a display substrate 1310 .
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 1310 may include an insulating substrate (not shown), a plurality of signal lines, a plurality of electric field generating electrodes, a plurality switching elements, and a first alignment layer (not shown).
  • First to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may be located along a first direction D 1 .
  • Fifth to eighth pixel regions PA 5 , PA 6 , PA 7 , and PA 8 may be located in a second direction D 2 from the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 , respectively.
  • the signal lines may include a first gate line GL 1 , a second gate line GL 2 , a third gate line GL 3 , a fourth gate line GL 4 , a first data line DL 1 , a second data line DL 2 , and a third data line DL 3 .
  • the electric field generating electrodes may include first to eighth lower electrodes 1313 _ 1 , 1313 _ 2 , 1313 _ 3 , 1313 _ 4 , 13135 , 13136 , 1313 _ 7 , and 1313 _ 8 , and first to eighth upper electrodes 1314 _ 1 , 1314 _ 2 , 1314 _ 3 , 1314 _ 4 , 1314 _ 5 , 1314 _ 6 , 1314 _ 7 , and 1314 _ 8 .
  • the first to eighth upper electrodes 1314 _ 1 , 1314 _ 2 , 1314 _ 3 , 1314 _ 4 , 1314 _ 5 , 1314 _ 6 , 1314 _ 7 , and 1314 _ 8 may be formed to overlap the first to eighth lower electrodes 1313 _ 1 , 1313 _ 2 , 1313 _ 3 , 1313 _ 4 , 1313 _ 5 , 1313 _ 6 , 1313 _ 7 , and 1313 _ 8 , respectively.
  • the first to eighth upper electrodes 1314 _ 1 , 1314 _ 2 , 1314 _ 3 , 1314 _ 4 , 1314 _ 5 , 1314 _ 6 , 1314 _ 7 , and 1314 _ 8 may have first to eighth silt patterns 1315 _ 1 , 1315 _ 2 , 1315 _ 3 , 1315 _ 4 , 13155 , 13156 , 1315 _ 7 , and 1315 _ 8 , respectively.
  • the first to eighth upper electrodes 1314 _ 1 , 1314 _ 2 , 1314 _ 3 , 1314 _ 4 , 1314 _ 5 , 1314 _ 6 , 1314 _ 7 , and 1314 _ 8 may be coupled to the signal lines through the first to eighth switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 , respectively.
  • the first to eighth upper electrodes 1314 _ 1 , 1314 _ 2 , 1314 _ 3 , 1314 _ 4 , 1314 _ 5 , 1314 _ 6 , 1314 _ 7 , and 1314 _ 8 may be pixel electrodes for receiving pixel voltages.
  • the first to fourth switching elements SW 1 , SW 2 , SW 3 , and SW 4 may be electrically coupled to the first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 , respectively.
  • the second and fourth switching elements SW 2 and SW 4 may be coupled to the first data line DL 1
  • the first and third switching elements SW 1 and SW 3 may be coupled to the second data line DL 2 .
  • the fifth to eighth switching elements SW 5 , SW 6 , SW 7 , and SW 8 may be electrically coupled to the first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 , respectively.
  • the sixth and eighth switching elements SW 6 and SW 8 may be coupled to the second data line DL 2
  • the fifth and seventh switching elements SW 5 and SW 7 may be coupled to the third data line DL 3 .
  • an arrangement of the switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 may be changed along the first direction D 1 . Therefore, light-blocking regions may be alternately arranged, so that the display device including the display panel 1300 may have balanced visibility in the left and right viewing directions. Further, since the switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 may be alternately coupled to different data lines along the first direction D 1 , a dot inversion method may be performed using a driving signal of a line inversion method.
  • the data lines, the lower electrodes, the upper electrodes, and slit patterns of the display substrate 1310 may be substantially similar to those of the display substrates 310 , 410 , 510 and 610 illustrated in FIGS. 7 to 10 .
  • the display panel 1300 may include an opposing substrate facing the display substrate 1310 .
  • the opposing substrate may include a light-blocking pattern.
  • FIG. 19A is a block diagram illustrating a display panel in accordance with example embodiments.
  • FIG. 19B is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 1400 of FIGS. 19A and 19B may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 4 , 5 and 6 .
  • the display panel 1400 may be substantially the same as the display panel 700 illustrated in FIGS. 11A and 11B , except for a display substrate 1410 .
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display panel 1400 may include a display substrate 1410 (or a lower substrate), an opposing substrate (or an upper substrate), and a liquid crystal layer.
  • the display panel 1400 may include a plurality of pixels, and a plurality of signal lines coupled to the pixels.
  • the pixels may be arranged in a matrix form.
  • the pixels may include first to eighth pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 .
  • Each of the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 may include a pair of electric field generating electrodes, and a liquid crystal layer formed on the display substrate 1410 .
  • Each of the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 may form the domain using a slit pattern formed in a corresponding upper electrode.
  • Adjacent pixels that are arranged along a second direction D 2 may have the same domain, and adjacent pixels that are arranged along a first direction D 1 may have different domains.
  • the signal lines may include first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 and first to third data lines DL 1 , DL 2 , and DL 3 .
  • the signal lines may be coupled to the pixels PX 1 , PX 2 , PX 3 , PX 4 , PX 5 , PX 6 , PX 7 , and PX 8 .
  • the display substrate 1210 may include an insulating layer, the signal lines, the electric field generating electrodes, a plurality of switching elements, and a first alignment layer.
  • the insulating substrate may include first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 .
  • the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may be arranged along the first direction D 1 .
  • the fifth to eighth pixel regions PA 5 , PA 6 , PA 7 , and PA 8 may be located in the second direction D 2 from the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the electric field generating electrodes may include first to eighth lower electrodes 1413 _ 1 , 1413 _ 2 , 1413 _ 3 , 1413 _ 4 , 1413 _ 5 , 1413 _ 6 , 1413 _ 7 , and 1413 _ 8 , and first to eighth upper electrodes 1414 _ 1 , 1414 _ 2 , 1414 _ 3 , 1414 _ 4 , 1414 _ 5 , 1414 _ 6 , 1414 _ 7 , and 1414 _ 8 .
  • the first to eighth upper electrodes 1414 _ 1 , 1414 _ 2 , 1414 _ 3 , 1414 _ 4 , 1414 _ 5 , 1414 _ 6 , 1414 _ 7 , and 1414 _ 8 may be formed to overlap the first to eighth lower electrodes 1413 _ 1 , 1413 _ 2 , 1413 _ 3 , 1413 _ 4 , 1413 _ 5 , 1413 _ 6 , 1413 _ 7 , and 1413 _ 8 in the first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 , respectively.
  • the first to eighth lower electrodes 1413 _ 1 , 1413 _ 2 , 1413 _ 3 , 1413 _ 4 , 1413 _ 5 , 1413 _ 6 , 1413 _ 7 , and 1413 _ 8 may be coupled to the signal lines through the first to eighth switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 , respectively.
  • the first to eighth lower electrodes 141 , 3 _ 1 , 1413 _ 2 , 1413 _ 3 , 1413 _ 4 , 1413 _ 5 , 1413 _ 6 , 1413 _ 7 , and 1413 _ 8 may be pixel electrodes for receiving pixel voltages.
  • the first to eighth upper electrodes 1414 _ 1 , 1414 _ 2 , 1414 _ 3 , 1414 _ 4 , 1414 _ 5 , 1414 _ 6 , 1414 _ 7 , and 1414 _ 8 may have first to eighth silt patterns 1415 _ 1 , 1415 _ 2 , 1415 _ 3 , 1415 _ 4 , 1415 _ 5 , 1415 _ 6 , 1415 _ 7 , and 1415 _ 8 , respectively.
  • the first, third, fifth, and seventh silt patterns 1415 _ 1 , 1415 _ 3 , 1415 _ 5 , and 1415 _ 7 may extend in a third direction that is different from the first and second directions D 1 and D 2 .
  • the second, fourth, sixth, and eighth silt patterns 1415 _ 2 , 1415 _ 4 , 1415 _ 6 , and 1415 _ 8 may extend in a fourth direction that is different from the first and second directions D 1 and D 2 , and the third direction.
  • the third and fourth directions may be symmetric with respect to the second direction D 2 .
  • the first and second upper electrodes 1414 _ 1 and 1414 _ 2 may have an integral structure. Further, the first and second slit patterns 1415 _ 1 and 1415 _ 2 may be coupled to each other. For example, a lower edge portion of the first slit pattern 1415 _ 1 may be coupled to an upper edge portion of the second slit pattern 1415 _ 2 . If the first and second slit patterns 1415 _ 1 and 1415 _ 2 are coupled to each other, an electrical distortion at a boundary between the first and second upper electrodes 1414 _ 1 and 1414 _ 2 , may be reduced, thereby improving visibility.
  • the first to fourth switching elements SW 1 , SW 2 , SW 3 , and SW 4 may be electrically coupled to the first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 , respectively, and may be coupled to the first data line DL 1 .
  • the fifth to eighth switching elements SW 5 , SW 6 , SW 7 , and SW 8 may be electrically coupled to the first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 , respectively, and may be coupled to the second data line DL 2 .
  • the first to eighth switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 may be located adjacently to the signal lines.
  • the data lines, the lower electrodes, the upper electrodes and the slit patterns of the display substrate 1410 may be substantially similar to those of the display substrates 810 , 910 , 1010 , and 1110 illustrated in FIGS. 12 to 15 .
  • the opposing substrate may include a light-blocking pattern, color filters and a second alignment layer.
  • FIG. 20 is a plan view illustrating a display panel in accordance with example embodiments.
  • a display panel 1500 of FIG. 20 may be included in the display device 10 illustrated in FIGS. 1 and 2 , or in the display device 20 illustrated in FIGS. 5 , 6 and 7 .
  • the display panel 1500 may be substantially the same as a display panel 1400 illustrated in FIGS. 19A and 19B , except for a display substrate 1510 .
  • differences will be briefly described hereinafter and any repetitive descriptions may be omitted.
  • a display substrate 1510 may include an insulating layer, a plurality of signal lines, a plurality of electric field generating electrodes, a plurality of switching elements, and a first alignment layer.
  • the insulating substrate may include first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 .
  • the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 may be arranged along the first direction D 1 .
  • the fifth to eighth pixel regions PA 5 , PA 6 , PA 7 , and PA 8 may be located in the second direction D 2 from the first to fourth pixel regions PA 1 , PA 2 , PA 3 , and PA 4 .
  • the signal lines may include first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 , and first to third data lines DL 1 , DL 2 , and DL 3 crossing the first to fourth gate lines GL 1 , GL 2 , GL 3 , and GL 4 .
  • the signal lines may be substantially the same as the signals illustrated in FIGS. 16A and 16B .
  • the electric field generating electrodes may include first to eighth lower electrodes 1513 _ 1 , 1513 _ 2 , 1513 _ 3 , 1513 _ 4 , 1513 _ 5 , 1513 _ 6 , 1513 _ 7 , and 1513 _ 8 , and first to eighth upper electrodes 1514 _ 1 , 1514 _ 2 , 1514 _ 3 , 1514 _ 4 , 1514 _ 5 , 1514 _ 6 , 1514 _ 7 , and 1514 _ 6 .
  • the first to eighth upper electrodes 1514 _ 1 , 1514 _ 2 , 1514 _ 3 , 1514 _ 4 , 1514 _ 5 , 1514 _ 6 , 1514 _ 7 , and 1514 _ 8 may be formed to overlap the first to eighth lower electrodes 1513 _ 1 , 1513 _ 2 , 1513 _ 3 , 1513 _ 4 , 1513 _ 5 , 1513 _ 6 , 1513 _ 7 , and 1513 _ 8 in the first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 , respectively.
  • the first to eighth upper electrodes 11514 _ 1 , 1514 _ 2 , 1514 _ 3 , 1514 _ 4 , 1514 _ 5 , 1514 _ 6 , 1514 _ 7 , and 1514 _ 8 may have first to eighth silt patterns 1515 _ 1 , 1515 _ 2 , 1515 _ 3 , 1515 _ 4 , 1515 _ 5 , 1515 _ 6 , 1515 _ 7 , and 1515 _ 8 , respectively.
  • the first to eighth silt patterns 1515 _ 1 , 1515 _ 2 , 1515 _ 3 , 1515 _ 4 , 1515 _ 5 , 1515 _ 6 , 1515 _ 7 , and 1515 _ 8 may be substantially the same as the first to eighth silt patterns 1415 _ 1 , 1415 _ 2 , 1415 _ 3 , 1415 _ 4 , 1415 _ 5 , 1415 _ 6 , 1415 _ 7 , and 1415 _ 8 illustrated in FIGS. 19A and 19B .
  • the first to eighth lower electrodes 1513 _ 1 , 1513 _ 2 , 1513 _ 3 , 1513 _ 4 , 1513 _ 5 , 1513 _ 6 , 1513 _ 7 , and 1513 _ 8 may be coupled to the signal lines through the first to eighth switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 .
  • the first to eighth lower electrodes 1513 _ 1 , 1513 _ 2 , 1513 _ 3 , 1513 _ 4 , 1513 _ 5 , 1513 _ 6 , 1513 _ 7 , and 1513 _ 8 may be pixel electrodes for receiving pixel voltages.
  • the first to eighth switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 may be located in the first to eighth pixel regions PA 1 , PA 2 , PA 3 , PA 4 , PA 5 , PA 6 , PA 7 , and PA 8 , respectively.
  • the connections between the first to eighth switching elements SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 , and SW 8 , and the signal lines in the display substrate 1510 may be substantially the same as those of the display substrate 1410 illustrated in FIGS. 19A and 19B .
  • the data lines, the lower electrodes, the upper electrodes and slit patterns of the display substrate 1510 may be substantially similar to those of the display substrates 310 , 410 , 510 and 610 illustrated in FIGS. 7 to 10 .
  • the display panel 1500 may include an opposing substrate facing the display substrate 1510 .
  • the opposing substrate may include a light-blocking pattern, color filters and a second alignment layer.

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US11333937B2 (en) 2022-05-17
CN102566176A (zh) 2012-07-11
US20180284549A1 (en) 2018-10-04
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EP2458432B1 (en) 2018-01-10
JP2012113305A (ja) 2012-06-14

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