US20120068676A1 - Voltage generation circuit - Google Patents

Voltage generation circuit Download PDF

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Publication number
US20120068676A1
US20120068676A1 US13/237,006 US201113237006A US2012068676A1 US 20120068676 A1 US20120068676 A1 US 20120068676A1 US 201113237006 A US201113237006 A US 201113237006A US 2012068676 A1 US2012068676 A1 US 2012068676A1
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United States
Prior art keywords
circuit
pulse
voltage
control
driving
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US13/237,006
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Norihiro KAWAGISHI
Nobuaki Tsuji
Toshio Maejima
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Yamaha Corp
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Yamaha Corp
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Assigned to YAMAHA CORPORATION reassignment YAMAHA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAWAGISHI, NORIHIRO, MAEJIMA, TOSHIO, TSUJI, NOBUAKI
Publication of US20120068676A1 publication Critical patent/US20120068676A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a technique of generating a predetermined voltage.
  • JP-A-2008-236822 proposes a technique of switching a period for controlling the conductive/non-conductive state of a transistor between a low load state and a high load state.
  • two kinds of clock signals that is, a reference clock signal of a predetermined frequency and a control clock signal of a frequency variable according to a load are generated in parallel, whereby the transistor is controlled in accordance with the reference clock signal in the high load state but controlled in accordance with the control clock signal in the low load state. According to the above configuration, it is possible to reduce an amount of dissipation power in the low load state.
  • an object of the invention is to reduce an amount of dissipation power in the low load state without requiring two kinds of signals and circuits.
  • a voltage generation circuit for generating an output voltage by supplying a driving pulse to a transistor connected to a DC power source so as to be turned on, comprising:
  • a voltage detection circuit that generates a detection voltage according to the output voltage
  • a reference voltage generation circuit that generates a reference voltage which changes periodically
  • a comparison circuit that generates a control signal according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses each having a pulse width according to the detection voltage are sequentially appeared in the control signal;
  • a driving pulse generation circuit that generates the driving pulse corresponding to the control pulse and supplies the generated driving pulse to the transistor when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width.
  • the driving pulse generation circuit includes a delay circuit which delays the control signal, a logical circuit which outputs as an output signal, a result of a negative AND operation between the control signal before the delay processing and the control signal after the delay processing, and a driving circuit which generates the driving pulse according to the output signal of the logical circuit.
  • the driving circuit generates the driving pulse in which a front edge is defined according to the output signal of the logical circuit and a rear edge is defined according to the control signal after the delay processing by the delay circuit.
  • a delay amount of the delay circuit is set to be variable.
  • the driving pulse generation circuit includes a counting circuit which measures the pulse width of the control pulse, a comparator which generates an output signal according to a result of a comparison between the pulse width measured by the counting circuit and a reference value, and a driving circuit which generates the driving pulse according to the output signal output from the comparator.
  • FIG. 1 is a block diagram showing a voltage generation circuit according to a first embodiment of the invention
  • FIG. 2 is a waveform diagram of respective signals in a high load state
  • FIG. 3 is a waveform diagram of respective signals in a low load state
  • FIG. 4 is a block diagram showing a voltage generation circuit according to a second embodiment of the invention.
  • FIG. 5 is a block diagram showing a voltage generation circuit according to a modified example 1 of the invention.
  • FIG. 6 is a circuit diagram of the voltage generation circuit in a modified example 2.
  • FIG. 1 is a block diagram showing a voltage generation circuit 100 according to the first embodiment of the invention.
  • the voltage generation circuit 100 is a power source circuit (DC-DC converter) which generates an output voltage VOUT according to an input voltage VIN generated from a DC power source 12 and supplies the output voltage to an output terminal 14 .
  • the output terminal 14 is coupled to a driving load (not shown).
  • the voltage generation circuit 100 includes a P-channel transistor TR 1 , an N-channel transistor TR 2 , a choke coil L, a smoothing capacitor C and a control circuit 20 .
  • the transistor TR 1 and the transistor TR 2 are coupled in series to the power source.
  • a drain of the transistor TR 1 and a drain of the transistor TR 2 are coupled to mutually at a coupling point N.
  • a source of the transistor TR 1 is supplied with the input voltage VIN and a source of the transistor TR 2 is grounded.
  • the choke coil L is disposed between the output terminal 14 (driving load) and the coupling point N between the transistor TR 1 and the transistor TR 2 .
  • the smoothing capacitor C is coupled to the output terminal 14 and smoothes the output voltage VOUT.
  • the control circuit 20 generates the output voltage VOUT at the output terminal 14 under the control of the transistor TR 1 and the transistor TR 2 .
  • the control circuit 20 supplies a driving signal DR 1 to a gate of the transistor TR 1 and also supplies a driving signal DR 2 to a gate of the transistor TR 2 .
  • the control circuit 20 includes a voltage detection circuit 30 , a reference generation circuit 40 , a comparison circuit 50 and a driving pulse generation circuit 60 .
  • the first embodiment exemplarily shows the configuration where the control circuit 20 is mounted on a single integrated circuit, the invention may employ the configuration where the respective elements of the control circuit 20 are mounted on a plurality of integrated circuits in a distributed manner.
  • the voltage detection circuit 30 generates a detection voltage VD according to the output voltage VOUT generated at the output terminal 14 .
  • the voltage detection circuit 30 of the first embodiment includes a resistor element 322 , a resistor element 324 , a voltage source 34 and an amplifier (error amplifier 36 ).
  • the resistor element 322 and the resistor element 324 divide the output voltage VOUT fed back from the output terminal 14 to generate a feedback voltage V 1 .
  • the voltage source 34 is a DC power source for generating a predetermined comparison voltage V 2 (for example, 1.2 volt).
  • the feedback voltage V 1 is supplied to the non-inverting input terminal of the amplifier 36 and the comparison voltage V 2 is supplied to the inverting input terminal of the amplifier 36 .
  • the amplifier 36 generates the detection voltage VD which is obtained by amplifying a difference voltage between the feedback voltage V 1 and the comparison voltage V 2 .
  • the detection voltage VD becomes larger as the output voltage VOUT is higher than the comparison voltage V 2
  • the detection voltage VD becomes smaller as the output voltage VOUT is lower than the comparison voltage V 2 . Since the output voltage VOUT becomes smaller as the supply power to the driving load increases (in a higher load state), the detection voltage VD reduces according to the higher load state (the detection voltage VD increases according to a lower load state).
  • FIG. 2 is a waveform diagram of respective signals in the high load state (the case where the detection voltage VD is low)
  • FIG. 3 is a waveform diagram of respective signals in the low load state (the case where the detection voltage VD is high).
  • the reference generation circuit 40 in FIG. 1 is an oscillation circuit for generating a reference voltage VREF which changes periodically and configured to include a current source circuit 42 , a transistor 44 and a capacitor element 46 .
  • a voltage between the both ends of the capacitor element 46 is supplied to the comparison circuit 50 as the reference voltage VREF.
  • the current source circuit 42 is a constant current source which generates a predetermined current and supplies to the capacitor element 46 .
  • the transistor 44 is a switch disposed between the both ends of the capacitor element 46 . When a clock signal CLK having a unit period T 0 as a single period is supplied to the gate of the transistor 44 , the transistor simultaneously shifts to an ON state at the start point of the unit period T 0 to thereby short-circuit between the both ends of the capacitor element 46 .
  • the reference voltage VREF of a triangular waveform or a sawtooth waveform is generated between the both ends of the capacitor element 46 in a manner that this reference voltage varies periodically at every unit period T 0 as a single period so as to be initialized to zero at the start point of each of the respective unit periods T 0 and increased within the unit period T 0 with time
  • the comparison circuit 50 is configured by an operational amplifier having an inverting input terminal and a non-inverting input terminal.
  • the detection voltage VD generated by the voltage detection circuit 30 is supplied to the inverting input terminal of the comparison circuit 50 and the reference voltage VREF generated by the reference generation circuit 40 is supplied to the non-inverting input terminal of the comparison circuit 50 .
  • the comparison circuit 50 compares the detection voltage VD and the reference voltage VREF to thereby generate a control signal X according to the comparison result.
  • the control signal X is set to a high level when the reference voltage VREF is higher than the detection voltage VD, whilst the control signal X is set to a low level when the reference voltage VREF is lower than the detection voltage VD.
  • the control signal X is generated in a manner that a pulse (hereinafter called a “control pulse”) PX is disposed at each unit period T 0 corresponding to the period of the reference voltage VREF.
  • the comparison circuit 50 acts as a pulse width modulation circuit for generating the control signal X in which the pulses PX respectively having the pulse widths WX according to the detection voltages VD (output voltages VOUT) are disposed.
  • the driving pulse generation circuit 60 in FIG. 1 generates the driving signal DR 1 and the driving signal DR 2 by utilizing the control signal X supplied from the comparison circuit 50 .
  • the driving pulse generation circuit 60 includes a short pulse removing circuit 70 and a driving circuit 80 .
  • the short pulse removing circuit 70 generates a control signal Y 1 and a control signal Y 2 from the control signal X generated from the comparison circuit 50
  • the driving circuit 80 generates the driving signal DR 1 and the driving signal DR 2 from the control signal Y 1 and the control signal Y 2 .
  • the short pulse removing circuit 70 is configured by including a delay circuit 72 , a logical circuit 74 , an inverting circuit 76 and an inverting circuit 78 .
  • the delay circuit 72 generates a control signal XD which is obtained by delaying the control signal X generated by the comparison circuit 50 by a predetermined delay amount ⁇ .
  • the delay amount ⁇ of the delay circuit 72 is set to be shorter than the unit period T 0 (single period of the reference voltage VREF).
  • the logical circuit 74 in FIG. 1 is a negative AND circuit which outputs the result of a negative AND (NAND) operation between the control signal X before the delay processing by the delay circuit 72 (that is, the control signal X just after the comparison circuit 50 ) and the control signal XD after the delay processing by the delay circuit 72 .
  • the inverting circuit 76 inverts the output signal of the logical circuit 74 to thereby generate the control signal Y 1 .
  • the control pulse PX is partially overlapped between the control signal X before the delay processing and the control signal XD after the delay processing.
  • a control pulse PY 1 having a pulse width corresponding to a section where the control pulse PX is overlapped between the control signal X and the control signal XD is generated in the control signal Y 1 .
  • the control pulse PX is not overlapped between the control signal X before the delay processing and the control signal XD after the delay processing.
  • the control pulse PY 1 corresponding to the control pulse PX having the pulse width WX smaller than the delay amount ⁇ is not generated but only the control pulse PY 1 corresponding to the control pulse PX having the pulse width WX larger than the delay amount ⁇ is generated in the control signal Y 1 . That is, the short pulse removing circuit 70 acts as an element for removing the control pulse PX having the pulse width WX smaller than the delay amount ⁇ in the control signal Y 1 .
  • the inverting circuit 78 in FIG. 1 inverts the control signal XD after the delay processing by the delay circuit 72 to thereby generate the control signal Y 2 .
  • a control pulse PY 2 having the opposite polarity (negative polarity) to that of each of the control pulses PX of the control signal XD is generated in the control signal Y 2 .
  • the driving circuit 80 in FIG. 1 includes a signal generation circuit 82 , a signal generation circuit 84 and a comparison circuit 86 .
  • Each of the signal generation circuit 82 and the signal generation circuit 84 is configured by an RS (Reset-Set) flip-flop.
  • the signal generation circuit 82 generates the driving signal DR 1 and supplies from an output terminal /Q thereof to the gate of the transistor TR 1
  • the signal generation circuit 84 generates the driving signal DR 2 and supplies from an output terminal Q thereof to the gate of the transistor TR 2 .
  • the input terminal S of the signal generation circuit 82 is supplied with the control signal Y 1 from the short pulse removing circuit 70 (inverting circuit 76 ), whilst each of the input terminal R of the signal generation circuit 82 and the input terminal S of the signal generation circuit 84 is supplied with the control signal Y 2 from the short pulse removing circuit 70 (inverting circuit 78 ).
  • the input terminal R of the signal generation circuit 84 is supplied with a comparison signal SC from the comparison circuit 86 .
  • the comparison circuit 86 generates the control signal SC according to the voltage difference between the voltage VN at a connection point N (hereinafter called a “connection point voltage”) between the transistor TR 1 and the transistor TR 2 and the ground voltage GND (zero).
  • the comparison signal SC is set to a low level when the connection point voltage VN is lower than the ground voltage GND (VN ⁇ GND), whilst the comparison signal SC is set to a high level when the connection point voltage VN is equal to or higher than the ground voltage GND (VN ⁇ GND).
  • the control pulse PY 1 corresponding to the overlapping between the control signal before the delay processing and the control signal after the delay processing is generated in the control signal Y 1 .
  • a driving pulse PDR 1 having a pulse width corresponding to a section from the front edge of the control pulse PY 1 of the control signal Y 1 to the rear edge of the control pulse PY 2 immediately after the control signal Y 2 (that is, a pulse width equal to that of the control pulse PX) is sequentially appeared in correspondence to each of the control pulses PX (WX> ⁇ ).
  • the driving pulse PDR 1 is a pulse of the negative polarity for turning the P-channel transistor TR 1 on.
  • the transistor TR 2 shifts to the off state, whereby the connection point voltage VN changes to the output voltage VOUT.
  • the current IL is repeatedly generated at every generation of the control pulse PX of the control signal X (control signal XD), whereby the output voltage VOUT is kept to a predetermined target value with a high accuracy.
  • the control pulse PY 1 corresponding to the control pulse PX is not generated in the control signal Y 1 (that is, the signal generation circuit 82 is not set).
  • the driving pulse is PDR 1 corresponding to the control pulse PX is not generated in the driving signal DR 1 .
  • the driving pulse generation circuit 60 generates the driving pulse PDR 1 corresponding to the control pulse PX having the pulse width WX exceeding the delay amount ⁇ and supplies this driving pulse to the transistor TR 1 , whilst stops generating the driving pulse PDR 1 when the pulse width WX becomes smaller than the delay amount ⁇ . Since the transistor TR 1 does not shift to the ON state in the state where the generation of the driving pulse PDR 1 is stopped, the current IL is not supplied to the choke coil L.
  • the output voltage VOUT reduces with time when the stopping state of the current IL continues as described above, whereby the pulse width WX becomes larger than the delay amount ⁇ like the third control pulse PX from the left side in FIG. 3 , for example.
  • the driving pulse PDR 1 is generated in the driving signal DR 1 to thereby shift the transistor TR 1 to the ON state.
  • the current IL passed through the transistor TR 1 is supplied to the choke coil L to thereby increase the output voltage VOUT.
  • the pulse width WX of the control pulse PX becomes smaller than the delay amount ⁇ , whereby the generation of the driving signal DR 1 is stopped again.
  • the frequency of the supply of the current IL to the chock coil L (increase of the output voltage VOUT) in the low load state reduces as compared with the high load state by a degree that the generation of the driving pulse PDR 1 corresponding to the control pulse PX having the pulse width WX smaller than the delay amount ⁇ is stopped in the low load state.
  • an amount of the consumption power can be reduced as compared with the configuration where the current IL is generated at every control pulse PX also in the low load state as well as the high load state.
  • the output voltage VOUT can be kept to the target value with a high accuracy by generating the current IL at every control pulse PX of the control signal X in the high load state, whilst an amount of the consumption power can be reduced by stopping the generation of the driving pulse PDR 1 in the low load state. Further, since the generation/stop of the driving pulse PDR 1 is controlled according to the comparison between the predetermined value (delay amount ⁇ ) and the pulse width WX of the control signal X generated by the comparison between the detection voltage VD (output voltage VOUT) and the reference voltage VREF, the aforesaid respective effects can be realized while utilizing the common reference voltage VREF both in the high load state and the low load state.
  • this embodiment is advantageous in that the circuit configuration can be simplified and the output voltage VOUT can be generated continuously as compared with the configuration where the circuit for the high load state and the circuit for the low load state are provided separately and one of these circuits is selectively utilized.
  • FIG. 4 is a block diagram showing a voltage generation circuit according to a second embodiment of the invention.
  • elements identical in actions and functions to those of the first embodiment are referred to by the common symbols, with detailed explanation thereof being omitted suitably.
  • the delay circuit 172 in the second embodiment is a variable delay circuit (a variable delay line, for example) capable of setting the delay amount ⁇ to be applied to the control signal X so as to be variable.
  • the delay amount ⁇ may be set to be variable according to an instruction from an input device 400 operated by a user.
  • the number of the control pulses PX each having the pulse width WX smaller than the delay amount ⁇ increases as the delay amount ⁇ is increased.
  • the effects of the reduction of a consumption amount in the low load state becomes remarkable in the large delay amount state as compared with the case where the delay amount ⁇ is small.
  • the number of the control pulses PX each having the pulse width WX smaller than the delay amount ⁇ reduces as the delay amount ⁇ is reduced.
  • the effects of keeping the output voltage VOUT to the target value with a high accuracy becomes remarkable in the small delay amount state as compared with the case where the delay amount ⁇ is large.
  • the number of the control pulses PX being reflected on the generation of the driving pulses PDR 1 can be controlled so as to be variable according to the delay amount ⁇ .
  • the voltage generation performance generation of the output voltage VOUT with a high accuracy/reduction of an amount of power consumption
  • the delay amount ⁇ is increased in the usage where the reduction of an amount of power consumption should have priority, whilst the delay amount ⁇ is reduced in the usage where the generation of the output voltage VOUT with a high accuracy should have priority.
  • the generation of the driving pulses PDR 1 is stopped as to the control pulse having the pulse width WX smaller than the delay amount ⁇ by performing the negative AND operation between the control signal X before the delay processing by the delay circuit 72 ( 172 ) and the control signal XD after the delay processing.
  • the configuration of not reflecting the control pulse PX having the pulse width WX smaller than the predetermined width on the generation of the driving signal DR 1 is not limited to the above configuration.
  • FIG. 5 is a block diagram showing a voltage generation circuit according to a modified example 1 of the invention.
  • a counting circuit (counter) 500 and a comparator is provided instead of the delay circuit 72 ( 172 ), the logical circuit 74 , the inverting circuit 76 , and the inverting circuit 78 .
  • the pulse width WX of the control pulse PX is measured by utilizing the counting circuit 500 to thereby determine whether or not the control pulse PX is to be reflected on the driving signal DR 1 according to the comparison result between the measured value and a reference value VREFX.
  • the number of the control pulses PX being reflected on the generation of the driving pulses PDR 1 can be easily controlled so as to be variable according to a setting of the reference value VREFX to be compared with the pulse width WX of the control pulse PX measured by the counting circuit 500 .
  • the voltage generation performance generation of the output voltage VOUT with a high accuracy/reduction of an amount of power consumption
  • the usage of the voltage generation circuit 100 shown in FIG. 5 can be set so as to be variable according to the usage of the voltage generation circuit 100 shown in FIG. 5 .
  • the above respective embodiments have the advantage that the configuration of the driving pulse generation circuit 60 (short pulse removing circuit 70 ) can be simplified as compared with the configuration that the pulse width WX is measured by the counting circuit, for example.
  • phase compensation circuit 38 for preventing the oscillation of the amplifier 36 to stably operate the amplifier is added to the voltage detection circuit 30 in each of the embodiments.
  • the phase compensation circuit 38 shown in FIG. 6 is configured by a capacitor element 382 and a resistor element 384 connected in series between the non-inverting input terminal and the output terminal 14 of the amplifier 36 .
  • the phase compensation circuit 38 shown in FIG. 6 is also required to be provided separately for the high load and the low load.
  • the circuit for stabilizing the operation like the phase compensation circuit 38 shown in FIG. 6 can also be advantageously utilized commonly between the high load state and the low load state.
  • the voltage generation circuit is a voltage generation circuit for generating an output voltage (an output voltage VOUT, for example) by supplying a driving pulse (a driving pulse PDR 1 , for example) to a transistor (a transistor TR 1 , for example) connected to a DC power source (a DC power source 12 , for example) so as to be turned on, that comprises:
  • a voltage detection circuit (a voltage detection circuit 30 , for example) that generates a detection voltage (a detection voltage VD, for example) according to the output voltage;
  • a reference voltage generation circuit (a reference generation circuit 40 , for example) that generates a reference voltage (a reference voltage VREF, for example) which changes periodically;
  • a comparison circuit (a comparison circuit 50 , for example) that generates a control signal (a control signal X, for example) according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses (control pulses PX, for example) each having a pulse width according to the detection voltage are sequentially appeared in the control signal; and
  • a driving pulse generation circuit (a driving pulse generation circuit 60 , for example) that generates a driving pulse corresponding to the control pulse and supplies the generated driving pulse to the transistor when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width.
  • the output voltage VOUT is kept to a target value with a high accuracy by generating the driving pulse at every control pulse of the control signal in the high load state, whilst an amount of the consumption power can be reduced by stopping the generation of the driving pulse in the low load state.
  • the control signal generated according to the comparison between the detection voltage and the reference voltage since the generation of the driving pulse is stopped as to the control pulse which pulse width is smaller than the predetermined width, the respective effects can be realized while utilizing the common circuits and signals (the reference signal VREF, for example) between the high load state and the low load state.
  • this invention has an advantage (the circuit configuration can be simplified, for example) that it is not necessary to employ the circuits and signals separately between the high load state and the low load state.
  • the driving pulse generation circuit includes a delay circuit which delays the control signal, a logical circuit which outputs a result of a negative AND operation between the control signal before the delay processing and the control signal after the delay processing, and a driving circuit which generates the driving pulse according to an output signal of the logical circuit.
  • the logical circuit outputs the result of the negative AND operation between the control signal before the delay processing and the control signal after the delay processing.
  • pulses are generated each of which corresponds to the overlapping between the control signal (a control signal X, for example) before the delay processing and the control signal (a control signal XD, for example) after the delay processing. That is, the control pulse is reflected on the output signal of the logical circuit when the pulse width of the control pulse in the control signal exceeds the delay amount of the delay circuit, whilst the control pulse is not reflected on the output signal of the logical circuit when the pulse width of the control pulse in the control signal is smaller than the delay amount of the delay circuit.
  • the driving circuit generates the driving pulse in which a front edge is defined according to the output signal of the logical circuit and a rear edge is defined according to the control signal after the delay processing by the delay circuit, for example.
  • the length of the control pulse can be discriminated advantageously with a simple configuration utilizing the delay circuit.
  • the delay circuit for discriminating the pulse width of the control pulse since the number of the control pulses (the control pulses reflected on the output signal of the logical circuit) used for the generation of the driving pulses reduces when the delay amount of the delay circuit is large, an amount of dissipation power necessary for generating the output voltage is reduced. On the other hand, since the number of the control pulses used for the generation of the driving pulses increases when the delay amount of the delay circuit is small, the output voltage can be set and kept to a predetermined target value with a high accuracy.
  • a delay amount of the delay circuit is set to be variable, either one of the generation of the output voltage with a high accuracy and the reduction of an amount of the dissipation power is set to have priority selectively according to the delay amount of the delay circuit.
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US20130335048A1 (en) * 2012-06-13 2013-12-19 Intel Mobile Communications GmbH Switched Mode Power Supply and Method of Operating Thereof
US9048730B2 (en) 2012-06-13 2015-06-02 Intel Mobile Communications GmbH Switched mode power supply and a method for operating a switched mode power supply
US9118241B2 (en) 2012-06-13 2015-08-25 Intel Deutschland Gmbh Switched-mode power supply and a two-phase DC to DC converter having switches and a filter that deliver current from a node among converter stages

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US9118241B2 (en) 2012-06-13 2015-08-25 Intel Deutschland Gmbh Switched-mode power supply and a two-phase DC to DC converter having switches and a filter that deliver current from a node among converter stages

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KR20120031145A (ko) 2012-03-30
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US8653803B2 (en) 2014-02-18
JP2012070501A (ja) 2012-04-05

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