US20110316107A1 - Solid-state image sensor and manufacturing method of the sensor - Google Patents

Solid-state image sensor and manufacturing method of the sensor Download PDF

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US20110316107A1
US20110316107A1 US13/220,079 US201113220079A US2011316107A1 US 20110316107 A1 US20110316107 A1 US 20110316107A1 US 201113220079 A US201113220079 A US 201113220079A US 2011316107 A1 US2011316107 A1 US 2011316107A1
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single crystal
crystal silicon
layer
silicon layer
wafer
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Akira Tsukamoto
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Corp
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Priority to US14/061,750 priority Critical patent/US9018031B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/014—Manufacture or treatment of image sensors covered by group H10F39/12 of CMOS image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/026—Wafer-level processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/199—Back-illuminated image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/139—Manufacture or treatment of devices covered by this subclass using temporary substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Definitions

  • the present disclosure relates to solid-state image sensors and manufacturing methods of the sensors, and more particularly to solid-state image sensors using silicon-on-insulator (SOI) substrates and manufacturing methods of the sensors.
  • SOI silicon-on-insulator
  • Solid-state image sensors such as charge coupled devices (CCDs), CMOS image sensors, etc., are generally used for digital cameras, video cameras, etc.
  • CCDs charge coupled devices
  • CMOS image sensors etc.
  • high-definition images can be obtained by a solid-state image sensor with highly dense pixels.
  • a conventional solid-state image sensor includes a transfer gate, a photoelectric conversion element, a MOS transistor, various interconnects, etc. on a semiconductor substrate.
  • a light-receiving region of a photoelectric conversion element needs to be provided avoiding the transfer gate, the MOS transistor, the interconnects, etc. There is thus the problem that the aperture ratio of the light-receiving region reduces with a reduced pixel size due to reduction in the area of the semiconductor substrate and an increase in the number of pixels.
  • a solid-state image sensor of back surface irradiation including a transfer gate, a MOS transistors, and an interconnect layer on a first (front) surface of a semiconductor substrate, and a photoelectric conversion element on a second (back) surface so that the back surface serves as a light-receiving region.
  • a substrate of a solid-state image sensor of back surface irradiation needs to be thinned to a thickness of 3-10 ⁇ m.
  • polishing or etching of a conventional silicon substrate from a back surface is considered, but the means is less controllable in uniformly reducing the thickness of an initial substrate, which is usually 500 ⁇ m, to 10 ⁇ m or less.
  • Japanese Translation of PCT International Application No. 2008-514011 shows a manufacturing method of a solid-state image sensor of back surface irradiation using an SOI wafer including a single crystal silicon layer on a silicon oxide layer.
  • the SOI wafer including the silicon oxide layer formed on a base wafer, and the single crystal silicon layer formed on the silicon oxide layer is used.
  • the method includes forming a photoelectric conversion element on the single crystal silicon layer with a light-receiving section facing the silicon oxide layer of the single crystal silicon layer, forming an interconnect layer on a surface of the single crystal silicon layer which is opposite to the surface closer to the silicon oxide layer, and selectively removing the base wafer under the silicon oxide layer.
  • the SIMOX is a manufacturing method of an SOI wafer utilizing the feature that a silicon oxide layer is formed inside a silicon substrate and a recrystallized silicon layer is formed near the surface of the silicon substrate by ion-implanting highly concentrated oxygen into the silicon substrate with highly accelerated energy and performing heat treatment. This method accurately controls the depth for ion implantation, thereby providing excellent uniformity of the thickness of the recrystallized silicon layer formed near the surface of the silicon substrate.
  • a silicon oxide film is formed on the surface of a silicon substrate, hydrogen ions are implanted via the formed silicon oxide film, and then the silicon oxide film of the silicon substrate is bonded to a base wafer (supporting substrate). After that, heat treatment is performed and the silicon substrate is separated in the implanted position, thereby providing a method (hydrogen ion implantation separation) of forming an SOI wafer.
  • This technique is shown in, e.g., Japanese Patent No. 2959704, or Japanese Patent No. 3385972.
  • a silicon oxide film is formed on at least one of two silicon wafers. Hydrogen ions or noble gas ions are implanted from above a first silicon wafer, thereby forming a defect layer (a sealing layer) inside the silicon wafer. Then, the silicon wafer is adhered to the other silicon wafer via the silicon oxide film and heat treatment (separation heat treatment) is performed to separate one of the wafers to be a thin film using the defect layer as a surface to be cleaved (surface to be separated). With further heat treatment (bonding heat treatment) is performed to strengthen the bonding, thereby forming an SOI wafer.
  • heat treatment separation heat treatment
  • a silicon wafer used in manufacturing an SOI wafer is usually formed by Czochralski (CZ) growth.
  • CZ Czochralski
  • massive polycrystalline silicon is put into a crucible made of quartz and melted by resistance heating in an argon atmosphere.
  • a silicon ingot comes into contact with single crystal silicon as a seed and is pulled up while gradually rotating to manufacture the silicon ingot.
  • the resistivity of silicon is controlled by the concentration of a dopant, but the resistivity in the axial direction and the in-plane direction is difficult to uniform. Variations in concentric resistivity, oxygen concentration, etc. caused by the pull-up of the silicon wafer produced by the CZ growth are referred to as “swirls.”
  • FIG. 9 is a schematic view of a swirl representing the magnitude of resistivity by concentration.
  • SOI wafers manufactured by hydrogen ion implantation separation using silicon wafers produced by the CZ growth are in practical use mainly in logic LSI manufactures. In usually manufactured SOI wafers, variations in resistivity caused by the CZ growth are not problematic.
  • a manufacturing method of a solid-state image sensor of back surface irradiation using an SOI wafer, which is formed by hydrogen ion implantation separation using a silicon wafer produced by CZ growth as a material, will be described below.
  • FIGS. 10A-10E and 11 A- 11 E are cross-sectional views illustrating a manufacturing method of a solid-state image sensor of back surface irradiation using a conventional SOI wafer.
  • a bond wafer 5 made of single crystal silicon is prepared.
  • the bond wafer 5 is made of single crystal silicon produced by CZ growth.
  • P-type impurities are implanted into the bond wafer 5 so that the bond wafer 5 will be a p-well 6 of a completed solid-state image sensor 3 shown in FIG. 11E .
  • the bond wafer 5 is shown in the figure so that the principal surface faces downwards.
  • the bond wafer 5 is thermally oxidized to form a silicon oxide layer 7 . While only the silicon oxide layer 7 on the principal surface is shown in the figure, silicon oxide films are actually formed on the back and side surfaces as well.
  • hydrogen ions are implanted from the principal surface of the bond wafer 5 .
  • Accelerated energy for implanting the hydrogen ions is controlled to adjust the depth of a defect layer 8 , which is caused by the hydrogen ion implantation, from the principal surface of the bond wafer 5 .
  • This determines the thickness of a single crystal silicon layer 9 being an upper layer when an SOI wafer 1 is completed, which will be described later with reference to FIG. 11A .
  • the base wafer 2 is made of single crystal silicon produced by CZ growth.
  • the base wafer 2 and the bond wafer 5 are separated from the back surface, thereby separating part of the bond wafer 5 from the base wafer 2 in the defect layer 8 .
  • the part of the bond wafer 5 separated from the base wafer 2 is returned to the oxidation shown in FIG. 10B , and may be reused in manufacture of another SOI wafer.
  • bonding of the bonded surfaces is strengthen by heat treatment at a temperature of 1000° C.
  • a method of lowering the temperature of the heat treatment by pretreatment with plasma, etc. is also considered.
  • the SOI wafer 1 is completed, which includes the base wafer 2 , the silicon oxide layer 7 , and the single crystal silicon layer 9 .
  • FIG. 11B illustrates forming photodiodes 4 and drains 11 in the single crystal silicon layer 9 which is the uppermost layer of the SOI wafer 1 , and forming read-out gates 10 and interconnects 12 on the single crystal silicon layer 9 to form a solid-state MOS image sensor.
  • photodiodes, charge transfer sections, gate electrodes and interconnects are used instead.
  • the photodiodes 4 are formed by ion-implanting impurities such as arsenic (As), properties (P), etc. into a p-type substrate.
  • the base wafer 2 is removed from the SOI wafer 1 .
  • the base wafer 2 is made of single crystal silicon, it can be easily removed by etching with an alkali solution.
  • the intermediate silicon oxide layer 7 is not etched with the alkali solution, it can be thus processed with thickness accuracy equal to that in manufacturing the SOI wafer 1 .
  • the strength of the wafer is insufficient, and thus, an extra support wafer for reinforcement is to be bonded on the front surface provided with the interconnects 12 , etc.
  • the support wafer is however, not shown in the figure.
  • boron (B + ) ions are implanted from the surface provided with the silicon oxide layer 7 to form a p + type depletion barrier layer 13 near the interface in the single crystal silicon layer 9 between the single crystal silicon layer 9 and the silicon oxide layer 7 .
  • the depletion barrier layer 13 blocks spread of the depletion layers of the photodiodes 4 to the interface with the silicon oxide film and prevents noise electrons generated at interface states from being accumulated at the photodiodes 4 and becoming dark signals.
  • color filters 14 and on-chip microlenses 15 are formed on the silicon oxide layer 7 being the back surface of the SOI wafer 1 . Then, the solid-state image sensor 3 of back surface irradiation is completed.
  • the manufacturing method of the solid-state image sensor of back surface irradiation using the conventional SOI wafer is excellent in uniformly and controllably thinning the silicon wafer.
  • slight variations in the resistivity of the substrate influence characteristics of the individual photodiodes, and lead to variations in sensitivity and the amount of saturated signals.
  • fixed pattern noise occurs in an obtained image due to a swirl shown in FIG. 12 .
  • the present disclosure provides a manufacturing method of a solid-state image sensor implemented by a structure using an SOI wafer made of single crystal silicon formed by epitaxial growth.
  • a manufacturing method of a first solid-state image sensor includes forming a single crystal silicon layer on a principal surface of a first wafer by epitaxial growth; forming a silicon oxide layer on the single crystal silicon layer; forming a defect layer inside the single crystal silicon layer by ion implantation; bonding the second wafer to the silicon oxide layer on the first wafer; forming an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer; forming a photodiode in the single crystal silicon layer; and forming an interconnect layer including a photodiode charge read-out structure on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer.
  • the first solid-state image sensor according to the present disclosure does not include single crystal silicon produced by CZ growth, which inevitably has concentric variations in impurity concentration. This prevents fixed pattern noise occurring in the solid-state image sensor manufactured by a conventional manufacturing method. This enables manufacture of a solid-state image sensor with reduced degradation in the quality of an obtained image.
  • the manufacturing method of the first solid-state image sensor according to the present disclosure may further include, after forming the interconnect layer, selectively etching part of or the entire second wafer with respect to the silicon oxide layer.
  • the photodiode the light-receiving section of the photodiode is formed to face the silicon oxide layer.
  • a manufacturing method of a second solid-state image sensor includes forming a first single crystal silicon layer on a principal surface of a first wafer by epitaxial growth; forming a silicon oxide layer on the first single crystal silicon layer; forming a defect layer inside the first single crystal silicon layer by ion implantation; bonding the second wafer to the silicon oxide layer on the first wafer; forming an SOI wafer including the silicon oxide layer formed on the second wafer and the first single crystal silicon layer formed on the silicon oxide layer by separating the first wafer including the first single crystal silicon layer from the second wafer including the first single crystal silicon layer in the defect layer; forming a second single crystal silicon layer on the first single crystal silicon layer by epitaxial growth; forming a photodiode in the first single crystal silicon layer or the second single crystal silicon layer; and forming an interconnect layer including a photodiode charge read-out structure on a surface of the second single crystal silicon layer which is opposite to the first single crystal silicon layer.
  • the second solid-state image sensor does not include single crystal silicon produced by CZ growth, which inevitably has variations in impurity concentration. This prevents fixed pattern noise occurring in the solid-state image sensor manufactured by a conventional manufacturing method. This enables manufacture of a solid-state image sensor with reduced degradation in the quality of an obtained image. Furthermore, read-out gates, drains, interconnects, etc. of the solid-state image sensor can be formed on the surface of the defect free second single crystal silicon layer, thereby further improving the image quality of the solid-state image sensor.
  • the manufacturing method of the second solid-state image sensor according to the present disclosure may further include, after forming the interconnect layer, selectively etching part of or the entire second wafer with respect to the silicon oxide layer.
  • the photodiode the light-receiving section of the photodiode is formed to face the silicon oxide layer.
  • a manufacturing method of a third solid-state image sensor includes forming a first single crystal silicon layer having impurity concentration of 1 ⁇ 10 17 cm ⁇ 3 or more on a principal surface of a first wafer by epitaxial growth; forming a silicon oxide layer on the first single crystal silicon layer; forming a defect layer inside the first single crystal silicon layer by ion implantation; bonding the second wafer to the silicon oxide layer on the first wafer; forming an SOI wafer including the silicon oxide layer formed on the second wafer and the first single crystal silicon layer formed on the silicon oxide layer by separating the first wafer including the first single crystal silicon layer from the second wafer including the first single crystal silicon layer in the defect layer; forming a second single crystal silicon layer having lower impurity concentration than the first single crystal silicon layer on the first single crystal silicon layer by epitaxial growth; forming a photodiode in the second single crystal silicon layer so that a light-receiving section faces the silicon oxide layer; forming an interconnect layer including a photodio
  • the third solid-state image sensor does not include single crystal silicon produced by CZ growth, which inevitably has variations in impurity concentration. This prevents fixed pattern noise occurring in the solid-state image sensor manufactured by a conventional manufacturing method. This enables manufacture of a solid-state image sensor with reduced degradation in the quality of an obtained image. Furthermore, read-out gates, drains, interconnects, etc. of the solid-state image sensor can be formed on the surface of the defect free second single crystal silicon layer, thereby further improving the image quality of the solid-state image sensor. There is no need to form a depletion barrier layer by ion implantation to perform activation annealing after forming the read-out gates, interconnects, etc. Thus, a negative influence of heat treatment on the interconnects, etc. can be avoided.
  • the first single crystal silicon layer is preferably of a first conductivity type.
  • the second single crystal silicon layer is preferably of a second conductivity type.
  • the photodiode is preferably of the second conductivity type.
  • the first single crystal silicon layer may be of a first conductivity type.
  • the second single crystal silicon layer may be of a second conductivity type.
  • the forming of the photodiode may include forming a well of the first conductivity type in the second single crystal silicon layer.
  • the photodiode may be of the second conductivity type, and may be formed in the well.
  • a solid-state image sensor includes a plate-like single crystal silicon layer formed by epitaxial growth, and including a first surface and a second surface facing the first surface, an interconnect layer provided on the first surface of the single crystal silicon layer and including a photodiode charge read-out structure; and a plurality of photodiodes formed in the single crystal silicon layer so that light-receiving sections face the second surface.
  • the solid-state image sensor according to the present disclosure does not include single crystal silicon produced by CZ growth, which inevitably has variations in impurity concentration. This prevents fixed pattern noise occurring in a conventional solid-state image sensor.
  • the solid-state image sensor according to the present disclosure may further include an insulating film provided on the second surface of the single crystal silicon layer, and color filters provided on the insulating film to correspond to the photodiodes.
  • the solid-state image sensor according to the present disclosure may further include on-chip microlenses provided on the second surface of the single crystal silicon layer to correspond to the photodiodes.
  • the solid-state image sensor according to the present disclosure may further include an insulating film provided on the second surface of the single crystal silicon layer; color filters provided on the insulating film; and on-chip microlenses provided on the color filters to correspond to the photodiodes.
  • a solid-state image sensor does not include single crystal silicon produced by CZ growth, which inevitably has variations in impurity concentration.
  • a solid-state image sensor is obtained, which is free from fixed pattern noise occurring in a solid-state image sensor manufactured by a conventional manufacturing method.
  • FIG. 1 is a cross-sectional view of a solid-state image sensor according to a first embodiment of the present disclosure.
  • FIGS. 2A-2E are cross-sectional views illustrating a manufacturing method of the solid-state image sensor according to the first embodiment in order of steps.
  • FIGS. 3A-3F are cross-sectional views illustrating the manufacturing method of the solid-state image sensor according to the first embodiment in order of steps.
  • FIGS. 4A-4E are cross-sectional views illustrating a manufacturing method of the solid-state image sensor according to a second embodiment in order of steps.
  • FIGS. 5A-5G are cross-sectional views illustrating the manufacturing method of the solid-state image sensor according to the second embodiment in order of steps.
  • FIGS. 6A-6E are cross-sectional views illustrating a manufacturing method of the solid-state image sensor according to a third embodiment in order of steps.
  • FIGS. 7A-7F are cross-sectional views illustrating the manufacturing method of the solid-state image sensor according to the third embodiment in order of steps.
  • FIG. 8 is a schematic view illustrating fixed pattern noise caused by variations in activation of laser annealing.
  • FIG. 9 is a schematic view illustrating variations in impurity concentration in a semiconductor wafer manufactured by conventional CZ growth.
  • FIGS. 10A-10E are cross-sectional views illustrating a manufacturing method of a solid-state image sensor of back surface irradiation using a conventional SOI wafer in order of steps.
  • FIGS. 11A-11E are cross-sectional views illustrating a manufacturing method of a solid-state image sensor of back surface irradiation using a conventional SOI wafer in order of steps.
  • FIG. 12 is a schematic view illustrating fixed pattern noise of a solid-state image sensor of back surface irradiation using a conventional SOI wafer.
  • FIG. 1 illustrates a cross-sectional structure of the solid-state image sensor according to the first embodiment.
  • the solid-state image sensor according to the first embodiment includes a single crystal silicon layer 24 formed by epitaxial growth, and a silicon oxide layer 22 having a surface formed by heat treatment. Impurities are implanted into the single crystal silicon layer 24 to have p-type conductivity for functioning as a p-well 21 .
  • the single crystal silicon layer 24 includes photodiodes 19 and drains 26 .
  • Read-out gates 25 and interconnects 27 are formed on the single crystal silicon layer 24 .
  • An interlayer insulating film 34 is formed on the single crystal silicon layer 24 to cover the read-out gates 25 and the interconnects 27 .
  • the photodiodes 19 are formed by forming n-type regions by implantation of ions such as arsenic, phosphorus, antimony, etc.
  • the light-receiving sections of the photodiodes 19 are formed to face the silicon oxide layer 22 .
  • boron (B + ) ions are implanted from the surface provided with the silicon oxide layer 22 , thereby forming the p + type depletion barrier layer 28 under the single crystal silicon layer 24 .
  • the impurity concentration of the depletion barrier layer 28 varies depending on the impurity concentration of the photodiodes 19 , and usually preferably ranges from 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 (both inclusive). This prevents spread of the depletion layers of the photodiodes 19 to the interface with the silicon oxide layer 22 , and provides the advantage of reducing dark signals generated by accumulating noise electrons occurring in the interface states at the photodiodes 19 .
  • Color filters 29 are formed on the surface of the silicon oxide layer 22 which is opposite to the single crystal silicon layer 24 .
  • On-chip microlenses 30 are formed on the color filters 29 .
  • the solid-state image sensor according to this embodiment does not include single crystal silicon formed by Czochralski (CZ) growth, which inevitably has concentric variations in impurity concentration. This prevents fixed pattern noise to improve image quality.
  • CZ Czochralski
  • FIGS. 2A-2E and 3 A- 3 F illustrate a manufacturing method of the solid-state image sensor according to the first embodiment of the present disclosure in order of steps.
  • a bond wafer 20 made of single crystal silicon is prepared.
  • the conductivity type and the impurity concentration of the bond wafer 20 are not directly related to the p-well 21 of the completed solid-state image sensor 18 shown in FIG. 3F .
  • the bond wafer 20 is shown with the principal surface facing downward.
  • the bond wafer 20 may be made of single crystal silicon produced by CZ growth.
  • the single crystal silicon layer 24 into which p-type impurities are implanted, is disposed on the principal surface of the bond wafer 20 by epitaxial growth.
  • the single crystal silicon layer 24 needs to have a thickness greater than the thickness of the surface on which a solid-state image element is eventually formed. Since a solid-state image sensor using visible light with sensitivity needs to include a substrate with a thickness ranging from several micrometers to ten micrometers, the single crystal silicon layer 24 by epitaxial growth needs to have the deposition thickness ranging from several micrometers to ten micrometers.
  • the bond wafer 20 is thermally oxidized to form the silicon oxide layer 22 . While only the front (lower) surface of the formed silicon oxide layer 22 is shown in the figure, the silicon oxide layer 22 is actually formed on the back and side surfaces of the bond wafer 20 as well.
  • hydrogen ions are implanted to the single crystal silicon layer 24 from the silicon oxide layer 22 to form a defect layer 23 inside the single crystal silicon layer 24 .
  • the bond wafer 20 is separated along the defect layer 23 .
  • accelerated energy in implanting the hydrogen ions is controlled to adjust the depth of the ion implantation, thereby determining the thickness of the single crystal silicon layer 24 in the silicon-on-insulator (SOI) wafer. Therefore, in this embodiment, the depth of the defect layer 23 eventually becomes the thickness of the single crystal silicon forming the solid-state image sensor 18 .
  • the solid-state image sensor 18 of back surface irradiation When the solid-state image sensor 18 of back surface irradiation is formed, it has a thickness ranging from about several micrometers to about ten micrometers as described above. Since the deposition thickness of the single crystal silicon layer 24 by the epitaxial growth shown in FIG. 2B is larger than the thickness of the single crystal silicon forming the solid-state image sensor 18 , the defect layer 23 formed by implanting the hydrogen ions is provided in the single crystal silicon layer 24 formed by epitaxial growth.
  • a base wafer 17 for maintaining the strength of an SOI wafer 16 to be completed in FIG. 3B The surfaces of the prepared base wafer 17 and the single crystal silicon layer 24 are cleaned, and then, the surfaces of the base wafer 17 and the single crystal silicon layer 24 are bonded. At this time, atomic force at the surfaces promotes the bonding only by softly pushing the base wafer 17 and the bond wafer 20 , on which the single crystal silicon layer 24 is deposited, since the surfaces are sufficiently flat.
  • the cleaning aims not only to remove contaminated materials, particles, etc. and to make the surfaces hydrophilic to improve bonding effects.
  • the base wafer 17 may be made of single crystal silicon produced by CZ growth.
  • the base wafer 17 is shown as if it is thinner than the bond wafer 20 for convenience, the base wafer 17 needs to have a thickness for maintaining the strength of the SOI wafer 16 . Therefore, when the diameter is 200 mm or more, a thickness of 500 ⁇ m is usually needed.
  • the bond wafer 20 also needs to have the same degree of thickness as the base wafer 17 to be subjected to the steps to bonding of the bond wafer 20 to the base wafer 17 .
  • the single crystal silicon layer 24 is separated in the defect layer 23 .
  • Part of the bond wafer 20 and the single crystal silicon layer 24 eparated from the base wafer 17 may be returned to the epitaxial growth shown in FIG. 2B and reused in manufacture of another SOI wafer.
  • the temperature of the heat treatment is 400° C. or more in view of the bonding strength, and is preferably about 1000° C.
  • the SOI wafer 16 including the base wafer 17 , the silicon oxide layer 22 , and the single crystal silicon layer 24 is completed as shown in FIG. 3B .
  • the entire single crystal silicon layer 24 is formed by epitaxial growth.
  • the SOI wafer 16 formed in this embodiment has fewer variations in impurity concentration than a conventional single crystal silicon layer produced by CZ growth.
  • the photodiodes 19 and the drains 26 are formed in the single crystal silicon layer 24 , and the read-out gates 25 and the interconnects 27 are formed on the single crystal silicon layer 24 to form a solid-state MOS image sensor.
  • CCD charge coupled device
  • the photodiodes 19 are formed in the p-type single crystal silicon layer 24 .
  • impurities such as arsenic, phosphorus, antimony, etc. are ion-implanted to form an n-type region.
  • the interlayer insulating film 34 is formed on the single crystal silicon layer 24 to cover the read-out gates 25 and the interconnects 27 .
  • the single crystal silicon layer 24 having p-type conductivity is formed by epitaxial growth.
  • the single crystal silicon layer 24 may be of an n-type, and the p-well 21 may be formed by ion implantation etc. in the step shown in FIG. 3C to form the photodiodes 19 etc. in the formed p-well 21 .
  • the base wafer 17 is removed. It is efficient to perform etching with an alkali solution after removing a large part of the base wafer 17 by polishing, dry etching, etc. However, only etching with an alkali solution suffices. Since the base wafer 17 is made of single crystal silicon, removal is facilitated by etching with an alkali solution. Furthermore, the intermediate silicon oxide layer 22 is not etched by an alkali solution, and serves as an etching stopper. This enables processing of thinning films with high accuracy in the case where the thickness of the SOI wafer 16 is determined mainly by the depth of hydrogen ion implantation.
  • the greatest advantage of using the SOI wafer 16 is that the thickness accuracy is dramatically high as compared to the case where a single layer single crystal silicon wafer with a thickness of 500 ⁇ m or more is processed to a thickness of about 10 ⁇ m by combining polishing and etching.
  • Removal of the base wafer 17 may be limited to the light-receiving region of the solid-state image sensor 18 using a masking step.
  • the SOI wafer 16 is preferably strengthen by bonding a quartz wafer etc. as a support wafer on the front surface provided with the interconnects 27 etc. in advance. Note that the support wafer is not shown in the figure.
  • boron ions are implanted from the surface provided with the silicon oxide layer 22 to form a p + type depletion barrier layer 28 near the interface in the single crystal silicon layer 24 between the single crystal silicon layer 24 and the silicon oxide layer 22 .
  • the concentration of the depletion barrier layer 28 varies depending on the impurity concentration of the photodiodes 19 , but usually preferably ranges from 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 (both inclusive). This blocks spread of the depletion layers of the photodiodes 19 to the interface with the silicon oxide film and prevents noise electrons generated at interface states from being accumulated at the photodiodes 19 and becoming dark signals. Note that, even when the step is omitted, basic functions as an image sensor can be obtained although image quality is degraded.
  • color filters 29 and on-chip microlenses 30 are formed on the silicon oxide layer 22 as necessary.
  • the solid-state image sensor 18 of back surface irradiation is completed, which is formed of the single crystal silicon layer 24 by epitaxial growth.
  • the solid-state image sensor 18 does not include single crystal silicon produced by CZ growth, which inevitably has concentric variations in impurity concentration. As a result, the solid-state image sensor free from fixed pattern noise as shown in FIG. 12 can be manufactured.
  • the solid-state image sensor of back surface irradiation has been described, a conventional solid-state image sensor of front surface irradiation can be manufactured similarly using an SOI wafer. Thinning a light-receiving region in a solid-state image sensor of front surface irradiation is advantageous in for example, allowing specific short wavelength to have sensitivity, and utilizing transmitted light of the solid-state image sensor for some purposes.
  • the depletion barrier layer 28 shown in FIG. 3E needs to be formed by implanting boron ions to the surface of the single crystal silicon layer 24 which is opposite to the above-described surface. The formation is performed in the step shown in FIG. 3D .
  • the manufacturing method of the solid-state image sensor of the present disclosure is applicable with a well of the other conductivity type.
  • a manufacturing method of a solid-state image sensor according to a second embodiment will be described hereinafter with reference to FIGS. 4A-4E and 5 A- 5 G.
  • FIGS. 4A-4E and 5 A- 5 G illustrate a manufacturing method of the solid-state image sensor according to the second embodiment of the present disclosure in order of steps.
  • FIGS. 4A-5B are similar to the steps of the first embodiment shown in FIGS. 2A-3B , and explanation thereof will be omitted.
  • the single crystal silicon layer 24 of the first embodiment corresponds to a first single crystal silicon layer 32 in this embodiment.
  • a second single crystal silicon layer 31 is deposited on the first single crystal silicon layer 32 by epitaxial growth. P-type impurities are implanted into the second single crystal silicon layer 31 .
  • the substrate thickness of the solid-state image sensor 18 shown in FIG. 5G the substrate needs to have a thickness ranging from about several micrometers to about ten micrometers in a solid-state image sensor of back surface irradiation. Therefore, where the depth of the defect layer 23 in the first single crystal silicon layer 32 is d 1 , and the thickness of the deposited second single crystal silicon layer 31 in FIG. 5C is d 2 , the sum of d 1 and d 2 needs to be equal to the substrate thickness of the solid-state image sensor 18 .
  • photodiodes 19 and drains 26 are formed on the second single crystal silicon layer 31 , and read-out gates 25 and interconnects 27 are formed on the second single crystal silicon layer 31 to form a solid-state MOS image sensor.
  • a solid-state CCD image sensor photodiodes, charge transfer sections, gate electrodes and interconnects are used instead.
  • impurities such as arsenic, phosphorus, antimony, etc. are ion-implanted in forming the photodiodes 19 to form an n-type region.
  • the interlayer insulating film 34 is formed on the single crystal silicon layer 24 to cover over the read-out gates 25 and the interconnects 27 .
  • the second single crystal silicon layer 31 of n-type conductivity may be formed by epitaxial growth, a p-well 21 may be formed by ion implantation etc., and the photodiodes 19 etc. may be formed in the p-well 21 .
  • the base wafer 17 is removed. It is efficient to perform etching with an alkali solution after removing a large part of the base wafer 17 by polishing, dry etching, etc. However, only etching with an alkali solution suffices. Since the base wafer 17 is made of single crystal silicon, removal is facilitated by etching with an alkali solution. Furthermore, the intermediate silicon oxide layer 22 is not etched by an alkali solution, and serves as an etching stopper. This enables processing of thinning films with high accuracy in the case where the thickness of the SOI wafer 16 is determined mainly by the depth of hydrogen ion implantation.
  • the greatest advantage of using the SOI wafer 16 is that the thickness accuracy is dramatically high as compared to the case where a single layer single crystal silicon wafer with a thickness of 500 ⁇ m or more is processed to a thickness of about 10 ⁇ m by combining polishing and etching.
  • Removal of the base wafer 17 may be limited to the light-receiving region of the solid-state image sensor 18 using a masking step.
  • the SOI wafer 16 is preferably strengthen by bonding a quartz wafer etc. as a support wafer on the front surface provided with the interconnects 27 etc. in advance. Note that the support wafer is not shown in the figure.
  • boron ions are implanted from the surface provided with the silicon oxide layer 22 to form a p + type depletion barrier layer 28 near the interface in the first single crystal silicon layer 32 between the first single crystal silicon layer 32 and the silicon oxide layer 22 .
  • the concentration of the depletion barrier layer 28 varies depending on the impurity concentration of the photodiodes 19 , but usually preferably ranges from 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 (both inclusive). This blocks spread of the depletion layers of the photodiodes 19 to the interface with the silicon oxide layer 22 and prevents noise electrons generated at interface states from being accumulated at the photodiodes 19 and becoming dark signals. Note that, even when the step is omitted, basic functions as an image sensor can be obtained although image quality is degraded.
  • color filters 29 and on-chip microlenses 30 are formed on the silicon oxide layer 22 as necessary.
  • the solid-state image sensor 18 of back surface irradiation is completed, which is formed of the first single crystal silicon layer 32 and the second single crystal silicon layer 31 by epitaxial growth.
  • the solid-state image sensor 18 does not include single crystal silicon produced by CZ growth, which inevitably has concentric variations in impurity concentration. As a result, the solid-state image sensor free from fixed pattern noise as shown in FIG. 12 can be manufactured.
  • the SOI wafer 16 is formed by hydrogen ion implantation separation. A large part of the defect layer 23 due to ion implantation remains on the surface separated by hydrogen ion implantation.
  • threshold voltages vary at the read-out gates 25 due to an increase in interface states, dark outputs increase at the drains 26 , and an increase in contact resistance, variations in resistance, etc. at the interconnects 27 , thereby causing degradation in image equality due to an increase in noise etc. as a solid-state image sensor.
  • the second single crystal silicon layer 31 is formed on a first single crystal silicon layer 32 including a surface on which a large part of the defect layer 23 remains.
  • the read-out gates 25 , the drains 26 , the interconnects 27 , etc. of the solid-state image sensor 18 can be formed on the surface of the defect free second single crystal silicon layer 31 .
  • This improves image quality of the image sensor.
  • epitaxial growth of single crystal silicon is usually performed with silane source gas at a high temperature of 1000° C.
  • hydrogen atoms ion-implanted from the silicon oxide layer 22 into the first single crystal silicon layer 32 desorb to recover defects caused by ion implantation.
  • the interface between the first single crystal silicon layer 32 and the second single crystal silicon layer 31 does not preferably exist in the depletion layers of the photodiodes 19 .
  • the crystal defects remaining inside the photodiodes 19 are the source of dark currents, and cause fixed pattern noise called “white defects.”
  • the thickness d 1 of the separated first single crystal silicon layer 32 is set to be less than the thickness of the depletion barrier layer 28 , thereby positioning the interface between the first single crystal silicon layer 32 and the second single crystal silicon layer 31 inside the depletion barrier layer 28 .
  • the structure is formed in which the interface between the first single crystal silicon layer 32 and the second single crystal silicon layer 31 does not exist in the depletion layers of the photodiodes 19 . This structure further improves image quality of a solid-state image sensor.
  • a manufacturing method of a solid-state image sensor according to a third embodiment will be described hereinafter with reference to FIGS. 6A-6E and 7 A- 7 F.
  • FIGS. 6A-6E and 7 A- 7 F illustrate a manufacturing method of the solid-state image sensor according to the third embodiment of the present disclosure in order of steps.
  • FIG. 8 is a schematic view illustrating fixed pattern noise caused by variations in activation of laser annealing.
  • the steps shown in FIGS. 6A-7E are similar to the steps of the second embodiment shown in FIGS. 4A-5E , and explanation thereof will be omitted.
  • the first single crystal silicon layer 32 according to the second embodiment corresponds to a first depletion barrier single crystal silicon layer 33 in this embodiment.
  • the first depletion barrier single crystal silicon layer 33 is made of single crystal silicon having the same conductivity type as the depletion barrier layer 28 shown in FIG. 5F and impurity concentration equal to that of the depletion barrier layer 28 , i.e., having P + type conductivity and impurity concentration ranging from 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 (both inclusive).
  • P + type conductivity and impurity concentration ranging from 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 (both inclusive).
  • the defect layer 23 formed by hydrogen ion implantation has a depth equal to the thickness of the depletion barrier layer 28 of the first and second embodiments, thereby allowing the first depletion barrier single crystal silicon layer 33 to function as the depletion barrier layer 28 of the first and second embodiments.
  • implantation of B + ions is unnecessary.
  • this embodiment differs from the other embodiments.
  • impurity atoms need to be located in stable positions in the single crystal silicon by heat treatment generally called “activation annealing.”
  • the activation annealing needs to be performed by heat treatment at a temperature of 800° C. or more.
  • the temperature applied to the entire wafer is considered based on the melting point of the interconnects 27 . Heating at a temperature of 500° C. or more is difficult. As a result, only part of ion-implanted impurities can be activated.
  • laser annealing As a method of solving this problem, heating called “laser annealing” can be used.
  • a wafer is scanned with intense laser light to heat the entire surface of the wafer. This locally heats one of the surfaces of the wafer.
  • the first problem is heat variations caused by scanning with laser light.
  • the maximum radius of laser light ranges from hundreds of micrometers to several millimeters, which is smaller than a solid-state image sensor and greater than a pixel size of the solid-state image sensor.
  • the heat variations caused by scanning of the laser light lead to variations in activation of impurities to cause variations in conductivity characteristics.
  • the second problem is that the front surface (upper surface) of the wafer 16 has a high temperature, even when the SOI wafer 16 is irradiated with laser light from the back surface, since the thickness of the formation region of the photodiodes 19 ranges from several micrometers to ten micrometers.
  • the layout of the interconnects 27 at the front surface is not limited by arrangement of pixels.
  • the wafer 16 transmits part of laser light from the back surface and the interconnects 27 reflects the part of laser light from the back surface, the temperature of the irradiated part with the reflected light rises more than the other parts. This may cause variations in activation of impurities reflecting the layout of the interconnects 27 , and fixed pattern noise of other types than the fixed pattern noise caused by scanning variations may be a concern. While the above-described problems may be solved, when laser annealing techniques with a short wavelength is developed, the heat treatment in processing the back surface is an essential problem of a solid-state image sensor of back surface irradiation.
  • the second single crystal silicon layer 31 is of p-type conductivity and the photodiodes 19 is of n-type conductivity
  • the second single crystal silicon layer 31 may be of the n-type conductivity.
  • a p-well is formed in the second single crystal silicon layer 31 by ion implantation etc., and the photodiodes 19 of n-type conductivity may be provided in the formed p-well.
  • the solid-state image sensor and the manufacturing method of the solid-state image sensor according to the present disclosure provide a solid-state image sensor not including single crystal silicon produced by CZ growth which inevitably has concentric variations in impurity concentration. This prevents fixed pattern noise, and thus, the solid-state image sensor and the manufacturing method of the solid-state image sensor according to the present disclosure are particularly useful as a solid-state image sensor and a manufacturing method etc. of the solid-state image sensor using an SOI substrate.

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