US20110204517A1 - Semiconductor Device with Vias Having More Than One Material - Google Patents

Semiconductor Device with Vias Having More Than One Material Download PDF

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Publication number
US20110204517A1
US20110204517A1 US12/710,399 US71039910A US2011204517A1 US 20110204517 A1 US20110204517 A1 US 20110204517A1 US 71039910 A US71039910 A US 71039910A US 2011204517 A1 US2011204517 A1 US 2011204517A1
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United States
Prior art keywords
semiconductor die
cte
conductive material
substrate
semiconductor
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Abandoned
Application number
US12/710,399
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English (en)
Inventor
Shiqun Gu
Yiming Li
Steve J. Bezuk
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Qualcomm Inc
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Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to US12/710,399 priority Critical patent/US20110204517A1/en
Assigned to QUALCOMM INCORPORATED reassignment QUALCOMM INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BEZUK, STEVE J., GU, SHIQUN, LI, YIMING
Priority to TW100106057A priority patent/TW201145486A/zh
Priority to PCT/US2011/025813 priority patent/WO2011106349A1/en
Publication of US20110204517A1 publication Critical patent/US20110204517A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

Definitions

  • the present description relates, in general, to vias and, more specifically, to vias having two or more conductive materials therein.
  • TSVs Through Silicon Vias
  • TSVs are generally substantially vertical interconnects used to make electrical connections through a semiconductor.
  • TSVs can be used to couple devices within the same die or in different but adjacent (e.g., stacked) dies.
  • a via should have low resistance since it carries signals between the chips.
  • Many conventional TSVs use copper for a conductor because of its low resistance. However, the use of copper presents some challenges.
  • PVD Physical Vapor Deposition
  • CTE Coefficient of Thermal Expansion
  • silicon a common material for semiconductor substrates
  • CTE Coefficient of Thermal Expansion
  • silicon a common material for semiconductor substrates
  • the copper will bend more than silicon bends so that the copper material in a via may “pop up” affecting material above the via.
  • thermal changes in the shape of copper materials of vias have caused delamination with low-K dielectric layers, and even breaking metal lines that couple to vias.
  • delamination occurs between the copper in the vias and silicon dioxide liners in the vias.
  • FIG. 1 is an illustration of a conventional TSV 100 .
  • the TSV 100 includes copper that interfaces with the silicon 102 and with the item 101 .
  • the copper interfaces with the silicon 102 through an insulating liner 103 , such as Tetraethylorthosilicate (TEOS).
  • TEOS Tetraethylorthosilicate
  • the item 101 can include anything that is placed above the TSV 100 , such as a low-K dielectric layer, a metal line, and/or the like.
  • FIG. 1 is not drawn to scale, as a conventional TSV may be 50 to 100 microns tall and six microns in diameter, whereas a metal line on top of a TSV may be about 0.2 microns thick.
  • the TSV 100 has expanded due to thermal changes, and its expansion has affected the item 101 by pushing the item 101 away from the silicon 102 , a phenomenon referred to as “delamination.” Delamination can also occur at the interface of the silicon 102 and the copper of the TSV 100 . Furthermore, the deformation of the item 102 can result in breaking in some instances due to the steep ninety degree drop from the copper of the TSV 100 to the silicon 102 .
  • Tungsten has a lower CTE than does copper, and the CTE of tungsten is closer to that of silicon, but there is a penalty for using tungsten.
  • the resistance of tungsten is higher than that of copper.
  • CVD plasma processes there is a maximum thickness of about one micron, which can be inadequate for a six micron via.
  • a method for fabricating a via within a semiconductor die includes the step of removing semiconductor material to create a hole through a substrate of the semiconductor die. The method further includes the steps of depositing a first conductive material, having a first coefficient of thermal expansion (CTE), within the hole and depositing a second conductive material, having a second CTE, over at least a portion of the first conductive material.
  • the first CTE is between the second CTE and a CTE of the substrate of the semiconductor die.
  • a semiconductor die has a via within a substrate material of the semiconductor die.
  • the via includes first means for conducting electrical signals having a first Coefficient of Thermal Expansion (CTE) and second means for conducting electrical signals between the first conducting means and the substrate material of the semiconductor die.
  • the second conducting means has a second CTE between the first CTE and a CTE of the material of the semiconductor die.
  • FIG. 4 is an illustration of the exemplary process adapted for fabricating a TSV in a semiconductor device according to one embodiment of the disclosure.
  • FIG. 5 shows an exemplary wireless communication system in which an embodiment of the disclosure may be advantageously employed.
  • the TSV 210 includes two conductive materials.
  • One conductive material is copper 211
  • the other conductive material is a buffer metal 212 , which is disposed between the copper 211 and the substrate 201 .
  • the buffer metal 212 has a CTE between that of the substrate 201 (i.e., about 3 ppm per degree Celsius for silicon) and that of copper (i.e., 16 ppm per degree Celsius).
  • Various suitable buffer materials include, but are not limited to, tungsten (CTE of about 4.5 ppm per degree Celsius) and nickel (CTE of about thirteen ppm per degree Celsius).
  • the presence of the buffer metal 212 can provide several structural enhancements. For instance, the stress at the buffer/liner (e.g., tungsten/silicon dioxide) interface and the stress at the filler/buffer (e.g., copper/tungsten) will be reduced due to the intermediate CTE of the buffer metal 212 . Also, the pushing force applied by the TSV 210 on items above/below it can be reduced. Both enhancements are explained in more detail with respect to FIG. 3 .
  • the TSV 300 includes features that are different than features of the all-copper TSV 100 of FIG. 1 .
  • the TSV 300 includes less copper than does the TSV 100 .
  • Less copper means less thermal expansion for the TSV 300 .
  • the TSV 300 has a more gradual CTE transition from the copper 311 to the substrate 302 , with the buffer metal 312 providing an intermediate CTE between the copper 311 and the substrate 302 .
  • the more gradual transition results in a more gradual deformation of the item 301 , thereby improving mechanical reliability by reducing the incidence of breakage and delamination.
  • the lower CTE of the buffer metal 312 leads to reduced incidence of delamination between the buffer metal 312 and the via liner, e.g., silicon dioxide, and between the copper 311 and the buffer metal 312 .
  • Dies according to various embodiments may be fabricated in any of a variety of ways.
  • a technique called “via first” is performed.
  • the via first method involves forming the TSVs in a substrate before other fabrication of circuitry (e.g., transistors) occurs.
  • a pattern of vias is etched or drilled into a fraction of the depth of the base substrate.
  • the vias are then filled with a buffer metal and another conductive material, such as copper.
  • Circuit fabrication follows, which can include high-temperature processes to properly dope the semiconductor material.
  • the back side of the substrate containing the TSVs is ground down to expose the TSVs.
  • circuitry fabrication takes place before the TSVs are formed.
  • the circuitry contains interconnect pads that will be coupling points for the TSVs.
  • TSVs are created by either etching or drilling into the pad through the depth of the substrate or etching or drilling from the back side of the substrate to the pad.
  • the TSV is then filled with a buffer metal and another conductive material.
  • a via first technique the front end of the line processing is performed first, then the vias are fabricated, followed by the back end of the line processing.
  • the via last approach the front end of the line processing is performed first, then back end of the line processing is performed, then vias are fabricated through the stack.
  • Another approach is referred to as “via middle,” in which TSVs are formed after the circuitry is formed but before back end of the line processing is performed.
  • An advantage of via middle and via last techniques is that the TSVs in such techniques are not exposed to the extreme temperatures of the doping process.
  • Various embodiments are not limited to any particular method for fabricating TSVs and semiconductor devices, as any method now known or later developed to fabricate TSVs can be used.
  • a first conductive material is deposited within the hole.
  • Various techniques can be used, including PVD techniques and CVD techniques.
  • PVD techniques including PVD techniques and CVD techniques.
  • plasma CVD may be used, though the scope of embodiments is not limited to tungsten nor to any particular technique for deposition of the first conductive material.
  • a second conductive material is deposited over at least a portion of the first conductive material.
  • the second conductive material is deposited within the space on the inner surface of the first conductive material.
  • Examples of a second conductive material include, but are not limited, to copper and silver.
  • block 403 may include Electrochemical Plating (ECP) processes to deposit the copper, though the scope of embodiments is not limited to any particular process.
  • block 403 may include filling in the remainder of the via with the second conductive material.
  • the method 400 is shown as a series of discrete blocks, the disclosure is not so limited. Various embodiments may add, omit, modify, or rearrange the actions of the blocks 401 - 403 . For instance, any method for fabricating dies can be used, including, e.g., via first, via last, and via middle techniques. Furthermore, some embodiments may include integrating the semiconductor die into a chip package with another die and installing the chip package into a larger device, such as a device shown in FIG. 5 .
  • block 402 may include depositing two or more different buffer materials in the TSV.
  • Various embodiments may provide one or more advantages over conventional designs that use vias with only a single conductive material. For instance, as mentioned above, various embodiments ameliorate the temperature-induced deformation of vias, thereby reducing the incidence of delamination at interfaces and metal line cracking.
  • the barrier/seed deposition processes of conventional techniques can be omitted.
  • the buffer metal layers themselves can sometimes be used as a barrier and seed.
  • the buffer metal layer deposition can sometimes be performed by various CVD processes (depending on the particular metals used for the buffer layers), which have a lower cost and better step coverage than PVD processes for conventional designs. Improved step coverage performance can facilitate the use of smaller vias, such as those of two microns or less in diameter.
  • FIG. 5 shows an exemplary wireless communication system 500 in which an embodiment of the disclosure may be advantageously employed.
  • FIG. 5 shows three remote units 520 , 530 , and 540 and two base stations 550 , 560 .
  • the remote units 520 , 530 , and 540 include improved semiconductor processor devices 525 A, 525 B, and 525 C, respectively, which in various embodiments include vias according to the embodiments above.
  • improved semiconductor devices are also included in base stations 550 , 560 .
  • FIG. 5 shows an exemplary wireless communication system 500 in which an embodiment of the disclosure may be advantageously employed.
  • FIG. 5 shows three remote units 520 , 530 , and 540 and two base stations 550 , 560 .
  • the remote units 520 , 530 , and 540 include improved semiconductor processor devices 525 A, 525 B, and 525 C, respectively, which in various embodiments include vias according to the embodiments above.
  • improved semiconductor devices are also included in base stations 550 , 560 .
  • FIG. 5 shows the forward link signals 580 from the base stations 550 , 560 and the remote units 520 , 530 , and 540 and the reverse link signals 590 from the remote units 520 , 530 , and 540 to base stations 550 , 560 .
  • the methodologies described herein may be implemented by various components depending upon the application. For example, these methodologies may be implemented in hardware, firmware, software, or any combination thereof.
  • the processing units may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, electronic devices, other electronic units designed to perform the functions described herein, or a combination thereof.
  • ASICs application specific integrated circuits
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLDs programmable logic devices
  • FPGAs field programmable gate arrays
  • processors controllers, micro-controllers, microprocessors, electronic devices, other electronic units designed to perform the functions described herein, or a combination thereof.
  • the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein.
  • Any machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein.
  • software codes may be stored in a memory and executed by a processor unit.
  • Memory may be implemented within the processor unit or external to the processor unit.
  • the term “memory” refers to any type of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to any particular type of memory or number of memories, or type of media upon which memory is stored.
  • such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US12/710,399 2010-02-23 2010-02-23 Semiconductor Device with Vias Having More Than One Material Abandoned US20110204517A1 (en)

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US12/710,399 US20110204517A1 (en) 2010-02-23 2010-02-23 Semiconductor Device with Vias Having More Than One Material
TW100106057A TW201145486A (en) 2010-02-23 2011-02-23 Semiconductor device with vias having more than one material
PCT/US2011/025813 WO2011106349A1 (en) 2010-02-23 2011-02-23 Semiconductor device with vias having more than one material

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Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130015504A1 (en) * 2011-07-11 2013-01-17 Chien-Li Kuo Tsv structure and method for forming the same
US9659858B2 (en) 2011-07-29 2017-05-23 Tessera, Inc. Low-stress vias
US9214425B2 (en) 2011-07-29 2015-12-15 Tessera, Inc. Low-stress vias
US10283449B2 (en) 2011-07-29 2019-05-07 Tessera, Inc. Low stress vias
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
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