US20100053922A1 - Micropackaging method and devices - Google Patents

Micropackaging method and devices Download PDF

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Publication number
US20100053922A1
US20100053922A1 US12/523,811 US52381108A US2010053922A1 US 20100053922 A1 US20100053922 A1 US 20100053922A1 US 52381108 A US52381108 A US 52381108A US 2010053922 A1 US2010053922 A1 US 2010053922A1
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Prior art keywords
component
micro
substrate
packaging
connections
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Thorbjorn Ebefors
Edvard Kalvesten
Tomas Bauer
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Silex Microsystems AB
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Silex Microsystems AB
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Assigned to SILEX MICROSYSTEMS AB reassignment SILEX MICROSYSTEMS AB ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAUER, TOMAS, EBEFORS, THORBJORN, KALVESTEN, EDVARD
Publication of US20100053922A1 publication Critical patent/US20100053922A1/en
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0077—Other packages not provided for in groups B81B7/0035 - B81B7/0074
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/008—Aspects related to assembling from individually processed components, not covered by groups B81C3/001 - B81C3/002
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Definitions

  • the present invention relates to packaging of components for electronic devices, in particular devices requiring small components, such as but not limited to electrical and micromechanical surface micromachined oscillators for computers, mobile phones and the like.
  • Certain components for surface mounting on circuit boards must be packaged in protective casings, quite often in vacuum or other controlled atmosphere/ambient and also need to be provided with connector legs for mounting or solder bumps for surface mounting.
  • Today most encapsulating casings are made of polymers or ceramic materials. The latter is commonly used for packaged components that are hermetically sealed.
  • the thickness of the package has an inherent lower limit. For e.g. mobile phone applications thickness is a vital parameter, and thus it would be desirable to further reduce the component thicknesses.
  • the smallest dimensions are dependent on the dimensions and the pitch between the interconnecting vias to the outside of the package.
  • Package-through vias with small dimensions and small separation/pitch is desired to further reduce the package size.
  • the object of the invention is to enable further miniaturization of such packaged components.
  • the present invention provides a method of micro-packaging a component.
  • At least a first and second substrate is provided of which the first substrate is a semiconductor substrate being provided with at least one electrical through connection.
  • a compartment is formed in either one or a plurality of the substrates by etching.
  • a component is provided above the first semiconductor substrate so that it covers the at least one through wafer connections and will be located within the compartment.
  • the component is connected to at least one through wafer connection and the substrates are joined to form a sealed micro-packaged device.
  • P There may also be provided a plurality of through wafer connections.
  • the substrates are semiconductor substrates.
  • the substrates comprising through wafer connections are thick enough to easily be handled during the manufacturing.
  • a device is a micro-packaged electronic or micromechanic device that comprises a thin walled casing which encloses a compartment. Electrical through connections through the bottom of the casing are connected to an electronic or micromechanic component and the micro-packaged device is hermetically sealed for maintaining a desired atmosphere, suitable vacuum inside.
  • the casing is made of a semiconducting material and the component is located immediately above the through connections.
  • the thickness of packaged components can be reduced at least by 50%.
  • Hermetic sealing can be made at wafer-level using wafer bonding which significantly simplifies the manufacturing process thereby reducing costs.
  • FIG. 1 shows in cross-section an embodiment of a device according to the invention
  • FIG. 2 shows another embodiment of a device according to the invention
  • FIG. 3 is a perspective view of a micro-packaged device seen from the bottom side
  • FIG. 4 is perspective view of a micro-packaged device from above with the lid taken off;
  • FIG. 5 a is a perspective view similar to FIG. 3 but with a component to be mounted inside shown in shadow lines;
  • FIG. 5 b illustrates a similar device as in FIG. 8( a ) but having an insulating trench between the vias;
  • FIG. 6 illustrates packaging of monolithically integrated components with high density via structures
  • FIG. 7 shows an array of contiguous vias
  • FIG. 8 illustrates the geometry for corner etching of insulating trenches
  • FIG. 9 shows a via with trench redundancy
  • FIG. 10 a illustrates (not to scale) an embodiment wherein the micro-packaged device is made by forming the vias on a flat wafer and making a depression in the “lid wafer” to form a compartment for the component;
  • FIG. 10 b illustrates an embodiment wherein the micro-packaged device is made by forming a compartment by making a depression in both the via wafer and in the “lid wafer”;
  • FIG. 10 c illustrates an embodiment wherein the compartment of the micro-packaged device is made by etching a hole in an intermediate substrate
  • FIG. 11 illustrates an embodiment wherein a discrete component is surface mounted on the via wafer
  • FIG. 12 a illustrates an embodiment wherein the component is provided using surface micromachining
  • FIG. 12 b illustrates an embodiment wherein the component is connected to one through wafer connection and in addition directly to the via wafer;
  • FIG. 13 illustrates a micro-packaged component manufactured using a SOI wafer and having an insulating trench separating through wafer connections
  • FIG. 14 illustrates a micro-packaged device according to the invention wherein the component is mounted on the “lid wafer”
  • FIG. 15 illustrates a bulk micromachined component integrated with an intermediate substrate.
  • the invention is based on the use of electrical through connections (or “vias”), which enables connection of packaged micro-components to circuit boards or to other components with the provision of bulky connector legs or pins, and wafer-level hermetic encapsulation.
  • electrical through connection and via are interchangeably used in this application.
  • the starting wafers having said vias are semiconductor wafers, more preferably single crystalline silicon wafers, however not limited to this.
  • semiconductor wafer also comprises other wafer materials typically used in the field, such as glass wafers and ceramic wafers.
  • wafer and substrate are interchangeably used throughout this application since processing preferably is made on wafer level, i.e. many devices are manufactured in parallel.
  • the packaged component is made by using a wafer having been provided with vias in accordance with the teachings of the International Patent Publication WO 2004/084300 A1 (Silex Microsystems), the content of which is incorporated herein in its entirety.
  • the invention of WO2004/084300 relates to a method of making an electrical through connection between a first (top) and a second (bottom) surface of a semiconductor substrate. The method comprises creating a trench in the first surface and establishing an insulating enclosure entirely separating a portion of said substrate, defined by said trench, i.e. an insulated through connection.
  • interposer One product manufactured according the method is usable as a starting substrate, a so called interposer, for further manufacturing of micro-electronic and/or micro-mechanic devices.
  • interposer One advantage of this kind of product (interposer) is that the through connections are made of the wafer material and therefore are suitable for the processing usually applied to such wafers, i.e. the wafers can withstand temperatures, chemicals that commonly are used in conventional processing of semiconductor wafers.
  • Another advantage of a wafer having these vias is that the wafer may have a thickness of 300-700 ⁇ m, which makes it possible to handle the wafers during the further processing.
  • Another kind of starting substrates with pre-made vias is a so called SOI (silicon on insulator) wafer, wherein the pre-made vias are made in the device layer of the wafer, i.e. not extending entirely through the whole wafer.
  • SOI silicon on insulator
  • the starting substrate for the process according to the invention is a wafer 1 having pre-made vias 2 , as can be seen in FIGS. 1 and 2 .
  • FIGS. 1 and 2 These figures and the following figures are not drawn to scale and serve to illustrate the invention.
  • the starting wafer should be thicker than about 300 ⁇ m in order to provide enough rigidity to enable handling of the wafer during processing without risk of breaking it.
  • the starting wafer comprising the through wafer connections has a thickness of >100 ⁇ m, preferably >200 ⁇ m, more preferably >300 ⁇ m, still more preferred >400 ⁇ m, and most preferred >500 ⁇ m.
  • the wafer is first subjected to a patterning to define the compartments 3 in which the components 4 are to be mounted.
  • Example of components are e.g. all kinds of MEMS devices (sensors and actuators), either in discrete form or monolithically integrated on silicon; capacitors and/or resistors of various materials; EMC Components such as EMI Filters, Transient Voltage Suppressors; Timing Devices such as Crystal Units, Clock Oscillators, TCXO, VCXO, High Precision Oscillators for Industrial Applications, Ceramic Resonators, SAW Resonators; Crystal Products of various kinds; Filters such as SAW Filters, Monolithic Crystal Filters; RF Modules such as Antenna Switch Module; Piezo Products such as Shock Sensors, Piezoelectric Acoustic Generator Elements, Piezo Buzzers.
  • MEMS devices sensors and actuators
  • capacitors and/or resistors of various materials EMC Components such as EMI Filters, Transient Voltage Suppressors
  • compartment 3 refers to a volume that has been formed in one or a plurality of substrates in order to receive a component, which subsequently is encapsulated therein.
  • the compartment 3 may, before the encapsulation, be a depression 3 a or a hole 3 b in one or in a plurality of the substrates ( 1 , 10 , 11 ).
  • a suitable etch is applied to the patterned wafer, and a suitably shaped depression, typically rectangular but not limited to this, is thus formed in any of the via wafer or the lid wafer or in both.
  • An advantage with an etching process as compared to the prior art milling, is that it is possible to make very sharp corners in the “box”-like depression, and furthermore silicon processing using lithography and etching enables making very small “boxes” with accurate dimensions.
  • a second pattern is applied to define mounting members corresponding to the vias 2 , i.e. the surface of the vias 2 are covered with etch resistant material.
  • a second etch is applied to etch a deeper depression, whereby protruding members 2 are formed.
  • the depression is suitably 150 ⁇ m deep, and the height of the protruding members is suitably of the order 20 ⁇ m, but these measures can of course vary depending on the application in question.
  • pads 5 or bumps of gold (Au), solder, AuSn., PbSn, etc. are formed by any suitable method such as plating, sputtering etc. If the box is made in the lid wafer 10 these bumps 5 are preferably made on the flat via wafer 1 which simplifies the manufacturing.
  • the component 4 to be mounted in the protective casing can be attached directly to the through wafer connections 2 e.g. by soldering, ultrasonic welding, gluing and wire bonding, in an automated processing using standard surface mounting machines. “Directly” is for the purpose of this application interpreted to mean that there is no additional routing needed to form a contact pad, but as illustrated in FIG. 1 there may be e.g. pads 5 or bumps in-between the component 4 and the through wafer connection 2 .
  • the component 4 can be place immediately above the through connections 2 .
  • the entire wafer 1 is put in a vacuum and a lid 10 is applied to cover the entire wafer 1 .
  • a lid 10 is applied to cover the entire wafer 1 .
  • FIG. 3 illustrates a micro-packaged device having large contact areas 8 on the bottom side of the device.
  • the routing 7 connects the large contact areas 8 with the through connections 2 which extends into the sealed package.
  • a “frame” 9 of gold on the lid wafer corresponding to the size of the package i.e. a strip of gold having the same dimensions as the package, such that when the lid wafer is aligned to the component wafer, pressure and heat is applied, there will be a eutectic bonding between the lid 10 and the silicon in the wafer 1 .
  • the insulating layer 6 -T is not applied.
  • the gold can be applied to the layer 6 -T and instead having the lid “silicon clean”, i.e. letting the silicon in the lid 10 bond to the gold on the component wafer 1 .
  • a second method is to apply a gold layer on both the lid wafer 10 and the component wafer 1 and apply what is referred to as a thermocompression bonding process.
  • a solder e.g. PbSn or AuSn
  • PbSn or AuSn can be applied on one of the wafers ( 1 , 10 , 11 ) and gold on the other and a soldering process is made.
  • the bonded wafers can be grinded or polished to reduce the total thickness to a desired thickness suitable for the application in question.
  • a desired thickness suitable for the application in question.
  • E.g. for mobile phones thin packages are essential.
  • an insulating layer 6 -B of e.g. oxide, or any other suitable material is applied on the back side of the wafer 1 .
  • This layer could have been applied before any other processing is done, as could the insulting layer 6 -T on the top side of the wafer.
  • openings are made by patterning/etching to expose the via to enable contacting to other components or to a circuit board.
  • a metallization 7 of e.g. Al that contacts the via material and can be provided as narrow contact strips from the via to the edges of the entire packaged structure.
  • solder Pb/Sn, Au/Sn, etc.
  • the package can be provided with so called Under Bump Metallization (UBM) and the solder provided on the circuit board, but the solder can also be provided on the package.
  • UBM Under Bump Metallization
  • the wafers are cut up in individual micro-packaged components by e.g. sawing.
  • the bump structures are not made from the vias 2 .
  • the depression 3 is made in one etching step, either on the via wafer or the lid wafer or both (the two latter embodiments are schematically illustrated in FIG. 10 ).
  • gold bumps 5 ′ are provided such that they exhibit the same height as the protruding members 2 in FIG. 1 . These gold bumps 5 ′ can then be used for attaching a component 4 in a similar fashion as described in connection with FIG. 1 .
  • FIG. 5 a illustrates a component 4 which is provided immediately above a depression 3 a forming a compartment 3 in a a first semiconductor substrate 1 comprising two through connections extending entirely through the first substrate 1 to the bottom side thereof. The through connections are protruding into the depression.
  • a second substrate 10 is arranged above the component 4 . After surface mounting of the component directly to the through wafer connections the compartment is sealed by joining the substrates together to form a sealed micro-packaged device.
  • FIG. 5 b illustrates a similar arrangement as shown in FIG. 5 a but the first substrate having the through connections 2 is a SOI substrate.
  • the first substrate 1 comprises an insulated trench 14 extending entirely through the first substrate 1 .
  • the insulating trench 14 is electrically insulating one portion of the first substrate from another, each portion comprising one of the two through wafer connections 2 .
  • the capacitive coupling between the through connections 2 is reduced and in addition, due to the insulating layer between the bulk Si layer and the device layer of the SOI substrate there is a vertical electrical insulation in the device.
  • 100 is a “lid wafer” on which a movable switch 102 is provided, comprising a flexible membrane (the flexing during actuation is shown with a broken line).
  • 101 is a wafer comprising an array of high-density vias 103 a - e.
  • 103 a is a “dummy” via used for etch load compensation
  • 103 b is used for actuation purposes
  • 103 c is a signal via
  • 103 d is coupled to ground
  • 103 e is another actuation via
  • 104 a and 104 b are electrostatic actuation pads
  • 105 designates Au pads for thermo compression bonding.
  • 106 is a UBM and 107 is a solder bump.
  • 108 are sawing traces.
  • FIG. 6 illustrates the wafer level packaging according to the invention which enables a considerable decrease in the pitch distance between two neighbouring vias. This is a great advantage that can be obtained when silicon is used for fabricating the hermetic sealed wafer through-connections.
  • the lid wafer that preferably is a silicon wafer or a transparent glass wafer, micro structures (e.g. switches or micro mirrors) are integrated in large array configurations using surface micromachining technologies well known to the man skilled in art.
  • the signal contacts ( 104 b ) on the membrane are individually switched by electrostatic actuation pads ( 104 a ).
  • electrostatic actuation pads are needed.
  • Wafer level encapsulation of these microstructures under vacuum (or other controlled ambient) is obtained by bonding the LID wafer and via wafer together.
  • wafer level bonding alternatives are:
  • Si—Si, SiO—Si or SiO—SiO or other alternative isolating materials such as SiN) for fusion bonding (optional plasma enhanced low temp bonding)
  • Si-glass for anodic bonding (optional Al on Si for Al/glass anodic bonding)
  • bonding materials on the wafer are (but not limited to): conventional sputter/evaporation metallization followed by photolithography and etching, lift-off, shadow evaporation/sputtering, screen printing, preform.
  • Bonding alternatives as well as methods for applying the materials are well known for the skill man in art.
  • solder bumping is preferably made by the photo lithography and electroplating process.
  • a typical centre-to-centre distance for circular vias is about 250 ⁇ m, if trenches are 10-30 ⁇ m wide and the diameter of vias is 100 ⁇ m.
  • the starting wafer is typically 300-450 ⁇ m in order to be processed without a handling wafer attached thereto.
  • the typical trench width is 15-20 ⁇ m and the via diameter is about 50-100 ⁇ m.
  • Closely spaced through wafer connections can also be accomplished if using a SOI-substrate having a device layer thickness of about 50-200 ⁇ m, as illustrated in FIG. 5 b.
  • a typical trench width is about 5 ⁇ m and the via diameter is about 20 ⁇ m.
  • FIG. 7 the inventors have devised a method of making very closely spaced vias, and an example of such vias 2 is schematically shown in FIG. 5 as a top view of a portion of a wafer or substrate 1 having the novel vias provide therein (see also FIG. 6 ).
  • the filled trenches are designated 54 .
  • the idea is to let neighbouring vias share a common insulated trench as at 56 in FIG. 7 .
  • a typical centre-to-centre distance for these vias is about 50 ⁇ m, if trenches are 5-10 ⁇ m wide and the side dimension of vias is, typically 35 ⁇ m.
  • etch load compensation in accordance with an aspect of the invention there will always be made a redundant via at each end of the array. These outermost vias in the array will not be used in operation of the array, but are only present for the above mentioned reason. See FIG. 6 , item 103 a.
  • the corners are given a special geometry, which corresponds to the encircled part shown at 58 in FIG. 7 .
  • the optimal shape can be determined based on etching parameters used for each specific case. Shaping the trenches like this will ideally result in trenches having essentially the same depth, or at least will the etch not be too deep in the corners of the trench structure.
  • a still further problem can occur with very long trenches, i.e. where the “via” itself occupies a large surface area on the wafer. Namely, in view of the trenches in a standard situation are about 8 ⁇ m wide, it will suffice if one single particle with conductive properties gets “caught” in the trench and forms a bridge between the via and the surrounding wafer material in order that the via will be short-circuited. The probability of this happening becomes increasingly larger as the length of the trench increases, and will inevitably cause high rejection rates and thus low manufacturing yields.
  • two or more trenches are made as concentric circles or squares or rectangles or any other geometric shape on a wafer or substrate 1 , enclosing a via 2 , and each circle is connected to the next by radially extending trenches, as shown in FIG. 9 , wherein three concentric trenches are connected by the radial trenches.
  • FIG. 10 a - c illustrates different ways to accomplish a compartment 3 for a component 4 to be hermetically sealed.
  • a first substrate 1 having at least one through connection 2 extending entirely through the substrate 1 is provided.
  • the component 4 is directly attached and connected to the through connection 2 . Thereby the through connection is covered by the component 4 .
  • a depression 3 a is etched in a second substrate 10 .
  • the depression defines the compartment 3 and by joining the substrates 1 , 10 the compartment 3 is sealed.
  • depressions 3 a are etched in each of the first substrate and the second substrate 1 , 10 , whereby the depressions 3 a define the compartment 4 .
  • the substrates 1 , 10 are joined together and the compartment 3 containing the component 4 is sealed.
  • a intermediate substrate 11 is provided in addition to the first and second substrates 1 , 10 .
  • a hole 3 b defining the compartment 3 is etched in the intermediate substrate 11 and the three substrates 1 , 10 , 11 are joined whereby the compartment 3 containing the component 4 is sealed.
  • a depression 3 a may be etched in either one or both of the first and second substrates 1 , 10 in addition to the hole 3 b etched in the intermediate substrate. Thereby the depression/depressions and the hole 3 b together define the compartment 4 .
  • the micro-packaged device 15 comprises a first and second semiconductor substrate 1 , 10 , which are joined together.
  • the first semiconductor substrate 1 comprises a depression 3 a , whereby the first and the second semiconductor substrates 1 , 10 form a sealed compartment 3 in-between.
  • Trough connections 2 are extending entirely through the first substrate 1 from the bottom of the compartment 3 to the other side of the first substrate 1 .
  • a micro-electronic or a micro-mechanic component 4 such as e.g. an ASIC or a resonator crystal, is attached directly to the through connections 2 within the sealed compartment 4 .
  • a micro-component 4 is attached directly on pads located on two through connections 2 , which are extending entirely through a first semiconductor substrate.
  • a getter plate 12 is deposited on the first substrate 1 within the compartment 3 .
  • the through connections 2 are by way of example made in the same material as the first substrate and are electrically insulated by a trench enclosing each via connection.
  • the first and the second substrates are by way of example joined by an Au—Si eutectic joint.
  • a first substrate 1 and a second substrate 10 are provided.
  • the first substrate is at least 300 ⁇ m, preferably at least 500 ⁇ m thick, and comprises the electrical through connections 2 , which are extending entirely though the first substrate 1 .
  • the second substrate 10 may in this embodiment be thinner than the first substrate 1 since it is not processed to such a large extent that the handling becomes a problem, preferably the thickness is however at least 300 ⁇ m.
  • FIG. 11 shows only one micro-packaged device 15 , it is to be understood that there preferably is made a large number of micro-packaged devices in parallel in one batch, i.e.
  • the first and second substrates 1 , 10 are wafers being large enough for making the large number of micro-packaged devices.
  • the wafers should have a sufficient thickness and the through connections 2 are made of the wafer material, in order to be compatible with conventional processing steps used in the field.
  • a depression 3 a is formed in the first substrate 1 using photolithography and etching, such as wet etching or dry etching, in such way that the through connections 2 are exposed in the bottom of the depression 3 a .
  • the depth of the depression 3 a is dependent on the thickness of the component to be packaged, but typically the thickness is about 150 ⁇ m.
  • the through connections 2 at the bottom of the depression 3 a of the first substrate 1 are bumped and the component 4 is attached to the bumps.
  • a gold layer is applied on the second wafer, at least in an area intended to be brought in contact with the first substrate to form the joint.
  • the second substrate 10 or the lid is aligned to the first substrate 1 and pressure and heat is applied, which gives a eutectic bonding between the first and second substrates 1 , 10 and a sealed compartment 3 containing the component 4 is formed.
  • the eutectic bonding is performed at relatively low temperatures (about 360° C.), which makes it a suitable bonding method when the attachment of the component 4 have yielded a temperature sensitive joint between the component and the through wafer connection.
  • a controlled atmosphere i.e. vacuum, protective gas, etc.
  • the long term stability of this controlled atmosphere is dependent on the gas permeability of the joint between the wafers of the package, the gas permeability of the wafers and release of gases from components or other structures enclosed within the compartment.
  • a getter means 17 in the form of e.g. a plate, a thin film, a bump, etc. is enclosed within the compartment to remove gas molecules that find its way into the compartment.
  • a person skilled in the art is familiar with the different getter materials used, since such is commonly used in other hermetically sealed devices.
  • FIG. 12 illustrates one embodiment of a micro-packaged device according to the invention similar to the micro-packaged device illustrated in Fig. A, although with a different kind of component 4 .
  • the component 4 is a monolithically integrated component, by way of example a polysilicon structure, intended to be used e.g. as a resonator structure or accelerometer structure.
  • the polysilicon structure attached to the through wafer connections of the first substrate 1 but is in between these attachment points free-hanging.
  • the polysilicon structure is fabricated on the first substrate after etching the depression 3 a using surface micromachining, which may comprise e.g. sacrificial oxide etching to form a gap between the polysilicon structure and the bottom of the depression 3 a .
  • Such a polysilicon structure can in contrast to e.g. an assembled ASIC withstand high temperatures and since neither the first substrate 1 or the second substrate 10 comprise any other temperature sensible parts, high temperature joining processes such as fusion bonding can be used.
  • the first and the second substrate 1 , 10 of the micro-packaged device in FIG. 12 are activated in the processing step that removes the sacrificial oxide to and thereafter immediately aligned and fusion bonded, preferably at a temperature of about 900-1000° C. to form a sealed package.
  • fusion bonded micro-packaged devices can be made even smaller.
  • the fusion bonding provides a good sealing and the sealing area can be made smaller than for e.g. thermocompression bonding.
  • the bond strength may be so high that a possible breakage of the package will likely take place in the substrate and not in the joint between the substrates.
  • FIG. 13 illustrates one embodiment of a micro-packaged device according to the present invention similar to the micro-packaged device in FIG. 12 .
  • the packaged component 4 is formed in the same material as the first substrate 1 .
  • the first substrate 1 comprises a buried oxide layer dividing the first substrate 1 in a device layer and a bulk layer.
  • the thickness of the device layer is usually thinner than the bulk layer, by way of example 100 ⁇ m and 300-400 ⁇ m, respectively.
  • the through connections 2 extend through the device layer and ends in the buried oxide layer which has been removed in an area about the through connections 2 .
  • a single crystalline micro-mechanic structure such as a resonator structure or an accelerometer structure, formed by etching of the bulk layer and sacrificial etching of the buried oxide layer, is attached to the through connections 2 .
  • the micro-mechanic structure is formed, preferably in the same process step, in a depression 3 that is etched out in the bulk layer of the first substrate 1 .
  • the first and second substrate 1 , 10 and the constituting parts thereof allow fusion bonding, which preferably is performed immediately after activation in the step of sacrificial etching of the buried oxide layer.
  • a vapour of HF may be used for this activation.
  • the bulk micromachined component is electrically anchored to the first substrate by a filled hole 20 extending entirely through the component 4 and the buried oxide layer between the component and the first substrate 1 down to the through wafer connections.
  • the filled hole 20 is filled with polysilicon which provides an electrical connection between the component 4 and the through connections 2 .
  • FIG. 14 illustrates a micro-packaged device according to the invention comprising a first substrate made of a semiconductor material such as monocrystalline silicon and a second substrate 10 made of glass.
  • the first substrate 1 comprises an array of through connections 2 extending entirely through the first substrate 1 to form electrical connections between the bottom of a depression to a second (lower) side of the first substrate 1 .
  • the first and the second substrate 1 , 10 are joined together to form a sealed compartment 3 , wherein a microelectromechanical component 4 is integrated on the surface of the second substrate 10 within the compartment 3 .
  • the first and the second substrates 1 , 10 each comprises e.g.
  • a gold layer which is patterned in order to connect at least one of the through connections 2 in the first substrate 1 with the microelectromechanical component 4 on the second substrate 10 .
  • the first and second substrates 1 , 10 are joined together using thermocompression bonding by applying a high pressure at about 400° C., whereby the gold layers adhere to each other.
  • the micro-packaged device 15 is formed using a first and a second substrate 1 , 10 and at least one intermediate substrate 11 .
  • At least the first substrate 1 comprises through connections 2 extending entirely through the first substrate 1 into the compartment 3 .
  • the compartment 3 for the component 4 is formed by etching a hole through the intermediate substrate and joining the first, the second and the intermediate substrate.
  • FIG. 15 illustrates one embodiment of this kind.
  • the component 4 is monolithically integrated with the intermediate substrate 11 and is formed by bulk micromachining of the intermediate substrate 11 .
  • the bulk micromachining both defines the shape of the component 4 and defines at least a portion of the compartment wherein the component 4 is to be packaged.
  • the component or the through wafer connections of the first substrate 1
  • a micro-packaged device according to the invention can be made much smaller than a conventional micro-packaged device for a given component size.
  • Usually ceramic materials are used to package and hermetically seal electrical and micromechanical components, but the smallest packages available are about 3 ⁇ 2 mm 2 and with a thickness of more than 1 mm. This technology does not allow substantial miniaturisation.
  • the present invention provides substantially smaller packages.
  • the thickness is preferably less than 0.6 mm and the lateral dimensions are preferably less than 1 ⁇ 1 mm 2 , depending on the size of the component.

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TW200848359A (en) 2008-12-16
WO2008091220A1 (fr) 2008-07-31
TWI461348B (zh) 2014-11-21
EP2106617A1 (fr) 2009-10-07
EP2106617B1 (fr) 2021-06-02
EP2121511A4 (fr) 2014-07-02
SE0700172L (sv) 2008-07-26
US8598676B2 (en) 2013-12-03
WO2008091221A2 (fr) 2008-07-31
EP2121511A2 (fr) 2009-11-25
SE533579C2 (sv) 2010-10-26

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