US20050062120A1 - Packaging microelectromechanical structures - Google Patents

Packaging microelectromechanical structures Download PDF

Info

Publication number
US20050062120A1
US20050062120A1 US10/980,516 US98051604A US2005062120A1 US 20050062120 A1 US20050062120 A1 US 20050062120A1 US 98051604 A US98051604 A US 98051604A US 2005062120 A1 US2005062120 A1 US 2005062120A1
Authority
US
United States
Prior art keywords
structures
cavity
mems
microelectromechanical
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/980,516
Inventor
Qing Ma
Valluri Rao
John Heck
Daniel Wong
Michele Berry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/980,516 priority Critical patent/US20050062120A1/en
Publication of US20050062120A1 publication Critical patent/US20050062120A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Definitions

  • This invention relates generally to microelectromechanical structures (MEMS) and particularly to techniques for packaging MEMS.
  • MEMS components such as varactors, switches and resonators need to be packaged in a hermetic environment.
  • hermetic packaging protects the MEMS components from the outside environment.
  • a second approach is to use a glass frit to bond a wafer containing the MEMS components to a cover.
  • this technique requires high temperature bonding that may not be suitable for all components utilized in some MEMS applications.
  • the glass frit occupies a large area that increases the size of the resulting product and therefore increases its costs.
  • the glass frit bonding technology uses wire bonds for electrical connections that may not be adequate in some applications, such as high frequency applications.
  • FIG. 1 is an enlarged cross-sectional view of one embodiment of the present invention
  • FIG. 2 is an enlarged cross-sectional view of a component of one embodiment of the present invention at an early stage of manufacturing
  • FIG. 3 is an enlarged cross-sectional view of another component of one embodiment of the present invention at an early stage of manufacture
  • FIG. 4 is an enlarged cross-sectional view of the components shown in FIGS. 2 and 3 , having been joined, but still at an early stage of manufacturing;
  • FIG. 5 shows one technique for processing the structure shown in FIG. 4 in accordance with one embodiment of the present invention
  • FIG. 6 shows another technique for processing the component shown in FIG. 4 in accordance with one embodiment of the present invention.
  • FIG. 7 is an enlarged cross-sectional view of one embodiment after further processing.
  • a MEMS component 12 such as a radio frequency (RF) MEMS component, including as examples a varactor, a switch or a resonator, may be formed on a semiconductor structure 14 having a layer 16 .
  • a plurality of bond pads 15 and 16 may be provided on the layer 16 .
  • the MEMS component 12 may be surrounded on one side by a printed circuit board 32 having a cavity 33 conforming to the shape of the semiconductor structure 14 in some embodiments. A gap may be maintained between the board 32 and the structure 14 .
  • a plurality of solder bumps 34 may bond the printed circuit board 32 to a semiconductor structure 22 through bond pads 36 and 20 a.
  • the semiconductor structure 22 may have internal electrical interconnection layers 40 that interconnect bond pads 15 , 20 a and 36 on the structure 14 , the board 32 and the semiconductor structure 22 . Thus, electrical connections are possible between the various components.
  • a solder ring 18 b completely encircles the MEMS device 12 , defining a sealed or hermetic cavity 42 for the device 12 , in one embodiment. In another embodiment, the cavity 42 may be at a reduced pressure.
  • the vias 18 a provide electrical interconnections between the structure 14 and the structure 22 .
  • the package 10 may be processed by forming the MEMS device 12 on the structure 14 over a layer 16 as shown in FIG. 2 .
  • a plurality of contacts 15 may be provided as well.
  • the layer 16 may provide electrical connections between the contacts 15 and the MEMS device 12 through the semiconductor structure 14 in some embodiments.
  • the semiconductor structure 22 may include an internal electrical interconnection layer 40 that electrically couples pads 20 a and vias 18 a in one embodiment of the present invention.
  • a sealing ring 18 b may be coupled to a pad 20 , in accordance with one embodiment of the present invention.
  • the sealing ring 18 b is not necessarily for electrical purposes but rather forms a vertical sealing wall between the structures 14 and 22 for hermetically sealing the MEMS device 12 inside the package 10 . Electrical interconnections to the outside would be provided by the vias 18 a coupled to the contacts 20 a, in one embodiment of the present invention.
  • the contacts 20 a may be solder or gold bumps and the ring 18 b may be made of solder or gold, in some embodiments.
  • the structures 14 and 22 have been combined with the structure 22 positioned on top of the structure 14 .
  • the combined package 10 may be heated to fuse the vias 18 to the pads 15 and the ring 18 b to the bond ring 20 .
  • surface mount techniques using temperatures of 300° C. or less may be used.
  • a semiconductor wafer including a plurality of structures 14 may be combined with a semiconductor wafer including a plurality of structures 22 .
  • each pair of structures 14 and 22 are simultaneously bonded to one another across the wafers.
  • the solder ring 18 b makes contact with bond ring 20 on the semiconductor structure 14 , forming a hermetic seal around the MEMS device 12 in the cavity 24 .
  • the cavity 24 may be a vacuum cavity.
  • the electrical vias 18 a extend from the structure 22 to the structure 14 making electrical contact with the contacts 15 , in one embodiment of the present invention.
  • electrical connections may be made to and from the MEMS device 12 , circumventing the sealing ring 18 b via the buried interconnection layer 40 within the structure 22 in one embodiment.
  • the ring 18 a is surface mounted to a pad 20 in turn coupled to the interconnection layer 40 which finally couples to a pad 20 a on the exterior of the sealing ring 18 b relative to the MEMS device 12 .
  • the interconnection layer 40 may be provided in either or both of the structures 14 and 22 in other embodiments.
  • the structure shown in FIG. 4 may be made at relatively low temperatures, for example under 300° C. in some embodiments, by using surface mounting techniques for combining the structures 14 and 22 .
  • lateral portions of the semiconductor structure 14 may be cut away.
  • a thick saw as indicated, may be utilized to saw through the semiconductor structure 14 separating it from its wafer and a dicing saw may be utilized to separate the structure 22 from the rest of its wafer.
  • both of the structures 14 and 22 may be severed along cut lines as indicated in FIG. 6 .
  • a cut through the structure 22 may be primarily to sever the structure 22 from the rest of its wafer.
  • the cut through structure 14 reveals bond pads 20 a on the structure 22 .
  • a pair of electrical bond pads 20 a may be provided, but in another embodiment, any number of contacts 20 a may be utilized as necessary.
  • the interconnection layer 40 acts as a buried contact to allow electrical connections from the MEMS device 12 in the interior of the cavity 24 to the outside world without compromising the sealed nature of the cavity 24 .
  • FIG. 7 After severing, in accordance with any of a variety of techniques including those shown in FIGS. 5 and 6 , the resulting structure is shown in FIG. 7 , with the pads 20 a fully accessible.
  • a printed circuit board 32 may be bonded to the semiconductor structure 22 . This may be done using solder bumps 34 and surface mount bonding pads 36 on the printed circuit board 32 to make electrical connection to the interconnection layers 40 through the bond pads 20 a.
  • the structure 14 may be left free floating for thermal compatibility or a suitable adhesive or filler may be used between the board 32 and the structure 14 .
  • the processing temperatures may be reduced. Lower processing temperatures may be important in processing MEMS components in some embodiments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

A MEMS device may be formed in a hermetic cavity by sealing a pair of semiconductor structures to one another, enclosing the MEMS device. The two structures may be coupled using surface mount techniques as one example, so that the temperatures utilized may be compatible with many MEMS applications. Electrical interconnection layers in one or the other of these structures may be utilized to allow electrical interconnections from the exterior world to the MEMS components within the cavity.

Description

    BACKGROUND
  • This invention relates generally to microelectromechanical structures (MEMS) and particularly to techniques for packaging MEMS.
  • In some cases, MEMS components such as varactors, switches and resonators need to be packaged in a hermetic environment. For example, particularly with radio frequency MEMS components, there may be a need for hermetic packaging. Such packaging protects the MEMS components from the outside environment.
  • Conventionally, two approaches have been utilized for hermetic packaging of MEMS components. Ceramic packages with cavities that may be sealed are used in the defense industry. This approach, while reliable, may be cost prohibitive for many commercial applications.
  • A second approach is to use a glass frit to bond a wafer containing the MEMS components to a cover. However, this technique requires high temperature bonding that may not be suitable for all components utilized in some MEMS applications. In some cases, the glass frit occupies a large area that increases the size of the resulting product and therefore increases its costs. In some cases, the glass frit bonding technology uses wire bonds for electrical connections that may not be adequate in some applications, such as high frequency applications.
  • Thus, there is a need for better ways to package MEMS components.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an enlarged cross-sectional view of one embodiment of the present invention;
  • FIG. 2 is an enlarged cross-sectional view of a component of one embodiment of the present invention at an early stage of manufacturing;
  • FIG. 3 is an enlarged cross-sectional view of another component of one embodiment of the present invention at an early stage of manufacture;
  • FIG. 4 is an enlarged cross-sectional view of the components shown in FIGS. 2 and 3, having been joined, but still at an early stage of manufacturing;
  • FIG. 5 shows one technique for processing the structure shown in FIG. 4 in accordance with one embodiment of the present invention;
  • FIG. 6 shows another technique for processing the component shown in FIG. 4 in accordance with one embodiment of the present invention; and
  • FIG. 7 is an enlarged cross-sectional view of one embodiment after further processing.
    • DETAILED DESCRIPTION
  • Referring to FIG. 1, a MEMS component 12, such as a radio frequency (RF) MEMS component, including as examples a varactor, a switch or a resonator, may be formed on a semiconductor structure 14 having a layer 16. A plurality of bond pads 15 and 16 may be provided on the layer 16. The MEMS component 12 may be surrounded on one side by a printed circuit board 32 having a cavity 33 conforming to the shape of the semiconductor structure 14 in some embodiments. A gap may be maintained between the board 32 and the structure 14.
  • A plurality of solder bumps 34 may bond the printed circuit board 32 to a semiconductor structure 22 through bond pads 36 and 20 a. The semiconductor structure 22 may have internal electrical interconnection layers 40 that interconnect bond pads 15, 20 a and 36 on the structure 14, the board 32 and the semiconductor structure 22. Thus, electrical connections are possible between the various components.
  • A solder ring 18 b completely encircles the MEMS device 12, defining a sealed or hermetic cavity 42 for the device 12, in one embodiment. In another embodiment, the cavity 42 may be at a reduced pressure. The vias 18 a provide electrical interconnections between the structure 14 and the structure 22.
  • In accordance with one embodiment of the present invention, the package 10 may be processed by forming the MEMS device 12 on the structure 14 over a layer 16 as shown in FIG. 2. In addition, a plurality of contacts 15 may be provided as well. The layer 16 may provide electrical connections between the contacts 15 and the MEMS device 12 through the semiconductor structure 14 in some embodiments.
  • Referring to FIG. 3, the semiconductor structure 22 may include an internal electrical interconnection layer 40 that electrically couples pads 20 a and vias 18 a in one embodiment of the present invention. In addition, a sealing ring 18 b may be coupled to a pad 20, in accordance with one embodiment of the present invention. The sealing ring 18 b is not necessarily for electrical purposes but rather forms a vertical sealing wall between the structures 14 and 22 for hermetically sealing the MEMS device 12 inside the package 10. Electrical interconnections to the outside would be provided by the vias 18 a coupled to the contacts 20 a, in one embodiment of the present invention. The contacts 20 a may be solder or gold bumps and the ring 18 b may be made of solder or gold, in some embodiments.
  • Referring to FIG. 4, the structures 14 and 22 have been combined with the structure 22 positioned on top of the structure 14. The combined package 10 may be heated to fuse the vias 18 to the pads 15 and the ring 18 b to the bond ring 20. In some embodiments, surface mount techniques using temperatures of 300° C. or less may be used.
  • In one embodiment, a semiconductor wafer including a plurality of structures 14 may be combined with a semiconductor wafer including a plurality of structures 22. In that embodiment each pair of structures 14 and 22 are simultaneously bonded to one another across the wafers.
  • At this stage, the solder ring 18 b makes contact with bond ring 20 on the semiconductor structure 14, forming a hermetic seal around the MEMS device 12 in the cavity 24. In some embodiments, the cavity 24 may be a vacuum cavity.
  • The electrical vias 18 a extend from the structure 22 to the structure 14 making electrical contact with the contacts 15, in one embodiment of the present invention. Thus, electrical connections may be made to and from the MEMS device 12, circumventing the sealing ring 18 b via the buried interconnection layer 40 within the structure 22 in one embodiment. For example, as shown in FIG. 4, the ring 18 a is surface mounted to a pad 20 in turn coupled to the interconnection layer 40 which finally couples to a pad 20 a on the exterior of the sealing ring 18 b relative to the MEMS device 12. However the interconnection layer 40 may be provided in either or both of the structures 14 and 22 in other embodiments.
  • In this way, electrical connections may be made to the MEMS device 12 through the exterior contacts 20 a. In addition, the structure shown in FIG. 4 may be made at relatively low temperatures, for example under 300° C. in some embodiments, by using surface mounting techniques for combining the structures 14 and 22.
  • Referring to FIG. 5, in accordance with one embodiment of the present invention, in order to access the contacts 20 a, lateral portions of the semiconductor structure 14 may be cut away. In one embodiment, a thick saw, as indicated, may be utilized to saw through the semiconductor structure 14 separating it from its wafer and a dicing saw may be utilized to separate the structure 22 from the rest of its wafer.
  • In accordance with another embodiment, both of the structures 14 and 22 may be severed along cut lines as indicated in FIG. 6. For example, a cut through the structure 22 may be primarily to sever the structure 22 from the rest of its wafer. The cut through structure 14 reveals bond pads 20 a on the structure 22. In this case, a pair of electrical bond pads 20 a may be provided, but in another embodiment, any number of contacts 20 a may be utilized as necessary.
  • Again, the interconnection layer 40 acts as a buried contact to allow electrical connections from the MEMS device 12 in the interior of the cavity 24 to the outside world without compromising the sealed nature of the cavity 24.
  • After severing, in accordance with any of a variety of techniques including those shown in FIGS. 5 and 6, the resulting structure is shown in FIG. 7, with the pads 20 a fully accessible.
  • Next, as shown in FIG. 1, a printed circuit board 32 may be bonded to the semiconductor structure 22. This may be done using solder bumps 34 and surface mount bonding pads 36 on the printed circuit board 32 to make electrical connection to the interconnection layers 40 through the bond pads 20 a. The structure 14 may be left free floating for thermal compatibility or a suitable adhesive or filler may be used between the board 32 and the structure 14.
  • Again, by using surface mount techniques, the processing temperatures may be reduced. Lower processing temperatures may be important in processing MEMS components in some embodiments.
  • While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (11)

1. A method comprising:
forming a microelectromechanical structure device on a first structure;
hermetically sealing said first structure to a second structure; and
providing an interconnection layer in one of said first and second structures to allow electrical interconnections to the microelectromechanical structure device.
2. The method of claim 1 including securing said first structure to said second structure using temperatures of 300° C. or less.
3. The method of claim 1 including securing said first structure to said second structure using surface mount techniques.
4. The method of claim 1 including forming a wall on one of said first or second structures that encircles said microelectromechanical structure device.
5. The method of claim 4 including surface mounting said wall on one of said structures to the other of said structures.
6. The method of claim 1 including forming a cavity between said first and second structures and providing a pillar which extends from one of said structures and electrically connects to the other of said structures.
7. The method of claim 6 including surface mounting said pillar on one of said structures to the other of said structures.
8. The method of claim 1 including forming a cavity between said first and second structures with said microelectromechanical structure device in said cavity, providing an electrical connection in said cavity to said microelectromechanical structure device and providing a contact on one of said first or second structures outside said cavity but electrically coupled to said microelectromechanical structure device through said interconnection layer.
9. The method of claim 1 including forming a contact electrically coupled to said interconnection layer and severing one of said first or second structures to expose the contact on the other of said first or second structures.
10. The method of claim 1 including surface mounting a printed circuit board to one of said structures sandwiching the other of said structures between the one of said structures and said printed circuit board.
11-30 (Canceled).
US10/980,516 2002-03-26 2004-11-03 Packaging microelectromechanical structures Abandoned US20050062120A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/980,516 US20050062120A1 (en) 2002-03-26 2004-11-03 Packaging microelectromechanical structures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/106,728 US6852926B2 (en) 2002-03-26 2002-03-26 Packaging microelectromechanical structures
US10/980,516 US20050062120A1 (en) 2002-03-26 2004-11-03 Packaging microelectromechanical structures

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/106,728 Division US6852926B2 (en) 2002-03-26 2002-03-26 Packaging microelectromechanical structures

Publications (1)

Publication Number Publication Date
US20050062120A1 true US20050062120A1 (en) 2005-03-24

Family

ID=28452551

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/106,728 Expired - Lifetime US6852926B2 (en) 2002-03-26 2002-03-26 Packaging microelectromechanical structures
US10/980,516 Abandoned US20050062120A1 (en) 2002-03-26 2004-11-03 Packaging microelectromechanical structures

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/106,728 Expired - Lifetime US6852926B2 (en) 2002-03-26 2002-03-26 Packaging microelectromechanical structures

Country Status (5)

Country Link
US (2) US6852926B2 (en)
AU (1) AU2003212969A1 (en)
MY (1) MY138751A (en)
TW (1) TW588421B (en)
WO (1) WO2003083883A2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070235501A1 (en) * 2006-03-29 2007-10-11 John Heck Self-packaging MEMS device
US20070290308A1 (en) * 2006-06-14 2007-12-20 Magnachip Semiconductor Ltd. Package of MEMS device and method for fabricating the same
US20090079037A1 (en) * 2007-09-20 2009-03-26 Heribert Weber Micromechanical component and method for producing a micromechanical component
US20100068854A1 (en) * 2005-10-03 2010-03-18 Analog Devices, Inc. MEMS Switch Capping and Passivation Method
US20100147294A1 (en) * 2007-05-15 2010-06-17 Portaero, Inc. Devices and methods to maintain the patency of an opening relative to parenchymal tissue of the lung

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7870788B2 (en) * 2002-01-25 2011-01-18 Kinemetrics, Inc. Fabrication process and package design for use in a micro-machined seismometer or other device
TW569407B (en) * 2002-05-17 2004-01-01 Advanced Semiconductor Eng Wafer-level package with bump and method for manufacturing the same
US7084724B2 (en) * 2002-12-31 2006-08-01 The Regents Of The University Of California MEMS fabrication on a laminated substrate
TWI275168B (en) * 2003-06-06 2007-03-01 Sanyo Electric Co Semiconductor device and method for making the same
US7170155B2 (en) * 2003-06-25 2007-01-30 Intel Corporation MEMS RF switch module including a vertical via
US20050170609A1 (en) * 2003-12-15 2005-08-04 Alie Susan A. Conductive bond for through-wafer interconnect
US6936918B2 (en) * 2003-12-15 2005-08-30 Analog Devices, Inc. MEMS device with conductive path through substrate
JP2005180930A (en) * 2003-12-16 2005-07-07 Ricoh Co Ltd Semiconductor sensor device and its manufacturing method
WO2005062356A1 (en) * 2003-12-24 2005-07-07 Hitachi, Ltd. Device and method of manufacturing the same
US7129417B2 (en) * 2004-04-29 2006-10-31 International Business Machines Corporation Method and structures for implementing customizable dielectric printed circuit card traces
US7608534B2 (en) * 2004-06-02 2009-10-27 Analog Devices, Inc. Interconnection of through-wafer vias using bridge structures
US7183622B2 (en) * 2004-06-30 2007-02-27 Intel Corporation Module integrating MEMS and passive components
US7422962B2 (en) * 2004-10-27 2008-09-09 Hewlett-Packard Development Company, L.P. Method of singulating electronic devices
US7442570B2 (en) 2005-03-18 2008-10-28 Invensence Inc. Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom
US7508063B2 (en) * 2005-04-05 2009-03-24 Texas Instruments Incorporated Low cost hermetically sealed package
JP5253159B2 (en) * 2005-06-24 2013-07-31 デューク・ユニヴァーシティ Direct drug delivery system based on thermoresponsive biopolymer
US7243833B2 (en) * 2005-06-30 2007-07-17 Intel Corporation Electrically-isolated interconnects and seal rings in packages using a solder preform
JP2007059470A (en) * 2005-08-22 2007-03-08 Sony Corp Semiconductor device and its manufacturing method
US7358615B2 (en) * 2005-09-30 2008-04-15 Intel Corporation Microelectronic package having multiple conductive paths through an opening in a support substrate
US20070114643A1 (en) * 2005-11-22 2007-05-24 Honeywell International Inc. Mems flip-chip packaging
US7449765B2 (en) * 2006-02-27 2008-11-11 Texas Instruments Incorporated Semiconductor device and method of fabrication
WO2007119206A2 (en) * 2006-04-13 2007-10-25 Nxp B.V. A method for manufacturing an electronic assembly; an electronic assembly, a cover and a substrate
US7524693B2 (en) * 2006-05-16 2009-04-28 Freescale Semiconductor, Inc. Method and apparatus for forming an electrical connection to a semiconductor substrate
US8159059B2 (en) * 2006-08-25 2012-04-17 Kyocera Corporation Microelectromechanical device and method for manufacturing the same
US20080087979A1 (en) * 2006-10-13 2008-04-17 Analog Devices, Inc. Integrated Circuit with Back Side Conductive Paths
EP2011762B1 (en) * 2007-07-02 2015-09-30 Denso Corporation Semiconductor device with a sensor connected to an external element
JP2009074979A (en) * 2007-09-21 2009-04-09 Toshiba Corp Semiconductor device
KR100959454B1 (en) * 2007-12-10 2010-05-25 주식회사 동부하이텍 Semiconductor device and method for fabricating the same
US7932515B2 (en) * 2008-01-03 2011-04-26 D-Wave Systems Inc. Quantum processor
US20090194861A1 (en) * 2008-02-04 2009-08-06 Mathias Bonse Hermetically-packaged devices, and methods for hermetically packaging at least one device at the wafer level
TWI419239B (en) * 2008-11-19 2013-12-11 Miradia Inc Method and structure for forming a gyroscope and accelerometer
JP4858547B2 (en) * 2009-01-09 2012-01-18 株式会社デンソー Semiconductor device and manufacturing method thereof
US7919842B2 (en) * 2009-03-17 2011-04-05 Texas Instruments Incorporated Structure and method for sealing cavity of micro-electro-mechanical device
US8247253B2 (en) * 2009-08-11 2012-08-21 Pixart Imaging Inc. MEMS package structure and method for fabricating the same
US8058106B2 (en) * 2009-09-04 2011-11-15 Magic Technologies, Inc. MEMS device package with vacuum cavity by two-step solder reflow method
US8296940B2 (en) * 2010-04-19 2012-10-30 General Electric Company Method of forming a micro pin hybrid interconnect array
US8865497B2 (en) 2010-06-25 2014-10-21 International Business Machines Corporation Planar cavity MEMS and related structures, methods of manufacture and design structures
US8567246B2 (en) 2010-10-12 2013-10-29 Invensense, Inc. Integrated MEMS device and method of use
US8947081B2 (en) 2011-01-11 2015-02-03 Invensense, Inc. Micromachined resonant magnetic field sensors
US8860409B2 (en) 2011-01-11 2014-10-14 Invensense, Inc. Micromachined resonant magnetic field sensors
US9664750B2 (en) 2011-01-11 2017-05-30 Invensense, Inc. In-plane sensing Lorentz force magnetometer
CN102649536A (en) * 2011-02-25 2012-08-29 永春至善体育用品有限公司 Structure-enhancing and sensitivity-increasing method for micro-machined components
JP5605347B2 (en) * 2011-11-01 2014-10-15 株式会社デンソー Manufacturing method of semiconductor device
JP2014057125A (en) * 2012-09-11 2014-03-27 Seiko Epson Corp Electronic device, method of manufacturing the same, and oscillator
US9764946B2 (en) 2013-10-24 2017-09-19 Analog Devices, Inc. MEMs device with outgassing shield
US9162874B2 (en) * 2014-01-22 2015-10-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method forming the same
US11257774B2 (en) * 2014-08-31 2022-02-22 Skyworks Solutions, Inc. Stack structures in electronic devices including passivation layers for distributing compressive force
CN107408516A (en) 2015-02-11 2017-11-28 应美盛股份有限公司 Integrated using the 3D of Al Ge eutectic bonding connection components
US9971970B1 (en) 2015-04-27 2018-05-15 Rigetti & Co, Inc. Microwave integrated quantum circuits with VIAS and methods for making the same
JP6702019B2 (en) * 2016-06-22 2020-05-27 株式会社ジェイテクト Semiconductor device
US10192850B1 (en) 2016-09-19 2019-01-29 Sitime Corporation Bonding process with inhibited oxide formation
WO2018106942A1 (en) 2016-12-07 2018-06-14 D-Wave Systems Inc. Superconducting printed circuit board related systems, methods, and apparatus
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
US11678433B2 (en) 2018-09-06 2023-06-13 D-Wave Systems Inc. Printed circuit board assembly for edge-coupling to an integrated circuit
US11647590B2 (en) 2019-06-18 2023-05-09 D-Wave Systems Inc. Systems and methods for etching of metals
CN111392683B (en) * 2020-02-28 2024-03-15 上海集成电路研发中心有限公司 Infrared detector structure and manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096421A1 (en) * 2000-11-29 2002-07-25 Cohn Michael B. MEMS device with integral packaging

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610431A (en) 1995-05-12 1997-03-11 The Charles Stark Draper Laboratory, Inc. Covers for micromechanical sensors and other semiconductor devices
US6025767A (en) 1996-08-05 2000-02-15 Mcnc Encapsulated micro-relay modules and methods of fabricating same
EP0951068A1 (en) * 1998-04-17 1999-10-20 Interuniversitair Micro-Elektronica Centrum Vzw Method of fabrication of a microstructure having an inside cavity
US6252229B1 (en) * 1998-07-10 2001-06-26 Boeing North American, Inc. Sealed-cavity microstructure and microbolometer and associated fabrication methods
US6219254B1 (en) 1999-04-05 2001-04-17 Trw Inc. Chip-to-board connection assembly and method therefor
US6521477B1 (en) 2000-02-02 2003-02-18 Raytheon Company Vacuum package fabrication of integrated circuit components
KR100370398B1 (en) * 2000-06-22 2003-01-30 삼성전자 주식회사 Method for surface mountable chip scale packaging of electronic and MEMS devices
US6550664B2 (en) * 2000-12-09 2003-04-22 Agilent Technologies, Inc. Mounting film bulk acoustic resonators in microwave packages using flip chip bonding technology
US6624003B1 (en) * 2002-02-06 2003-09-23 Teravicta Technologies, Inc. Integrated MEMS device and package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096421A1 (en) * 2000-11-29 2002-07-25 Cohn Michael B. MEMS device with integral packaging

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100068854A1 (en) * 2005-10-03 2010-03-18 Analog Devices, Inc. MEMS Switch Capping and Passivation Method
US7968364B2 (en) * 2005-10-03 2011-06-28 Analog Devices, Inc. MEMS switch capping and passivation method
US20110287586A1 (en) * 2005-10-03 2011-11-24 Analog Devices, Inc. MEMS Switch Capping and Passivation Method
US8124436B2 (en) * 2005-10-03 2012-02-28 Analog Devices, Inc. MEMS switch capping and passivation method
US20070235501A1 (en) * 2006-03-29 2007-10-11 John Heck Self-packaging MEMS device
US20070290308A1 (en) * 2006-06-14 2007-12-20 Magnachip Semiconductor Ltd. Package of MEMS device and method for fabricating the same
US7615394B2 (en) * 2006-06-14 2009-11-10 Magnachip Semiconductor Ltd. Method for fabricating MEMS device package that includes grinding MEMS device wafer to expose array pads corresponding to a cap wafer
US20100006959A1 (en) * 2006-06-14 2010-01-14 Magnachip Semiconductor Ltd. Package of mems device and method for fabricating the same
US7948043B2 (en) 2006-06-14 2011-05-24 Magnachip Semiconductor Ltd. MEMS package that includes MEMS device wafer bonded to cap wafer and exposed array pads
US20100147294A1 (en) * 2007-05-15 2010-06-17 Portaero, Inc. Devices and methods to maintain the patency of an opening relative to parenchymal tissue of the lung
US20090079037A1 (en) * 2007-09-20 2009-03-26 Heribert Weber Micromechanical component and method for producing a micromechanical component
US7705413B2 (en) * 2007-09-20 2010-04-27 Robert Bosch Gmbh Micromechanical component and method for producing a micromechanical component

Also Published As

Publication number Publication date
MY138751A (en) 2009-07-31
WO2003083883A2 (en) 2003-10-09
AU2003212969A8 (en) 2003-10-13
TW588421B (en) 2004-05-21
TW200304682A (en) 2003-10-01
WO2003083883A3 (en) 2003-12-11
AU2003212969A1 (en) 2003-10-13
US20030183407A1 (en) 2003-10-02
US6852926B2 (en) 2005-02-08

Similar Documents

Publication Publication Date Title
US6852926B2 (en) Packaging microelectromechanical structures
US6903452B2 (en) Packaging microelectromechanical structures
US7368808B2 (en) MEMS packaging using a non-silicon substrate for encapsulation and interconnection
EP2121511B1 (en) Method of packaging an electronic or micromechanical component
EP0609062B1 (en) Mass simultaneous sealing and electrical connection of electronic devices
US7868448B2 (en) Electrical component and production thereof
US6630725B1 (en) Electronic component and method of manufacture
US20040032012A1 (en) Hermetically packaging a microelectromechanical switch and a film bulk acoustic resonator
US20080128901A1 (en) Micro-electro-mechanical systems device and integrated circuit device integrated in a three-dimensional semiconductor structure
JP2014131830A (en) Method for manufacturing microelectromechanical component, and microelectromechanical component
US20090261416A1 (en) Integrated mems device and control circuit
US20140329362A1 (en) QFN/SON-Compatible Package
US8138062B2 (en) Electrical coupling of wafer structures
JP2009004461A (en) Electronic component package and manufacturing method thereof
WO2006061792A2 (en) Hermetically sealed integrated circuit package
US7911043B2 (en) Wafer level device package with sealing line having electroconductive pattern and method of packaging the same
JP4268480B2 (en) Electronic component sealing substrate and electronic device using the same
JP2005262382A (en) Electronic device and its manufacturing method
JPH07283334A (en) Airtightly sealed electronic parts
JP2020120195A (en) MEMS oscillator
JP2004296724A (en) Substrate for packaging electronic part and method for manufacturing electronic device using the same
WO2012050461A1 (en) Small form factor oscillator
CN113659954A (en) Bulk acoustic wave resonator, packaging method thereof and electronic equipment
JPH118334A (en) Intermediate of ball grid array package and its manufacture
JP4371217B2 (en) Hermetic sealing structure for semiconductor devices

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION