JP6702019B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP6702019B2
JP6702019B2 JP2016123869A JP2016123869A JP6702019B2 JP 6702019 B2 JP6702019 B2 JP 6702019B2 JP 2016123869 A JP2016123869 A JP 2016123869A JP 2016123869 A JP2016123869 A JP 2016123869A JP 6702019 B2 JP6702019 B2 JP 6702019B2
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semiconductor element
stress
circuit board
expansion member
expansion
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JP2017228659A5 (en
JP2017228659A (en
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谷　直樹
直樹 谷
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JTEKT Corp
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JTEKT Corp
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Priority to JP2016123869A priority Critical patent/JP6702019B2/en
Priority to US15/623,943 priority patent/US10211135B2/en
Priority to EP17177033.2A priority patent/EP3261416A1/en
Priority to CN201710474001.3A priority patent/CN107527872A/en
Publication of JP2017228659A publication Critical patent/JP2017228659A/en
Publication of JP2017228659A5 publication Critical patent/JP2017228659A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09136—Means for correcting warpage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2018—Presence of a frame in a printed circuit or printed circuit assembly

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

本発明は、回路基板上に実装された半導体素子を有する半導体装置に関する。   The present invention relates to a semiconductor device having a semiconductor element mounted on a circuit board.

半導体素子の高機能化に伴って、半導体素子に設けられる接続端子の数が増加する傾向にある。一方で、半導体素子の小型化も求められている。このため、複数の接続端子を狭い領域に効率よく設けるために、フリップチップ構造が半導体素子に採用されている。フリップチップ構造は、例えば、半導体素子の底面に複数の接続端子がアレイ状に配列された構造を有する。   The number of connection terminals provided in a semiconductor element tends to increase as the functionality of the semiconductor element increases. On the other hand, miniaturization of semiconductor elements is also required. Therefore, in order to efficiently provide a plurality of connection terminals in a narrow area, a flip chip structure is adopted for the semiconductor element. The flip chip structure has, for example, a structure in which a plurality of connection terminals are arranged in an array on the bottom surface of a semiconductor element.

しかし、フリップチップ構造を有する半導体素子を回路基板上に実装した場合、回路基板と半導体素子とを接続するはんだにおいて、クラックが発生することがある。   However, when a semiconductor element having a flip chip structure is mounted on a circuit board, cracks may occur in the solder that connects the circuit board and the semiconductor element.

半導体素子や、半導体素子の周辺に設置された熱源で発生する熱によって、回路基板及び半導体素子が膨張する。回路基板の線膨張係数が、半導体素子の線膨張係数よりも大きいため、回路基板は、半導体素子よりも大きく膨張する。このようにして生じる回路基板と半導体素子との膨張差によって、半導体素子において反りが発生する。半導体素子の反りは、半導体素子の接続端子と回路基板に形成された配線とを電気的に接続するはんだにおいて発生するクラックの原因となる。クラックは、半導体素子が設けられた半導体装置の故障の原因となるため、クラックの発生を防ぐ対策を取らなければならない。   The circuit board and the semiconductor element are expanded by the heat generated by the semiconductor element and the heat source installed around the semiconductor element. Since the linear expansion coefficient of the circuit board is larger than the linear expansion coefficient of the semiconductor element, the circuit board expands more than the semiconductor element. Due to the difference in expansion between the circuit board and the semiconductor element thus generated, the semiconductor element is warped. The warp of the semiconductor element causes cracks that occur in the solder that electrically connects the connection terminal of the semiconductor element and the wiring formed on the circuit board. A crack causes a failure of a semiconductor device provided with a semiconductor element, and therefore measures must be taken to prevent the occurrence of the crack.

特許文献１には、フリップチップ構造を有するＬＳＩ（Large-Scale Integration）と、ＬＳＩが実装される回路基板との接続構造が開示されている。特許文献１では、ＬＳＩの接続端子は、ＬＳＩの底面の中心領域（電気的接続端子領域）においてアレイ状に配置される。電気的接続端子領域の周囲に、ＬＳＩと回路基板との機械的な接合を補強する領域（機械的接続補強端子領域）が形成される。回路基板とＬＳＩの機械的接続補強端子領域との間を、はんだボールを用いてリフローすることにより、回路基板とＬＳＩの機械的接続補強端子領域とを機械的に接続するはんだがアレイ状に配置される。これにより、ＬＳＩと回路基板との接合が補強されるため、ＬＳＩの反りが抑制される。半導体素子と回路基板に設けられた配線との電気的接続の信頼性を向上させることができる。   Patent Document 1 discloses a connection structure between an LSI (Large-Scale Integration) having a flip chip structure and a circuit board on which the LSI is mounted. In Patent Document 1, the connection terminals of the LSI are arranged in an array in the central region (electrical connection terminal region) of the bottom surface of the LSI. A region (mechanical connection reinforcing terminal region) that reinforces mechanical joining between the LSI and the circuit board is formed around the electrical connection terminal region. By reflowing between the circuit board and the mechanical connection reinforcing terminal area of the LSI using a solder ball, solder that mechanically connects the circuit board and the mechanical connection reinforcing terminal area of the LSI is arranged in an array. To be done. As a result, the joint between the LSI and the circuit board is reinforced, so that warpage of the LSI is suppressed. The reliability of electrical connection between the semiconductor element and the wiring provided on the circuit board can be improved.

特開２０００−２２０３４号公報JP, 2000-22034, A

本発明の目的は、半導体素子の接続端子と回路基板に設けられた配線とを電気的に接続するはんだでクラックが発生することを防ぐことができる半導体装置を提供することである。   It is an object of the present invention to provide a semiconductor device capable of preventing cracks from being generated by solder that electrically connects a connection terminal of a semiconductor element and a wiring provided on a circuit board.

本発明の一実施の形態に係る半導体装置は、第１の面と、第１の面に対向する第２の面とを有する回路基板と、第１の面及び第２の面の少なくとも一方に形成される少なくとも２つの金属配線と、第１の面に対向するように配置された端子形成面において、少なくとも２つの接続端子が形成されている半導体素子と、少なくとも２つの接続端子の各々と少なくとも２つの金属配線の各々とを電気的に接続するはんだと、半導体素子の端子形成面に固定され、半導体素子の線膨張係数よりも大きい線膨張係数を有し、少なくとも２つの接続端子のうち互いに隣り合う２つの接続端子の間隔よりも大きいサイズを有する膨張部材と、を備える。膨張部材は、金属配線の線膨張係数よりも大きい線膨張係数を有し、膨張部材において第１の面に対向する面は、第１の面に接触する接触面と、第１の面に接触しない非接触面とを有する。 A semiconductor device according to one embodiment of the present invention includes a circuit board having a first surface and a second surface facing the first surface, and at least one of the first surface and the second surface. At least two metal wirings to be formed, a semiconductor element in which at least two connection terminals are formed on the terminal formation surface arranged so as to face the first surface, and at least two connection terminals, respectively. Solder that electrically connects each of the two metal wirings and a solder that is fixed to the terminal formation surface of the semiconductor element and has a linear expansion coefficient larger than the linear expansion coefficient of the semiconductor element. And an expansion member having a size larger than a space between two adjacent connection terminals. The expansion member has a linear expansion coefficient larger than that of the metal wiring, and a surface of the expansion member facing the first surface is in contact with the first surface and in contact with the first surface. It has a non-contact surface.

好ましくは、上記の半導体装置において、膨張部材が、１０〜３３×１０−６（１／Ｋ）の範囲内の線膨張係数を有する。 Preferably, in the above semiconductor device, the expansion member has a linear expansion coefficient within the range of 10 to 33×10 −6 (1/K).

好ましくは、上記の半導体装置は、さらに、第１の面と非接触面との間に挿入され、膨張部材の線膨張係数よりも小さい線膨張係数を有する挿入部材、を備える。   Preferably, the above semiconductor device further includes an insertion member inserted between the first surface and the non-contact surface and having a linear expansion coefficient smaller than that of the expansion member.

好ましくは、上記の半導体装置において、膨張部材は、端子形成面と対向する面に固定され、挿入部材が第１の面と非接触面との間に配置される。   Preferably, in the above semiconductor device, the expansion member is fixed to a surface facing the terminal formation surface, and the insertion member is arranged between the first surface and the non-contact surface.

本発明に係る半導体装置において、膨張部材は、半導体素子の線膨張係数よりも大きい線膨張係数を有し、半導体素子の端子形成面に固定される。膨張部材のサイズは、互いに隣り合う２つの接続端子の間隔よりも大きい。膨張部材の膨張により発生する応力が、半導体素子のうち、互いに隣り合う２つの接続端子の間の部分に伝わるため、本発明に係る半導体装置は、接続端子とはんだとの接続面に生じる剪断応力を小さくすることができる。従って、本発明に係る半導体装置は、接続端子とはんだとの接続面でクラックが発生することを防ぐことができる。   In the semiconductor device according to the present invention, the expansion member has a linear expansion coefficient larger than that of the semiconductor element and is fixed to the terminal formation surface of the semiconductor element. The size of the expansion member is larger than the distance between two adjacent connection terminals. Since the stress generated by the expansion of the expansion member is transmitted to the portion of the semiconductor element between the two adjacent connection terminals, the semiconductor device according to the present invention has a shear stress generated on the connection surface between the connection terminal and the solder. Can be made smaller. Therefore, the semiconductor device according to the present invention can prevent the occurrence of cracks on the connection surface between the connection terminal and the solder.

本発明の第１の実施の形態に係る半導体装置の構成を示す側面断面図である。It is a side sectional view showing the composition of the semiconductor device concerning a 1st embodiment of the present invention. 図１に示す回路基板の底面図である。It is a bottom view of the circuit board shown in FIG. 図１に示す半導体素子の底面図である。It is a bottom view of the semiconductor device shown in FIG. 図１に示す半導体装置で発生する応力を説明する図である。FIG. 3 is a diagram illustrating stress generated in the semiconductor device shown in FIG. 1. 図１に示す半導体装置で発生する応力を説明する図である。FIG. 3 is a diagram illustrating stress generated in the semiconductor device shown in FIG. 1. 図１に示す膨張部材で発生する応力を模式的に示す図である。It is a figure which shows typically the stress which arises in the expansion member shown in FIG. 図１に示す膨張部材の変形例を示す図である。It is a figure which shows the modification of the expansion member shown in FIG. 図１に示す半導体装置の変形例の側面断面図である。It is a side surface sectional view of the modification of the semiconductor device shown in FIG. 本発明の第２の実施の形態に係る半導体装置の構成を示す側面断面図である。It is a side sectional view showing the composition of the semiconductor device concerning a 2nd embodiment of the present invention. 図９に示す回路基板の平面図である。It is a top view of the circuit board shown in FIG. 図９に示す半導体装置で発生する応力を説明する図である。It is a figure explaining the stress which arises in the semiconductor device shown in FIG. 図９に示す半導体装置の変形例の側面断面図である。It is a side sectional view of a modification of the semiconductor device shown in FIG.

以下、図面を参照し、本発明の実施の形態を詳しく説明する。図中同一又は相当部分には同一符号を付してその説明は繰り返さない。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts will be denoted by the same reference symbols and description thereof will not be repeated.

［第１の実施の形態］
図１は、本発明の第１の実施の形態に係る半導体装置１００の構成を示す側面断面図である。図２は、図１に示す回路基板２の底面図である。図３は、図１に示す半導体素子１の底面図である。 [First Embodiment]
FIG. 1 is a side sectional view showing the configuration of a semiconductor device 100 according to the first embodiment of the present invention. FIG. 2 is a bottom view of the circuit board 2 shown in FIG. FIG. 3 is a bottom view of the semiconductor device 1 shown in FIG.

以下の説明において、図１における横方向をｘ軸、図１における縦方向をｙ軸、図１における紙面奥行き方向をｚ軸と定義する。なお、説明の便宜上、ｙ軸方向を上下方向と呼び、半導体素子１から見て回路基板２の位置する方向を下方向と呼ぶ場合がある。   In the following description, the horizontal direction in FIG. 1 is defined as the x-axis, the vertical direction in FIG. 1 is defined as the y-axis, and the paper depth direction in FIG. 1 is defined as the z-axis. For convenience of description, the y-axis direction may be referred to as a vertical direction, and the direction in which the circuit board 2 is located when viewed from the semiconductor element 1 may be referred to as a downward direction.

図１及び図２に示すように、半導体装置１００は、半導体素子１と、回路基板２と、金属配線３Ａ〜３Ｆと、はんだ４，４，・・・と、膨張部材５とを備える。以下、金属配線３Ａ〜３Ｆを総称する場合、「金属配線３」と記載する。   As shown in FIGS. 1 and 2, the semiconductor device 100 includes a semiconductor element 1, a circuit board 2, metal wirings 3A to 3F, solders 4, 4,..., And an expansion member 5. Hereinafter, the metal wirings 3A to 3F are collectively referred to as "metal wiring 3".

半導体装置１００は、例えば、自動車の電動パワーステアリング用のモータの制御回路であり、このモータを駆動させるための交流電流を生成するために用いられる。半導体素子１は、図示しないスイッチング素子の制御信号を生成して、スイッチング素子に供給する。   The semiconductor device 100 is, for example, a control circuit of a motor for electric power steering of an automobile, and is used to generate an alternating current for driving the motor. The semiconductor element 1 generates a control signal for a switching element (not shown) and supplies it to the switching element.

半導体素子１は、例えば、トランジスタ、ダイオードなどにより構成される回路部を含む半導体チップであり、回路基板２の上に位置する。図１及び図３に示すように、半導体素子１は、筐体１１と、接続端子１２Ａ〜１２Ｆとを備える。図１に示す半導体素子１において、トランジスタやダイオード等により形成される回路部の表示を省略している。   The semiconductor element 1 is, for example, a semiconductor chip including a circuit portion configured by transistors, diodes, and the like, and is located on the circuit board 2. As shown in FIGS. 1 and 3, the semiconductor element 1 includes a housing 11 and connection terminals 12A to 12F. In the semiconductor device 1 shown in FIG. 1, the display of the circuit portion formed by transistors, diodes, etc. is omitted.

半導体素子１は、半導体素子１自身で発生する熱や、上記のスイッチング素子などの他の熱源で発生する熱により膨張する。半導体素子１の線膨張係数は、筐体１１に用いられる素材や、回路部を構成する基板に用いられる素材等に基づいて決まる。半導体素子１の線膨張係数は、具体的には、２〜６×１０−６（１／Ｋ）である。 The semiconductor element 1 expands due to the heat generated by the semiconductor element 1 itself or the heat generated by another heat source such as the switching element. The coefficient of linear expansion of the semiconductor element 1 is determined based on the material used for the housing 11 and the material used for the substrate forming the circuit section. The linear expansion coefficient of the semiconductor element 1 is specifically 2 to 6×10 −6 (1/K).

接続端子１２Ａ〜１２Ｆは、半導体素子１における入出力端子であり、回路部に接続される。以下、接続端子１２Ａ〜１２Ｆを総称する場合、「接続端子１２」と記載する。接続端子１２は、半導体素子１において回路基板２の上面２１に対向する端子形成面１３にアレイ状に配置される。接続端子１２は、端子形成面１３において、ｘ軸方向に沿って２つ配置され、ｚ軸方向に沿って３つ配置される。端子形成面１３は、筐体１１の底面に相当する。半導体素子１は、半導体素子１において対向する２つの面のうち一方の面に接続端子１２が配置された横型半導体素子であり、フリップチップ構造を有する。   The connection terminals 12A to 12F are input/output terminals in the semiconductor element 1 and are connected to the circuit section. Hereinafter, the connection terminals 12A to 12F will be collectively referred to as "connection terminal 12". The connection terminals 12 are arranged in an array on the terminal formation surface 13 facing the upper surface 21 of the circuit board 2 in the semiconductor element 1. On the terminal formation surface 13, two connection terminals 12 are arranged along the x-axis direction and three connection terminals 12 are arranged along the z-axis direction. The terminal forming surface 13 corresponds to the bottom surface of the housing 11. The semiconductor element 1 is a lateral semiconductor element in which the connection terminal 12 is arranged on one surface of the two surfaces facing each other in the semiconductor element 1, and has a flip chip structure.

図１及び図２に示すように、回路基板２は、平板状の部材である。回路基板２は、半導体素子１の線膨張係数よりも大きい線膨張係数を有する素材により形成される。回路基板２の線膨張係数は、具体的には、１０〜２０×１０−６（１／Ｋ）である。 As shown in FIGS. 1 and 2, the circuit board 2 is a flat plate-shaped member. The circuit board 2 is formed of a material having a linear expansion coefficient larger than that of the semiconductor element 1. The linear expansion coefficient of the circuit board 2 is specifically 10 to 20×10 −6 (1/K).

スルーホール２３Ａ〜２３Ｆが、回路基板２を上下方向に貫通している。スルーホール２３Ａ〜２３Ｆは、ｘ軸方向に沿って２つ形成され、ｚ軸方向に沿って３つ形成される。半導体装置１００を上から下方向に見た場合において、スルーホール２３Ａ〜２３Ｆの各々は、半導体素子１の接続端子１２Ａ〜１２Ｆの各々に重なる位置に形成される。   The through holes 23A to 23F penetrate the circuit board 2 in the vertical direction. Two through holes 23A to 23F are formed along the x-axis direction, and three through holes are formed along the z-axis direction. When the semiconductor device 100 is viewed from above, the through holes 23A to 23F are formed at positions overlapping the connection terminals 12A to 12F of the semiconductor element 1, respectively.

金属配線３Ａ〜３Ｆの各々は、回路基板２の下面２２と、回路基板２を上下方向に貫通するスルーホール２３Ａ〜２３Ｆの内周面とに形成される。具体的には、金属配線３Ａは、スルーホール２３Ａの内周面に金属めっきを施すことにより形成される層間接続部３１Ａと、回路基板２の下面２２に形成されるパターン部３２Ａとを備える。   Each of the metal wirings 3A to 3F is formed on the lower surface 22 of the circuit board 2 and the inner peripheral surfaces of the through holes 23A to 23F penetrating the circuit board 2 in the vertical direction. Specifically, the metal wiring 3A includes an interlayer connection portion 31A formed by applying metal plating to the inner peripheral surface of the through hole 23A, and a pattern portion 32A formed on the lower surface 22 of the circuit board 2.

金属配線３Ｂ〜３Ｆは、金属配線３Ａと同様の構成を備える。すなわち、金属配線３Ｂは、層間接続部３１Ｂと、パターン部３２Ｂとを備える。金属配線３Ｃは、層間接続部３１Ｃと、パターン部３２Ｃとを備える。金属配線３Ｄは、層間接続部３１Ｄと、パターン部３２Ｄとを備える。金属配線３Ｅは、層間接続部３１Ｅと、パターン部３２Ｅとを備える。金属配線３Ｆは、層間接続部３１Ｆと、パターン部３２Ｆとを備える。   The metal wirings 3B to 3F have the same configuration as the metal wiring 3A. That is, the metal wiring 3B includes the interlayer connection portion 31B and the pattern portion 32B. The metal wiring 3C includes an interlayer connecting portion 31C and a pattern portion 32C. The metal wiring 3D includes an interlayer connection portion 31D and a pattern portion 32D. The metal wiring 3E includes an interlayer connecting portion 31E and a pattern portion 32E. The metal wiring 3F includes an interlayer connection portion 31F and a pattern portion 32F.

金属配線３に用いられる素材は、例えば、銅や、銅を主成分とする合金である。具体的には、線膨張係数が１４〜２３×１０−６（１／Ｋ）である金属が、金属配線３として用いられる。つまり、回路基板２の線膨張係数は、金属配線３の線膨張係数と同程度となるように設定される。 The material used for the metal wiring 3 is, for example, copper or an alloy containing copper as a main component. Specifically, a metal having a linear expansion coefficient of 14 to 23×10 −6 (1/K) is used as the metal wiring 3. That is, the linear expansion coefficient of the circuit board 2 is set to be approximately the same as the linear expansion coefficient of the metal wiring 3.

はんだ４，４，・・・は、半導体素子１の接続端子１２Ａ〜１２Ｆと、金属配線３Ａ〜３Ｆとを電気的に接続する。はんだ４の線膨張係数は、半導体素子１の線膨張係数よりも大きい。はんだ４の線膨張係数は、具体的には、１４〜３０×１０−６（１／Ｋ）である。接続端子１２Ａは、金属配線３Ａの層間接続部３１Ａとはんだ４によりはんだ付けされることにより、金属配線３Ａと電気的に接続される。同様に、接続端子１２Ｂは、金属配線３Ｂと電気的に接続される。接続端子１２Ｃは、金属配線３Ｃと電気的に接続される。接続端子１２Ｄは、金属配線３Ｄと電気的に接続される。接続端子１２Ｅは、金属配線３Ｅと電気的に接続される。接続端子１２Ｆは、金属配線３Ｆと電気的に接続される。 The solder 4, 4,... Connects the connection terminals 12A to 12F of the semiconductor element 1 and the metal wirings 3A to 3F electrically. The linear expansion coefficient of the solder 4 is larger than that of the semiconductor element 1. The coefficient of linear expansion of the solder 4 is specifically 14 to 30×10 −6 (1/K). The connection terminal 12A is electrically connected to the metal wiring 3A by being soldered to the interlayer connection portion 31A of the metal wiring 3A with the solder 4. Similarly, the connection terminal 12B is electrically connected to the metal wiring 3B. The connection terminal 12C is electrically connected to the metal wiring 3C. The connection terminal 12D is electrically connected to the metal wiring 3D. The connection terminal 12E is electrically connected to the metal wiring 3E. The connection terminal 12F is electrically connected to the metal wiring 3F.

膨張部材５は、図１及び図３に示すように、環状形状であり、半導体素子１の端子形成面１３の外周に沿って配置される。つまり、膨張部材５は、接続端子１２を囲むようにして配置される。膨張部材５の上面は、半導体素子１の端子形成面１３に固定される。膨張部材５の下面は、回路基板２の上面２１に接触しているが、回路基板２の上面２１に固定されない。   As shown in FIGS. 1 and 3, the expansion member 5 has an annular shape and is arranged along the outer periphery of the terminal formation surface 13 of the semiconductor element 1. That is, the expansion member 5 is arranged so as to surround the connection terminal 12. The upper surface of the expansion member 5 is fixed to the terminal formation surface 13 of the semiconductor element 1. The lower surface of the expansion member 5 is in contact with the upper surface 21 of the circuit board 2, but is not fixed to the upper surface 21 of the circuit board 2.

膨張部材５は、半導体素子１の線膨張係数よりも大きい線膨張係数を有する素材により形成される。膨張部材５として、例えば、はんだや、半導体に接合された銅板などが用いられる。膨張部材５の線膨張係数は、好ましくは、１０〜３３×１０−６（１／Ｋ）であり、さらに好ましくは、１４〜３０×１０−６（１／Ｋ）である。 The expansion member 5 is formed of a material having a linear expansion coefficient larger than that of the semiconductor element 1. As the expansion member 5, for example, solder or a copper plate bonded to a semiconductor is used. The linear expansion coefficient of the expansion member 5 is preferably 10 to 33×10 −6 (1/K), and more preferably 14 to 30×10 −6 (1/K).

このように、膨張部材５は、半導体素子１の端子形成面１３に固定され、端子形成面１３の外周に沿って環状に配置される。膨張部材５を設けることにより、半導体素子１及び半導体素子１の近傍に配置された熱源で発生する熱により、半導体装置１００においてクラックが発生することを防ぐことができる。以下、詳しく説明する。   In this way, the expansion member 5 is fixed to the terminal forming surface 13 of the semiconductor element 1 and arranged in an annular shape along the outer periphery of the terminal forming surface 13. By providing the expansion member 5, it is possible to prevent cracks from occurring in the semiconductor device 100 due to heat generated by the semiconductor element 1 and the heat source arranged near the semiconductor element 1. The details will be described below.

ここで、クラックは、接続端子１２とはんだ４との接続面において割れが発生することを示す。熱源は、例えば、半導体素子１により生成された制御信号に応じて動作するスイッチング素子や、半導体装置１００の近傍に配置されたモータなどが挙げられる。   Here, the crack means that a crack occurs at the connection surface between the connection terminal 12 and the solder 4. Examples of the heat source include a switching element that operates according to a control signal generated by the semiconductor element 1 and a motor that is arranged near the semiconductor device 100.

最初に、クラックが発生する原因について、図４を参照しながら説明する。図４は、半導体装置１００で発生する応力を説明する図である。図４において、膨張部材５の表示を省略している。また、図４において、スルーホール、層間接続部、及びパターン部の符号の表示を省略している。   First, the cause of cracks will be described with reference to FIG. FIG. 4 is a diagram for explaining the stress generated in the semiconductor device 100. In FIG. 4, the display of the expansion member 5 is omitted. Further, in FIG. 4, the reference numerals of the through holes, the interlayer connecting portions, and the pattern portions are omitted.

半導体素子１と、回路基板２と、金属配線３と、はんだ４とは、半導体素子１及び熱源で発生する熱により膨張する。つまり、半導体素子１と、回路基板２と、金属配線３と、はんだ４との各々において、ｘ軸方向、ｙ軸方向、ｚ軸方向の各々の方向に向かう応力が発生する。これら３軸方向に向かう応力のうち、ｘ軸方向及びｚ軸方向の応力（ｘｚ平面に平行な方向の応力）が、クラックの原因となる。   The semiconductor element 1, the circuit board 2, the metal wiring 3, and the solder 4 expand due to the heat generated by the semiconductor element 1 and the heat source. That is, stress is generated in each of the semiconductor element 1, the circuit board 2, the metal wiring 3, and the solder 4 in the x-axis direction, the y-axis direction, and the z-axis direction. Among the stresses in the three axial directions, the stresses in the x-axis direction and the z-axis direction (the stress in the direction parallel to the xz plane) cause the cracks.

回路基板２及び金属配線３は、上述のように、同程度の線膨張係数を有している。従って、回路基板２のｘｚ平面に平行な方向の伸びは、金属配線３のｘｚ平面に平行な方向の伸びと同程度となり、回路基板２及び金属配線３の各々で、応力６０が発生する。回路基板２及び金属配線３において、膨張に大きな差が発生しないため、回路基板２に反りが発生することが抑制される。このように、回路基板２及び金属配線３は、熱膨張に関して、一体化された１つの部材とみなすことができる。   The circuit board 2 and the metal wiring 3 have similar linear expansion coefficients as described above. Therefore, the extension of the circuit board 2 in the direction parallel to the xz plane is approximately the same as the extension of the metal wiring 3 in the direction parallel to the xz plane, and the stress 60 is generated in each of the circuit board 2 and the metal wiring 3. Since a large difference in expansion does not occur between the circuit board 2 and the metal wiring 3, it is possible to prevent the circuit board 2 from warping. In this way, the circuit board 2 and the metal wiring 3 can be regarded as one integrated member in terms of thermal expansion.

一方、半導体素子１の線膨張係数は、上述のように、回路基板２及び金属配線３の各々の線膨張係数よりも小さく、回路基板２及び金属配線３の各々の線膨張係数の３分の１程度である。従って、半導体素子１のｘｚ平面に平行な方向への伸びは、回路基板２及び金属配線３のｘｚ平面に平行な方向の伸びより小さい。半導体素子１のｘｚ平面に平行な方向への伸びに応じて発生する応力６１は、回路基板２及び金属配線３のｘｚ平面に平行な方向への伸びに応じて発生する応力６０よりも小さい。   On the other hand, the linear expansion coefficient of the semiconductor element 1 is smaller than the linear expansion coefficient of each of the circuit board 2 and the metal wiring 3, as described above, and is 3/3 of the linear expansion coefficient of each of the circuit board 2 and the metal wiring 3. It is about 1. Therefore, the extension of the semiconductor element 1 in the direction parallel to the xz plane is smaller than the extension of the circuit board 2 and the metal wiring 3 in the direction parallel to the xz plane. The stress 61 generated according to the extension of the semiconductor element 1 in the direction parallel to the xz plane is smaller than the stress 60 generated according to the extension of the circuit board 2 and the metal wiring 3 in the direction parallel to the xz plane.

この結果、半導体素子１で発生する応力６１と、回路基板２及び金属配線３で発生する応力６０との差が、接続端子１２とはんだ４との接続面において剪断応力として作用する。半導体素子１及び熱源において熱が発生している期間において、剪断応力が、接続端子１２とはんだ４との接続面において継続的に作用する。この剪断応力は、半導体素子１の線膨張係数と、回路基板２及び金属配線３の各々の線膨張係数との差によって発生し、接続端子１２とはんだ４との接続面でひずみを発生させる。従って、この剪断応力は、接続端子１２とはんだ４との接続面において発生するクラックの原因となる。   As a result, the difference between the stress 61 generated in the semiconductor element 1 and the stress 60 generated in the circuit board 2 and the metal wiring 3 acts as a shear stress on the connection surface between the connection terminal 12 and the solder 4. During the period in which heat is generated in the semiconductor element 1 and the heat source, shear stress continuously acts on the connection surface between the connection terminal 12 and the solder 4. This shear stress is generated due to the difference between the linear expansion coefficient of the semiconductor element 1 and the linear expansion coefficient of each of the circuit board 2 and the metal wiring 3, and causes strain at the connection surface between the connection terminal 12 and the solder 4. Therefore, this shear stress causes a crack that occurs in the connection surface between the connection terminal 12 and the solder 4.

また、半導体素子１の線膨張係数とはんだ４の線膨張係数との差も、クラックの原因となる。はんだ４の線膨張係数は、上述のように、半導体素子１の線膨張係数よりも大きいため、はんだ４のｘｚ平面に平行な方向の伸びは、半導体素子１のｘｚ平面に平行な方向の伸びよりも大きい。はんだ４で発生するｘｚ平面に平行な方向の応力４１が、半導体素子１で発生するｘｚ平面に平行な応力６１よりも大きいため、応力４１と応力６１との差も、接続端子１２とはんだ４との接続面における剪断応力として作用する。つまり、半導体素子１の線膨張係数とはんだ４との線膨張係数との差によっても、剪断応力が、接続端子１２とはんだ４との接続面で発生し、この剪断応力も、クラックの原因となる。   Further, the difference between the linear expansion coefficient of the semiconductor element 1 and the linear expansion coefficient of the solder 4 also causes a crack. Since the linear expansion coefficient of the solder 4 is larger than that of the semiconductor element 1 as described above, the expansion of the solder 4 in the direction parallel to the xz plane is the expansion of the semiconductor element 1 in the direction parallel to the xz plane. Greater than. Since the stress 41 generated in the solder 4 in the direction parallel to the xz plane is larger than the stress 61 generated in the semiconductor element 1 parallel to the xz plane, the difference between the stress 41 and the stress 61 is also the connection terminal 12 and the solder 4 It acts as a shear stress on the connection surface with. That is, due to the difference between the linear expansion coefficient of the semiconductor element 1 and the linear expansion coefficient of the solder 4, shear stress also occurs at the connection surface between the connection terminal 12 and the solder 4, and this shear stress also causes cracks. Become.

また、熱により生じる半導体素子１の反りも、クラックの原因となる。図４に示すように、回路基板２で発生する応力６０が、接続端子１２Ｂ，１２Ｅの各々に接続されたはんだ４，４を介して、半導体素子１の中心部に伝わる。中心部とは、半導体素子１を上から下方向に見た場合において、半導体素子１において複数の接続端子１２により挟まれた部分である。図３では、一点鎖線により囲まれた領域が中心部に相当する。   The warp of the semiconductor element 1 caused by heat also causes a crack. As shown in FIG. 4, the stress 60 generated in the circuit board 2 is transmitted to the central portion of the semiconductor element 1 via the solders 4 and 4 connected to the connection terminals 12B and 12E, respectively. The central portion is a portion sandwiched by a plurality of connection terminals 12 in the semiconductor element 1 when the semiconductor element 1 is viewed from above. In FIG. 3, the area surrounded by the alternate long and short dash line corresponds to the central portion.

この結果、半導体素子１の中心部では、応力６１と、回路基板２から伝わる応力６０とが合成された合成応力６２が発生する。合成応力６２は、応力６１よりも大きい。一方、半導体素子１の周縁部には、回路基板２及び金属配線３で発生する応力６０は伝わらず、半導体素子１の周縁部は、応力６０の影響を受けない。ここで、周縁部は、半導体素子１において、接続端子１２から外方向の部分である。外方向は、接続端子１２から見て膨張部材５が位置する方向である。この結果、応力の局所的な差が半導体素子１で発生するため、半導体素子１において、下に凸となるような反りが発生する。この反りは、半導体素子１を上方向に引っ張る力として作用するため、クラックの原因となる。   As a result, in the central portion of the semiconductor element 1, a synthetic stress 62, which is a combination of the stress 61 and the stress 60 transmitted from the circuit board 2, is generated. The synthetic stress 62 is larger than the stress 61. On the other hand, the stress 60 generated in the circuit board 2 and the metal wiring 3 is not transmitted to the peripheral portion of the semiconductor element 1, and the peripheral portion of the semiconductor element 1 is not affected by the stress 60. Here, the peripheral portion is a portion of the semiconductor element 1 outward from the connection terminal 12. The outward direction is the direction in which the expansion member 5 is located when viewed from the connection terminal 12. As a result, a local difference in stress is generated in the semiconductor element 1, so that the semiconductor element 1 is warped to be convex downward. This warp acts as a force to pull the semiconductor element 1 upward, and thus causes a crack.

図５及び図６は、膨張部材５で発生する応力を説明する図である。図５は、半導体素子１の側面断面図に相当し、図６は、半導体素子１の底面図に相当する。図５において、スルーホール、層間接続部、及びパターン部の符号の表示を省略している。   5 and 6 are diagrams for explaining the stress generated in the expansion member 5. FIG. 5 corresponds to a side cross-sectional view of the semiconductor element 1, and FIG. 6 corresponds to a bottom view of the semiconductor element 1. In FIG. 5, reference numerals of the through holes, the interlayer connecting portions, and the pattern portions are omitted.

図５に示すように、応力６１が半導体素子１に発生し、応力６０が回路基板２及び金属配線３に発生し、応力４１がはんだ４に発生する。また、半導体素子１の中心部において、合成応力６２が発生する。   As shown in FIG. 5, stress 61 is generated in the semiconductor element 1, stress 60 is generated in the circuit board 2 and the metal wiring 3, and stress 41 is generated in the solder 4. Further, the synthetic stress 62 is generated in the central portion of the semiconductor element 1.

図５及び図６に示すように、膨張部材５が環状の形状をしている。このため、膨張部材５が熱により膨張した場合、膨張部材５において、ｘｙ平面に平行な方向であり、かつ、外方向に広がる応力５５が発生する。膨張部材５は、半導体素子１の線膨張係数よりも大きい線膨張係数を有するため、応力５５は、半導体素子１で発生する応力６１よりも大きい。   As shown in FIGS. 5 and 6, the expansion member 5 has an annular shape. Therefore, when the expansion member 5 is expanded by heat, a stress 55 is generated in the expansion member 5 that is in a direction parallel to the xy plane and that spreads outward. Since the expansion member 5 has a linear expansion coefficient larger than that of the semiconductor element 1, the stress 55 is larger than the stress 61 generated in the semiconductor element 1.

膨張部材５が回路基板２の上面２１に固定されていないため、膨張部材５は、膨張する際に、回路基板２に対して相対的に移動する。従って、応力５５は、膨張部材５から回路基板２に伝わらない。一方、膨張部材５は、半導体素子１の端子形成面１３に固定されているため、半導体素子１の周縁部は、膨張部材５で発生する応力５５を受ける。上述のように、応力５５は、膨張部材５の外方向に向かう力であるため、半導体素子１に伝わる応力５５は、半導体素子１全体を、ｘｚ平面に平行な方向であり、かつ、半導体素子１の中心から外方向に伸ばす力として作用する。   Since the expansion member 5 is not fixed to the upper surface 21 of the circuit board 2, the expansion member 5 moves relative to the circuit board 2 when expanding. Therefore, the stress 55 is not transmitted from the expansion member 5 to the circuit board 2. On the other hand, since the expansion member 5 is fixed to the terminal forming surface 13 of the semiconductor element 1, the peripheral edge of the semiconductor element 1 receives the stress 55 generated in the expansion member 5. As described above, since the stress 55 is a force directed to the outside of the expansion member 5, the stress 55 transmitted to the semiconductor element 1 is in the direction parallel to the xz plane in the entire semiconductor element 1 and It acts as a force that extends outward from the center of 1.

半導体素子１において、応力６１と、膨張部材５から伝わる応力５５とが合成されるため、合成応力６３が発生する。合成応力６３は、半導体素子１から、接続端子１２とはんだ４との接続面に伝わる。合成応力６３が応力６１よりも大きいため、応力６０と合成応力６３との差は、応力６０と応力６１との差よりも小さい。従って、半導体装置１００は、半導体素子１の線膨張係数と、回路基板２及び金属配線３の各々の線膨張係数との差によって生じる剪断応力を小さくすることができる。また、応力５５が半導体素子１に伝わることにより、半導体素子１の線膨張係数とはんだ４の線膨張係数との差によって生じる剪断応力を小さくすることができる。従って、半導体装置１００は、接続端子１２とはんだ４との接続面で発生するクラックを抑制することができる。   In the semiconductor element 1, the stress 61 and the stress 55 transmitted from the expansion member 5 are combined, so that a combined stress 63 is generated. The synthetic stress 63 is transmitted from the semiconductor element 1 to the connection surface between the connection terminal 12 and the solder 4. Since the combined stress 63 is larger than the stress 61, the difference between the stress 60 and the combined stress 63 is smaller than the difference between the stress 60 and the stress 61. Therefore, the semiconductor device 100 can reduce the shear stress caused by the difference between the linear expansion coefficient of the semiconductor element 1 and the linear expansion coefficient of each of the circuit board 2 and the metal wiring 3. Further, by transmitting the stress 55 to the semiconductor element 1, it is possible to reduce the shear stress caused by the difference between the linear expansion coefficient of the semiconductor element 1 and the linear expansion coefficient of the solder 4. Therefore, the semiconductor device 100 can suppress cracks generated at the connection surface between the connection terminal 12 and the solder 4.

膨張部材５で発生する応力５５は、上述のように、半導体素子１の周縁部に伝わる。応力５５は、半導体素子１の周縁部を外方向へ伸ばす力として作用する。膨張部材５は、半導体素子１における応力の局所的な差を小さくすることができる。半導体装置１００は、半導体素子１の反りを抑制することができるため、接続端子１２とはんだ４との接続面で発生するクラックを抑制することができる。   The stress 55 generated in the expansion member 5 is transmitted to the peripheral portion of the semiconductor element 1 as described above. The stress 55 acts as a force that extends the peripheral portion of the semiconductor element 1 outward. The expansion member 5 can reduce the local difference in stress in the semiconductor element 1. Since the semiconductor device 100 can suppress the warpage of the semiconductor element 1, it is possible to suppress cracks generated on the connection surface between the connection terminal 12 and the solder 4.

また、膨張部材５の下面は、上述のように、回路基板２の上面２１に接触している。これにより、半導体装置１００は、接続端子１２とはんだ４との接続面におけるクラックの発生をさらに抑制することができる。以下、詳しく説明する。   The lower surface of the expansion member 5 is in contact with the upper surface 21 of the circuit board 2 as described above. Accordingly, the semiconductor device 100 can further suppress the occurrence of cracks on the connection surface between the connection terminal 12 and the solder 4. The details will be described below.

半導体装置１００において、図示しない熱源で発生する熱は、回路基板２及び金属配線３に伝わる。回路基板２及び金属配線３に伝わった熱は、はんだ４又は膨張部材５を介して半導体素子１に伝わる。半導体素子１の膨張が、回路基板２、金属配線３及びはんだ４よりも遅れて始まるため、応力６０及び応力４１は、応力６１よりも時間的に先に発生する。従って、接続端子１２とはんだ４との接続面における剪断応力は、回路基板２、金属配線３及びはんだ４が膨張を開始してから半導体素子１が膨張を開始するまでの期間において一時的に増加する。   In the semiconductor device 100, heat generated by a heat source (not shown) is transferred to the circuit board 2 and the metal wiring 3. The heat transferred to the circuit board 2 and the metal wiring 3 is transferred to the semiconductor element 1 via the solder 4 or the expansion member 5. Since the expansion of the semiconductor element 1 starts later than that of the circuit board 2, the metal wiring 3 and the solder 4, the stress 60 and the stress 41 occur in time earlier than the stress 61. Therefore, the shear stress on the connection surface between the connection terminal 12 and the solder 4 temporarily increases during the period from the expansion of the circuit board 2, the metal wiring 3 and the solder 4 to the expansion of the semiconductor element 1. To do.

膨張部材５は、回路基板２の上面２１に接触しているため、回路基板２を伝わる熱は、回路基板２から膨張部材５に直接伝わる。膨張部材５は、半導体素子１で応力６１が発生するよりも時間的に早く応力５５を発生させることができる。膨張部材５は、半導体素子１が膨張を開始する前に、応力５５を半導体素子１に伝えることができるため、回路基板２が膨張を開始してから半導体素子１が膨張を開始するまでにおける剪断応力の一時的な増加を抑制することができる。   Since the expansion member 5 is in contact with the upper surface 21 of the circuit board 2, the heat transmitted through the circuit board 2 is directly transferred from the circuit board 2 to the expansion member 5. The expansion member 5 can generate the stress 55 temporally earlier than the stress 61 generated in the semiconductor element 1. Since the expansion member 5 can transmit the stress 55 to the semiconductor element 1 before the semiconductor element 1 starts expansion, the expansion member 5 is sheared after the circuit board 2 starts expansion until the semiconductor element 1 starts expansion. A temporary increase in stress can be suppressed.

また、膨張部材５がはんだ等の金属により形成されているため、膨張部材５は、半導体素子１の端子形成面１３と回路基板２の上面２１との間の空間を電磁気的に遮蔽する。従って、半導体素子１に入力される信号や、半導体素子１から出力される信号にノイズが混入することを防ぐことができる。   Further, since the expansion member 5 is formed of a metal such as solder, the expansion member 5 electromagnetically shields the space between the terminal formation surface 13 of the semiconductor element 1 and the upper surface 21 of the circuit board 2. Therefore, it is possible to prevent noise from being mixed in the signal input to the semiconductor element 1 and the signal output from the semiconductor element 1.

なお、上記第１の実施の形態では、膨張部材５が円環形状である例を説明したが、これに限られない。図７は、半導体装置１００が備える膨張部材５の変形例を示す図であり、半導体素子１の底面図に相当する。   In addition, in the said 1st Embodiment, although the example in which the expansion member 5 was annular shape was demonstrated, it is not restricted to this. FIG. 7 is a view showing a modified example of the expansion member 5 included in the semiconductor device 100 and corresponds to a bottom view of the semiconductor element 1.

半導体装置１００は、膨張部材５に代えて、図７に示す４つの膨張部材５１〜５４を備えてもよい。膨張部材５１〜５４の各々の形状は、直線形状である。膨張部材５１〜５４は、接続端子１２を囲むように、端子形成面１３に固定される。なお、膨張部材５１〜５４の下面は、図１に示す膨張部材５と同様に、回路基板２の上面２１に固定されないが、回路基板２の上面２１と接触している。   The semiconductor device 100 may include four expansion members 51 to 54 shown in FIG. 7 instead of the expansion member 5. The shape of each of the expansion members 51 to 54 is a linear shape. The expansion members 51 to 54 are fixed to the terminal forming surface 13 so as to surround the connection terminal 12. The lower surfaces of the expansion members 51 to 54 are not fixed to the upper surface 21 of the circuit board 2 like the expansion member 5 shown in FIG. 1, but are in contact with the upper surface 21 of the circuit board 2.

以下、膨張部材５１〜５４におけるｘｚ平面に平行な方向におけるサイズについて説明する。図７に示すように、ｘ軸方向に沿って互いに隣り合う２つの接続端子１２の間隔は、Ｄ１である。ｚ軸方向に沿って互いに隣り合う２つの接続端子の間隔は、Ｄ２である。２つの接続端子の間隔は、２つの接続端子の一方の中心から他方の接続端子の中心までの距離により定義される。   Hereinafter, the size of the expansion members 51 to 54 in the direction parallel to the xz plane will be described. As shown in FIG. 7, the distance between the two connection terminals 12 adjacent to each other along the x-axis direction is D1. The distance between two connection terminals adjacent to each other along the z-axis direction is D2. The distance between the two connection terminals is defined by the distance from the center of one of the two connection terminals to the center of the other connection terminal.

膨張部材５１〜５４は、互いに隣り合う２つの接続端子を結ぶ直線に沿って配置され、ｘｚ平面に平行な方向におけるサイズとして、この２つの接続端子の間隔よりも大きいサイズを有する。   The expansion members 51 to 54 are arranged along a straight line connecting two connection terminals adjacent to each other, and have a size in a direction parallel to the xz plane that is larger than a space between the two connection terminals.

例えば、膨張部材５１は、接続端子１２Ａと接続端子１２Ｄとをつなぐ直線に沿って配置され、膨張部材５１のｘ軸方向のサイズは、間隔Ｄ１よりも大きい。また、膨張部材５２は、接続端子１２Ａと接続端子１２Ｂとをつなぐ直線に沿って配置され、膨張部材５２のｚ軸方向のサイズは、間隔Ｄ２よりも大きい。これにより、膨張部材５１〜５４は、図１及び図３に示す膨張部材５と同様に、膨張部材５１〜５４の膨張により発生する応力を、半導体素子１の中心部に作用させることができる。膨張部材５１〜５４は、接続端子１２とはんだ４との接続面に生じる剪断応力を小さくすることができるため、接続端子１２とはんだ４との接続面で発生するクラックを防ぐことができる。   For example, the expansion member 51 is arranged along a straight line connecting the connection terminal 12A and the connection terminal 12D, and the size of the expansion member 51 in the x-axis direction is larger than the distance D1. The expansion member 52 is arranged along a straight line connecting the connection terminal 12A and the connection terminal 12B, and the size of the expansion member 52 in the z-axis direction is larger than the distance D2. Accordingly, the expansion members 51 to 54 can apply the stress generated by the expansion of the expansion members 51 to 54 to the central portion of the semiconductor element 1 as in the expansion member 5 shown in FIGS. 1 and 3. Since the expansion members 51 to 54 can reduce the shear stress generated on the connection surface between the connection terminal 12 and the solder 4, cracks that occur at the connection surface between the connection terminal 12 and the solder 4 can be prevented.

図７では、膨張部材５１〜５４が互いに離間して配置されているが、膨張部材５１〜５４の各々の端部を接触させることにより、膨張部材５１〜５４が、四角い１つの枠を形成してもよい。   In FIG. 7, the expansion members 51 to 54 are arranged apart from each other, but by bringing the respective ends of the expansion members 51 to 54 into contact with each other, the expansion members 51 to 54 form one square frame. May be.

また、半導体装置１００は、図７に示す膨張部材５１〜５４のうち、少なくとも１つを備えていればよい。例えば、半導体装置１００は、図７に示す膨張部材５１のみを備えていてもよく、あるいは、膨張部材５２のみを備えていてもよい。つまり、半導体装置１００が備える膨張部材は、端子形成面１３に固定され、端子形成面１３に形成された互いに隣り合う２つの接続端子を結ぶ直線方向のサイズとして、互いに隣り合う２つの接続端子の間隔よりも大きいサイズを有していればよい。また、膨張部材は、互いに隣りあう２つの接続端子１２の一方側から他方側に向かって伸びるように配置される。   Further, the semiconductor device 100 may include at least one of the expansion members 51 to 54 shown in FIG. 7. For example, the semiconductor device 100 may include only the expansion member 51 shown in FIG. 7, or may include only the expansion member 52. That is, the expansion member included in the semiconductor device 100 is fixed to the terminal forming surface 13 and has a size in a linear direction connecting two connecting terminals adjacent to each other formed on the terminal forming surface 13 and has a size of two connecting terminals adjacent to each other. It only has to have a size larger than the interval. Further, the expansion member is arranged so as to extend from one side of the two adjacent connection terminals 12 toward the other side.

膨張部材の膨張により膨張部材で発生する応力のうちｘｚ平面に平行な方向の応力は、半導体素子１の周縁部に伝わる。周縁部に伝わった応力は、半導体素子１における互いに隣り合う２つの接続端子１２の間の部分に伝わる。この結果、半導体装置１００は、接続端子１２とはんだ４との接続面の剪断応力を小さくすることができる。これにより、半導体素子１は、クラックの発生を抑制することができる。   Of the stress generated in the expansion member due to the expansion of the expansion member, the stress in the direction parallel to the xz plane is transmitted to the peripheral portion of the semiconductor element 1. The stress transmitted to the peripheral portion is transmitted to the portion between the two connection terminals 12 adjacent to each other in the semiconductor element 1. As a result, the semiconductor device 100 can reduce the shear stress on the connection surface between the connection terminal 12 and the solder 4. Thereby, the semiconductor element 1 can suppress the occurrence of cracks.

また、上記実施の形態では、膨張部材５１が、回路基板２の上面２１に接触する例を説明したが、これに限られない。図８は、半導体装置１００の他の変形例の側面断面図である。図８に示すように、膨張部材５の下面が、回路基板２の上面２１に接触しなくてもよい。この場合、金属配線３を回路基板２の上面２１に形成することができるため、回路基板２に形成される金属配線３の設計の自由度を向上させることができる。つまり、半導体装置１００が図８に示す構成を有する場合、金属配線３は、回路基板２の上面２１及び下面２２の少なくとも一方に形成されていればよい。   Further, in the above embodiment, an example in which the expansion member 51 contacts the upper surface 21 of the circuit board 2 has been described, but the present invention is not limited to this. FIG. 8 is a side sectional view of another modification of the semiconductor device 100. As shown in FIG. 8, the lower surface of the expansion member 5 may not contact the upper surface 21 of the circuit board 2. In this case, since the metal wiring 3 can be formed on the upper surface 21 of the circuit board 2, the degree of freedom in designing the metal wiring 3 formed on the circuit board 2 can be improved. That is, when the semiconductor device 100 has the configuration shown in FIG. 8, the metal wiring 3 may be formed on at least one of the upper surface 21 and the lower surface 22 of the circuit board 2.

［第２の実施の形態］
図９は、本発明の第２の実施の形態に係る半導体装置２００の構成を示す側面断面図である。図１０は、図９に示す回路基板２の平面図である。図９及び図１０に示す半導体装置２００が上記第１の実施の形態に係る半導体装置１００と異なる点は、半導体装置２００が、膨張部材５に代えて、挿入部材７と膨張部材８とを備える点である。 [Second Embodiment]
FIG. 9 is a side sectional view showing the configuration of the semiconductor device 200 according to the second embodiment of the present invention. FIG. 10 is a plan view of the circuit board 2 shown in FIG. The semiconductor device 200 shown in FIGS. 9 and 10 is different from the semiconductor device 100 according to the first embodiment described above in that the semiconductor device 200 includes an insertion member 7 and an expansion member 8 instead of the expansion member 5. It is a point.

図１０に示すように、挿入部材７は、回路基板２の上面２１に固定される環状の部材である。挿入部材７は、半導体装置２００を上から下方向に見た場合において、回路基板２の上面２１のうち、半導体素子１と重複する重複領域２１Ａの外周に沿って配置される。従って、半導体装置２００を上から下方向に見た場合、挿入部材７の外周は、半導体素子１の外周と一致する。挿入部材７の上下方向のサイズは、半導体素子１の端子形成面１３と回路基板２の上面２１との間の距離よりも小さい。すなわち、挿入部材７の上面は、半導体素子１の端子形成面１３には接触しない。   As shown in FIG. 10, the insertion member 7 is an annular member fixed to the upper surface 21 of the circuit board 2. The insertion member 7 is arranged along the outer periphery of the overlapping region 21A of the upper surface 21 of the circuit board 2 which overlaps with the semiconductor element 1 when the semiconductor device 200 is viewed from above. Therefore, when the semiconductor device 200 is viewed from above, the outer periphery of the insertion member 7 matches the outer periphery of the semiconductor element 1. The vertical size of the insertion member 7 is smaller than the distance between the terminal formation surface 13 of the semiconductor element 1 and the upper surface 21 of the circuit board 2. That is, the upper surface of the insertion member 7 does not contact the terminal formation surface 13 of the semiconductor element 1.

挿入部材７は、例えば、はんだや、めっき材や樹脂などで形成される。また、挿入部材７は、膨張部材８と密着性の悪いめっき材により形成されてもよいし、回路基板２上に形成された銅などを用いてもよい。   The insertion member 7 is formed of, for example, solder, plated material, resin, or the like. Further, the insertion member 7 may be formed of a plated material having poor adhesion to the expansion member 8, or copper or the like formed on the circuit board 2 may be used.

膨張部材８は、半導体素子１の端子形成面１３と、回路基板２の上面２１との間の空間に充填される樹脂である。膨張部材８が、半導体素子１の端子形成面１３に固定されている。膨張部材８は、回路基板２の上面２１における重複領域２１Ａのうち、挿入部材７が形成されていない領域に固定される。つまり、挿入部材７は、回路基板２の上面２１と、膨張部材８の下面のうち回路基板２の上面２１と接触しない非接触面との間に配置される。また、膨張部材８は、挿入部材７の上面に固定される。膨張部材８の線膨張係数は、半導体素子１の線膨張係数よりも大きく、回路基板２及び金属配線３の線膨張係数よりも大きい。膨張部材８の線膨張係数は、好ましくは、１０〜３３×１０−６（１／Ｋ）であり、さらに好ましくは、１４〜３０×１０−６（１／Ｋ）である。 The expansion member 8 is a resin that fills the space between the terminal formation surface 13 of the semiconductor element 1 and the upper surface 21 of the circuit board 2. The expansion member 8 is fixed to the terminal forming surface 13 of the semiconductor element 1. The expansion member 8 is fixed to a region where the insertion member 7 is not formed in the overlapping region 21A on the upper surface 21 of the circuit board 2. That is, the insertion member 7 is disposed between the upper surface 21 of the circuit board 2 and the non-contact surface of the lower surface of the expansion member 8 that does not contact the upper surface 21 of the circuit board 2. The expansion member 8 is fixed to the upper surface of the insertion member 7. The linear expansion coefficient of the expansion member 8 is larger than the linear expansion coefficient of the semiconductor element 1 and larger than the linear expansion coefficient of the circuit board 2 and the metal wiring 3. The linear expansion coefficient of the expansion member 8 is preferably 10 to 33×10 −6 (1/K), and more preferably 14 to 30×10 −6 (1/K).

膨張部材８は、端子形成面１３の全体にわたって固定されるため、膨張部材８のｘｚ平面方向に平行な方向のサイズは、互いに隣接する２つの接続端子１２の間隔よりも大きい。   Since the expansion member 8 is fixed over the entire terminal forming surface 13, the size of the expansion member 8 in the direction parallel to the xz plane direction is larger than the distance between the two connection terminals 12 adjacent to each other.

上述のように、半導体装置２００は、膨張部材５に代えて、膨張部材８を有する。これにより、半導体装置２００は、半導体装置１００と同様に、接続端子１２とはんだ４との接続面におけるクラックの発生を抑制することができる。以下、詳しく説明する。   As described above, the semiconductor device 200 has the expansion member 8 instead of the expansion member 5. As a result, the semiconductor device 200, like the semiconductor device 100, can suppress the occurrence of cracks on the connection surface between the connection terminal 12 and the solder 4. The details will be described below.

図１１は、半導体装置２００で発生する応力を示す図である。図１１において、スルーホール、層間接続部、パターン部の符号の表示を省略している。   FIG. 11 is a diagram showing stress generated in the semiconductor device 200. In FIG. 11, the reference numerals of the through holes, the interlayer connection parts, and the pattern parts are omitted.

図１１に示すように、膨張部材８は、半導体素子１で発生する熱又は熱源からの熱によって膨張し、ｘｚ平面に平行な方向に向かって伸びる。膨張部材８の伸びに伴って、ｘｚ平面に平行な方向に向かう応力８１が膨張部材８で発生する。また、半導体素子１において応力６１が発生し、回路基板２において、応力６０が発生する。膨張部材８の線膨張係数は、半導体素子１の線膨張係数よりも大きく、回路基板２及び金属配線３の線膨張係数より大きくい。このため、応力８１は、応力６０及び応力６１よりも大きい。   As shown in FIG. 11, the expansion member 8 expands due to the heat generated in the semiconductor element 1 or the heat from the heat source, and extends in a direction parallel to the xz plane. Along with the expansion of the expansion member 8, a stress 81 directed in a direction parallel to the xz plane is generated in the expansion member 8. Further, stress 61 is generated in the semiconductor element 1 and stress 60 is generated in the circuit board 2. The linear expansion coefficient of the expansion member 8 is larger than the linear expansion coefficient of the semiconductor element 1 and smaller than the linear expansion coefficient of the circuit board 2 and the metal wiring 3. Therefore, the stress 81 is larger than the stress 60 and the stress 61.

膨張部材８が、半導体素子１の端子形成面１３と、回路基板２の上面２１における重複領域２１Ａのうち挿入部材７が形成されていない領域とに固定されている。このため、半導体素子１と、回路基板２とは、膨張部材８から応力８１を受ける。   The expansion member 8 is fixed to the terminal formation surface 13 of the semiconductor element 1 and the area of the upper surface 21 of the circuit board 2 where the insertion member 7 is not formed in the overlapping area 21A. Therefore, the semiconductor element 1 and the circuit board 2 receive the stress 81 from the expansion member 8.

半導体素子１が膨張部材８から受ける応力８１について説明する。膨張部材８が半導体素子１の端子形成面１３に固定されているため、半導体素子１は、膨張部材８の伸びに伴う応力８１を、端子形成面１３全体から受ける。つまり、半導体素子１は、ｘｚ平面の平行な方向であり、かつ、半導体素子１の外方向に広がる力を、膨張部材８から受ける。この結果、半導体素子１の中心部及び周縁部において、応力６１と応力８１とが合成された合成応力６４が発生する。合成応力６４は、半導体素子１の膨張に伴って発生する応力６１よりも大きい。   The stress 81 that the semiconductor element 1 receives from the expansion member 8 will be described. Since the expansion member 8 is fixed to the terminal formation surface 13 of the semiconductor element 1, the semiconductor element 1 receives the stress 81 associated with the expansion of the expansion member 8 from the entire terminal formation surface 13. That is, the semiconductor element 1 receives from the expansion member 8 a force that is in a direction parallel to the xz plane and that spreads outward of the semiconductor element 1. As a result, a synthetic stress 64, which is a combination of the stress 61 and the stress 81, is generated in the central portion and the peripheral portion of the semiconductor element 1. The synthetic stress 64 is larger than the stress 61 generated as the semiconductor element 1 expands.

回路基板２が膨張部材８から受ける応力について説明する。膨張部材８は、回路基板２の上面２１における重複領域２１Ａのうち一部の領域に固定されている。ここで、一部の領域とは、重複領域２１Ａのうち、挿入部材７が形成された領域を除く領域である。このため、回路基板２は、上記の一部の領域において、膨張部材８で発生する応力８１を受ける。従って、回路基板２のうち、膨張部材５が固定された部分では、回路基板２で発生する応力６０と、膨張部材８から受ける応力８１の一部とが合成された合成応力６５が発生する。   The stress that the circuit board 2 receives from the expansion member 8 will be described. The expansion member 8 is fixed to a part of the overlapping area 21A on the upper surface 21 of the circuit board 2. Here, the partial area is an area of the overlapping area 21A excluding the area where the insertion member 7 is formed. Therefore, the circuit board 2 receives the stress 81 generated in the expansion member 8 in the above-mentioned partial area. Therefore, in the portion of the circuit board 2 to which the expansion member 5 is fixed, a synthetic stress 65 that is a combination of the stress 60 generated in the circuit board 2 and a part of the stress 81 received from the expansion member 8 is generated.

しかし、上記の一部の領域は、半導体素子１の端子形成面１３よりも狭い。また、後述するように、挿入部材７が、膨張部材８から回路基板２に伝わる応力８１を吸収する。従って、膨張部材８から回路基板２に伝わる応力８１は、膨張部材８から半導体素子１の端子形成面１３に伝わる応力８１よりも小さい。この結果、合成応力６４と合成応力６５との差は、回路基板２及び金属配線３で発生する応力６０と、半導体素子１で発生する応力６１との差よりも小さくなるため、半導体装置２００は、接続端子１２とはんだ４との接続面で生じる剪断応力を小さくすることができる。従って、半導体装置２００は、接続端子１２とはんだ４との接続面で発生するクラックを抑制することができる。   However, the above-mentioned part of the region is narrower than the terminal formation surface 13 of the semiconductor element 1. Further, as will be described later, the insertion member 7 absorbs the stress 81 transmitted from the expansion member 8 to the circuit board 2. Therefore, the stress 81 transmitted from the expansion member 8 to the circuit board 2 is smaller than the stress 81 transmitted from the expansion member 8 to the terminal formation surface 13 of the semiconductor element 1. As a result, the difference between the synthetic stress 64 and the synthetic stress 65 is smaller than the difference between the stress 60 generated in the circuit board 2 and the metal wiring 3 and the stress 61 generated in the semiconductor element 1, so that the semiconductor device 200 is It is possible to reduce the shear stress generated at the connection surface between the connection terminal 12 and the solder 4. Therefore, the semiconductor device 200 can suppress cracks generated on the connection surface between the connection terminal 12 and the solder 4.

はんだ４で発生する応力４１については、図１１に示していないが、半導体装置２００は、半導体装置１００と同様に、半導体素子１の線膨張係数とはんだ４の線膨張係数との差に起因する剪断応力を小さくすることができる。   Although the stress 41 generated in the solder 4 is not shown in FIG. 11, the semiconductor device 200 is caused by the difference between the linear expansion coefficient of the semiconductor element 1 and the linear expansion coefficient of the solder 4, like the semiconductor device 100. Shear stress can be reduced.

また、半導体素子１が、端子形成面１３全体で応力８１を受けるため、半導体装置２００は、半導体装置１００と同様に、半導体素子１で発生する応力の局所的な差を小さくすることができる。半導体装置２００は、半導体素子１の反りを抑制することができるため、接続端子１２とはんだ４との接続面で発生するクラックを抑制することができる。   Further, since the semiconductor element 1 receives the stress 81 on the entire terminal forming surface 13, the semiconductor device 200 can reduce the local difference in stress generated in the semiconductor element 1 as in the semiconductor device 100. Since the semiconductor device 200 can suppress the warpage of the semiconductor element 1, it is possible to suppress cracks generated on the connection surface between the connection terminal 12 and the solder 4.

以下、挿入部材７が膨張部材８から回路基板２に伝わる応力８１を吸収する理由について説明する。膨張部材８の線膨張係数が、上述のように、回路基板２及び金属配線３の各々の線膨張係数よりも大きいため、ｘｚ平面に平行な方向への膨張部材８の伸びは、ｘｚ平面に平行な方向への回路基板２及び金属配線３の伸びよりも大きい。また、挿入部材７は、回路基板２の上面２１に固定されている。   Hereinafter, the reason why the insertion member 7 absorbs the stress 81 transmitted from the expansion member 8 to the circuit board 2 will be described. Since the linear expansion coefficient of the expansion member 8 is larger than the linear expansion coefficient of each of the circuit board 2 and the metal wiring 3 as described above, the expansion of the expansion member 8 in the direction parallel to the xz plane is in the xz plane. It is larger than the extension of the circuit board 2 and the metal wiring 3 in the parallel direction. The insertion member 7 is fixed to the upper surface 21 of the circuit board 2.

この結果、挿入部材７と膨張部材８との接続面において、ｘｚ平面に平行な剪断応力が発生する。そして、挿入部材７の上面が、挿入部材７の下面に対してｘｚ平面に平行な方向にずれるように移動する。この結果、挿入部材７は、膨張部材８から伝わる応力８１を吸収することができる。挿入部材７が応力８１を吸収することにより、回路基板２の上面２１における重複領域２１Ａのうち、挿入部材７が形成された領域には、膨張部材８で発生する応力が伝わりにくくなる。従って、膨張部材８から回路基板２に伝わる応力８１は、膨張部材８から半導体素子１に伝わる応力８１よりも小さくなる。   As a result, shear stress parallel to the xz plane is generated at the connection surface between the insertion member 7 and the expansion member 8. Then, the upper surface of the insertion member 7 moves so as to deviate from the lower surface of the insertion member 7 in the direction parallel to the xz plane. As a result, the insertion member 7 can absorb the stress 81 transmitted from the expansion member 8. Since the insertion member 7 absorbs the stress 81, the stress generated in the expansion member 8 is less likely to be transmitted to the region where the insertion member 7 is formed in the overlapping region 21A on the upper surface 21 of the circuit board 2. Therefore, the stress 81 transmitted from the expansion member 8 to the circuit board 2 is smaller than the stress 81 transmitted from the expansion member 8 to the semiconductor element 1.

また、挿入部材７と膨張部材８との接触面又は膨張部材８の内部で発生する応力が、大きくなった場合、膨張部材８が挿入部材７から剥離するか、あるいは、膨張部材８が破壊される。挿入部材７から剥離した膨張部材８又は破壊された膨張部材８は、挿入部材７に対して相対的に移動する。この場合、膨張部材８で発生する応力８１が挿入部材７に伝わらないため、膨張部材８から回路基板２に伝わる応力８１が膨張部材８から半導体素子１に伝わる応力８１よりも小さい状態が継続される。従って、膨張部材８が挿入部材７から剥離した場合であっても、接続端子１２とはんだ４との接続面で発生するクラックを抑制することができる。   When the stress generated in the contact surface between the insertion member 7 and the expansion member 8 or inside the expansion member 8 increases, the expansion member 8 is separated from the insertion member 7 or the expansion member 8 is destroyed. It The expansion member 8 separated from the insertion member 7 or the destroyed expansion member 8 moves relative to the insertion member 7. In this case, since the stress 81 generated in the expansion member 8 is not transmitted to the insertion member 7, the stress 81 transmitted from the expansion member 8 to the circuit board 2 remains smaller than the stress 81 transmitted from the expansion member 8 to the semiconductor element 1. It Therefore, even when the expansion member 8 is peeled off from the insertion member 7, it is possible to suppress cracks generated on the connection surface between the connection terminal 12 and the solder 4.

なお、第２の実施の形態において、半導体装置２００が、挿入部材７を備える例を説明したが、これに限られない。半導体装置２００は、挿入部材７を備えなくてもよい。この場合、図１２に示すように、膨張部材８の下面において、回路基板２の上面２１と接触しない領域があればよい。つまり、回路基板２の上面２１に対向する膨張部材８の下面は、上面２１に接触する接触面８３と、上面２１に接触しない非接触面８４とを備えていればよい。この場合であっても、回路基板２の重複領域２１Ａにおいて、膨張部材８で発生する応力２１を直接受ける領域を小さくすることができるため、接続端子１２とはんだ４との接続面においてクラックが発生することを防ぐことができる。   In addition, in the second embodiment, an example in which the semiconductor device 200 includes the insertion member 7 has been described, but the present invention is not limited to this. The semiconductor device 200 may not include the insertion member 7. In this case, as shown in FIG. 12, a region on the lower surface of the expansion member 8 that does not contact the upper surface 21 of the circuit board 2 may be used. That is, the lower surface of the expansion member 8 facing the upper surface 21 of the circuit board 2 may be provided with the contact surface 83 that contacts the upper surface 21 and the non-contact surface 84 that does not contact the upper surface 21. Even in this case, in the overlapping area 21A of the circuit board 2, since the area directly receiving the stress 21 generated in the expansion member 8 can be reduced, a crack is generated in the connection surface between the connection terminal 12 and the solder 4. Can be prevented.

また、図１２に示すように、半導体装置２００が挿入部材７を備えない場合、金属配線３Ａ〜３Ｆを、回路基板２の上面２１に形成してもよい。つまり、半導体装置２００が図１２に示す構成を有する場合、金属配線３は、回路基板２の上面２１及び下面２２の少なくとも一方に形成されていればよい。   Further, as shown in FIG. 12, when the semiconductor device 200 does not include the insertion member 7, the metal wirings 3A to 3F may be formed on the upper surface 21 of the circuit board 2. That is, when the semiconductor device 200 has the configuration shown in FIG. 12, the metal wiring 3 may be formed on at least one of the upper surface 21 and the lower surface 22 of the circuit board 2.

また、第２の実施の形態において、挿入部材７の形状が環状である例を説明したが、これに限られない。挿入部材７は、回路基板２の上面２１と、膨張部材８の非接触面８４との間に挿入される部材であり、膨張部材８が挿入部材の上面（端子形成面１３に対向する面）に固定されていれば、挿入部材７の形状及び挿入部材７の位置は特に限定されない。   Further, in the second embodiment, an example in which the shape of the insertion member 7 is annular has been described, but the present invention is not limited to this. The insertion member 7 is a member inserted between the upper surface 21 of the circuit board 2 and the non-contact surface 84 of the expansion member 8, and the expansion member 8 is the upper surface of the insertion member (the surface facing the terminal formation surface 13). The shape of the insertion member 7 and the position of the insertion member 7 are not particularly limited as long as they are fixed to the position.

なお、上記実施の形態において、半導体素子１が、接続端子１２Ａ〜１２Ｆを備える例を説明したが、これに限られない。半導体素子１は、少なくとも２つの接続端子を有し、少なくとも２つの接続端子が端子形成面１３に配置されていればよい。   In addition, in the said embodiment, although the semiconductor element 1 demonstrated the example provided with the connection terminals 12A-12F, it is not restricted to this. The semiconductor element 1 may have at least two connection terminals, and at least two connection terminals may be arranged on the terminal formation surface 13.

また、上記実施の形態において、半導体素子１が、横型半導体素子である例を説明したが、これに限られない。半導体素子１における端子形成面１３以外の面に、接続端子１２が設けられていてもよい。   Further, in the above-described embodiment, an example in which the semiconductor element 1 is a lateral semiconductor element has been described, but the present invention is not limited to this. The connection terminal 12 may be provided on a surface of the semiconductor element 1 other than the terminal formation surface 13.

以上、本発明の実施の形態を説明したが、上述した実施の形態は本発明を実施するための例示に過ぎない。よって、本発明は上述した実施の形態に限定されることなく、その趣旨を逸脱しない範囲内で上述した実施の形態を適宜変形して実施することが可能である。   Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiments, and can be implemented by appropriately modifying the above-described embodiments without departing from the spirit of the present invention.

１００，２００ 半導体装置
１ 半導体素子
２ 回路基板
３Ａ〜３Ｆ 金属配線
４ はんだ
５，８ 膨張部材
７ 挿入部材
１１ 筐体
１２Ａ〜１２Ｆ 接続端子
１３ 端子形成面 100, 200 Semiconductor device 1 Semiconductor element 2 Circuit board 3A to 3F Metal wiring 4 Solder 5, 8 Expansion member 7 Insertion member 11 Housing 12A to 12F Connection terminal 13 Terminal formation surface

Claims (4)

第１の面と、前記第１の面に対向する第２の面とを有する回路基板と、
前記第１の面及び前記第２の面の少なくとも一方に形成される少なくとも２つの金属配線と、
前記第１の面に対向するように配置された端子形成面において、少なくとも２つの接続端子が形成されている半導体素子と、
前記少なくとも２つの接続端子の各々と前記少なくとも２つの金属配線の各々とを電気的に接続するはんだと、
前記半導体素子の前記端子形成面に固定され、前記半導体素子の線膨張係数よりも大きい線膨張係数を有し、前記少なくとも２つの接続端子のうち互いに隣り合う２つの接続端子の間隔よりも大きいサイズを有する膨張部材と、
を備え、
前記膨張部材は、前記金属配線の線膨張係数よりも大きい線膨張係数を有し、
前記膨張部材において前記第１の面に対向する面は、前記第１の面に接触する接触面と、前記第１の面に接触しない非接触面とを有する半導体装置。 A circuit board having a first surface and a second surface facing the first surface;
At least two metal wirings formed on at least one of the first surface and the second surface;
A semiconductor element having at least two connection terminals formed on a terminal formation surface arranged to face the first surface;
Solder for electrically connecting each of the at least two connection terminals and each of the at least two metal wirings,
A size fixed to the terminal formation surface of the semiconductor element, having a coefficient of linear expansion larger than that of the semiconductor element, and larger than a distance between two adjacent connection terminals of the at least two connection terminals. An inflatable member having
Equipped with
The expansion member has a linear expansion coefficient larger than that of the metal wiring,
A surface of the expansion member that faces the first surface has a contact surface that contacts the first surface and a non-contact surface that does not contact the first surface. 請求項１に記載の半導体装置であって、
前記膨張部材が、１０〜３３×１０−６（１／Ｋ）の範囲内の線膨張係数を有する半導体装置。 The semiconductor device according to claim 1, wherein
The semiconductor device in which the expansion member has a linear expansion coefficient within a range of 10 to 33×10 −6 (1/K). 請求項１に記載の半導体装置であって、さらに、
前記第１の面と前記非接触面との間に挿入され、前記膨張部材の線膨張係数よりも小さい線膨張係数を有する挿入部材、
を備える半導体装置。 The semiconductor device according to claim 1, further comprising:
An insertion member inserted between the first surface and the non-contact surface and having a linear expansion coefficient smaller than that of the expansion member,
A semiconductor device comprising: 請求項３に記載の半導体装置であって、
前記膨張部材は、前記端子形成面と対向する面に固定され、
前記挿入部材が前記第１の面と前記非接触面との間に配置される半導体装置。
The semiconductor device according to claim 3 , wherein
The expansion member is fixed to a surface facing the terminal formation surface,
A semiconductor device in which the insertion member is arranged between the first surface and the non-contact surface.
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