JP2009071251A - Flip chip bga substrate - Google Patents

Flip chip bga substrate Download PDF

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JP2009071251A
JP2009071251A JP2007241112A JP2007241112A JP2009071251A JP 2009071251 A JP2009071251 A JP 2009071251A JP 2007241112 A JP2007241112 A JP 2007241112A JP 2007241112 A JP2007241112 A JP 2007241112A JP 2009071251 A JP2009071251 A JP 2009071251A
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substrate
silicon chip
chip
flip
bga
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Chikako Kato
知香子 加藤
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Yokogawa Electric Corp
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Yokogawa Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip chip BGA substrate in which warpage is decreased without increasing shearing stress which is applied to a bump, in a flip chip BGA package. <P>SOLUTION: In a flip chip BGA substrate 13, a groove 18 is formed like the outline of the silicon chip 11 or along an outside perimeter on the surface of the substrate 13 which corresponds to the backside of a mounted position in which a silicon chip 11 is mounted. Thereby, since distortion caused by the deformation of the silicon chip mounted part is absorbed, warpage is decreased. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、各種ＩＣのフリップチップＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ：ボールグリッドアレイ）パッケージ基板に関するもので、より詳細には、シリコンチップが実装される部位に溝或いは窪みを設けて基板全体の反りを低減させたフリップチップＢＧＡ基板に関する。   The present invention relates to a flip chip BGA (Ball Grid Array) package substrate for various ICs, and more specifically, a groove or a recess is provided in a portion where a silicon chip is mounted to reduce warpage of the entire substrate. The present invention relates to a flip chip BGA substrate.

従来技術において、シリコンチップは、図７に示すように、バンプ１１２によりパッケージ基板１１３にフリップチップ接合され、パッケージ基板内部の配線によりＢＧＡはんだボール１１４に電気的に接続されている。   In the prior art, as shown in FIG. 7, the silicon chip is flip-chip bonded to the package substrate 113 by bumps 112 and electrically connected to the BGA solder balls 114 by wiring inside the package substrate.

フリップチップＢＧＡパッケージ構造では、シリコンチップ１１１とパッケージ基板１１３との間にアンダーフィル材１１５と呼ばれる樹脂を充填し、シリコンチップ１１１とパッケージ基板１１３を平面で接着する構造をとる。
フリップチップ接合は、高温下で行われることが多く、シリコンチップ１１１とパッケージ基板１１３との熱膨張係数差により接合終了後の常温状態ではシリコンチップ１１１側が凸になるようにシリコンチップ１１１とパッケージ基板１１３が反る。
この反りにより、シリコンチップ１１１とパッケージ基板１１３の接合面同士の相対位置が維持されるため、接続バンプ１１２にかかるせん断応力が低減されている。
特開２００７−２７６９９号公報（図１） In the flip chip BGA package structure, a resin called an underfill material 115 is filled between the silicon chip 111 and the package substrate 113, and the silicon chip 111 and the package substrate 113 are bonded in a plane.
Flip chip bonding is often performed at a high temperature, and the silicon chip 111 and the package substrate are projected so that the silicon chip 111 side is convex in a normal temperature state after the bonding is completed due to a difference in thermal expansion coefficient between the silicon chip 111 and the package substrate 113. 113 warps.
By this warpage, the relative position between the bonding surfaces of the silicon chip 111 and the package substrate 113 is maintained, so that the shear stress applied to the connection bump 112 is reduced.
JP 2007-27699 A (FIG. 1)

しかしながら、従来技術で説明したシリコンチップとパッケージ基板の熱膨張係数差による反りは、ＢＧＡパッケージ全体の反りとなり、ＢＧＡはんだボール面の平坦性（コプラナリティ）に影響する。平坦性が悪いと、マザーボードへの部品マウント時に問題となる。シリコンチップが大きい場合、パッケージ基板が大きい場合は特に深刻である。
又、図８に示すように、マザーボード１１６への部品実装後にも、ＢＧＡはんだボール１１４に大きい変形を発生させ、ＢＧＡパッケージとマザーボード１１６との接続信頼性の低下をもたらす。
一般的に、パッケージ全体の反りを低減するために、図９に示すように、スティフナ１１７と呼ばれる補強部材を接着する方法がとられているが、この場合、パッケージ基板１１３を強制的に変形させるために、フリップチップ接続バンプ１１２に加わるせん断応力が増加し、シリコンチップ１１１とパッケージ基板１１３との接続強度の低下をもたらす。 However, the warp due to the difference in thermal expansion coefficient between the silicon chip and the package substrate described in the prior art becomes the warp of the entire BGA package and affects the flatness (coplanarity) of the BGA solder ball surface. If the flatness is poor, there will be a problem when mounting components on the motherboard. This is especially serious when the silicon chip is large and the package substrate is large.
Further, as shown in FIG. 8, even after the components are mounted on the mother board 116, the BGA solder balls 114 are greatly deformed, and the connection reliability between the BGA package and the mother board 116 is lowered.
In general, in order to reduce the warpage of the entire package, a method of adhering a reinforcing member called a stiffener 117 as shown in FIG. 9 is used. In this case, the package substrate 113 is forcibly deformed. Therefore, the shear stress applied to the flip chip connection bump 112 is increased, and the connection strength between the silicon chip 111 and the package substrate 113 is lowered.

従って、フリップチップ接続バンプに加わるせん断応力を増加させることなくパッケージの反りを抑えることができるパッケージ基板を実現することに解決しなければならない課題を有する。   Therefore, there is a problem to be solved by realizing a package substrate that can suppress the warpage of the package without increasing the shear stress applied to the flip chip connection bump.

上記課題を解決するために、本願発明のフリップチップＢＧＡ基板は、次に示す構成にしたことである。   In order to solve the above problems, the flip chip BGA substrate of the present invention is configured as follows.

（１）フリップチップＢＧＡ基板は、フリップチップＢＧＡパッケージに用いられる基板において、前記基板は、シリコンチップが実装される実装位置の裏面に相当する基板表面に、シリコンチップ外形と同じか、又は外側外周に沿って溝を形成したことである。
（２）フリップチップＢＧＡ基板は、フリップチップＢＧＡパッケージに用いられる基板において、前記基板は、シリコンチップが実装される実装位置と同じ基板表面に、シリコンチップ外形よりも外側外周に沿って溝を形成したことである。
（３）フリップチップＢＧＡ基板は、フリップチップＢＧＡパッケージに用いられる基板において、前記基板は、シリコンチップが実装される実装位置の裏面に相当する基板表面に、シリコンチップ外形よりも大きく板厚を薄くした窪み部分を形成したことである。 (1) The flip chip BGA substrate is a substrate used for a flip chip BGA package, and the substrate is the same as the outer shape of the silicon chip on the substrate surface corresponding to the back surface of the mounting position where the silicon chip is mounted, or the outer periphery. A groove is formed along the line.
(2) The flip-chip BGA substrate is a substrate used for a flip-chip BGA package, and the substrate has a groove formed on the same substrate surface as the mounting position on which the silicon chip is mounted along the outer periphery outside the outer shape of the silicon chip. It is that.
(3) The flip-chip BGA substrate is a substrate used for a flip-chip BGA package, and the substrate has a thickness larger than the outer shape of the silicon chip on the substrate surface corresponding to the back surface of the mounting position where the silicon chip is mounted. It is that the hollow part which was made was formed.

本発明においては、パッケージ基板のシリコンチップを実装する位置に溝或いは窪みを形成する構造にしたことにより、フリップチップＢＧＡパッケージの反りが低減するため、スティフナ形成の必要がなくなる。又は、スティフナを形成しても、溝により形成される板厚の薄い部分で歪が吸収され、フリップチップ接続バンプへのせん断応力の増加が抑えられる。
更に、本願発明のフリップチップＢＧＡパッケージは、マザーボードに部品実装された後のＢＧＡはんだボールの変形が小さいため、ＢＧＡはんだボールの接続信頼性が向上する。 In the present invention, since the groove or the recess is formed at the position where the silicon chip of the package substrate is mounted, the warp of the flip chip BGA package is reduced, so that it is not necessary to form a stiffener. Alternatively, even when the stiffener is formed, strain is absorbed by the thin plate portion formed by the groove, and an increase in shear stress to the flip chip connection bump is suppressed.
Further, since the flip chip BGA package of the present invention has a small deformation of the BGA solder ball after being mounted on the mother board, the connection reliability of the BGA solder ball is improved.

次に、本願発明に係るフリップチップＢＧＡ基板の実施例について図面を参照して説明する。   Next, an example of a flip chip BGA substrate according to the present invention will be described with reference to the drawings.

本願発明の第１実施例のフリップチップＢＧＡ基板は、図１及び図２に示すように、パッケージ基板１３の上面に搭載されるシリコンチップ１１がフリップチップ実装される位置の裏面に、シリコンチップ１１の外形と同じか、または外側外周に沿って溝１８を形成する。
この溝１８は、ルータやレーザ加工によって形成が可能であり、パッケージ基板１３の板厚の約半分程度を切り欠いて形成されている。 As shown in FIGS. 1 and 2, the flip chip BGA substrate according to the first embodiment of the present invention has a silicon chip 11 on the back surface where the silicon chip 11 mounted on the upper surface of the package substrate 13 is flip-chip mounted. A groove 18 is formed along the outer periphery of the outer periphery.
The groove 18 can be formed by a router or laser processing, and is formed by cutting out about half the plate thickness of the package substrate 13.

図３は、パッケージ基板１３にシリコンチップ１１をフリップチップ実装した構造の断面図であり、バンプ１２によりパッケージ基板１３にフリップチップ接合され、パッケージ基板１３内部の配線によりＢＧＡはんだボール１４に電気的に接続されている。シリコンチップ１１とパッケージ基板１３との間にアンダーフィル材１５と呼ばれる樹脂を充填し、シリコンチップ１１とパッケージ基板１３を平面で接着する構造となっている。
このようにして生成されたフリップチップＢＧＡ基板は、シリコンチップ１１とパッケージ基板１３との熱膨張係数差によりパッケージ基板１３に反りが発生するが、溝１８によりパッケージ基板１３の板厚の薄い（剛性の低い）部分が形成されているため、シリコンチップ実装部分の変形による歪が吸収され、溝１８のない場合に比べて基板全体の反りが低減される。 FIG. 3 is a cross-sectional view of a structure in which the silicon chip 11 is flip-chip mounted on the package substrate 13, which is flip-chip bonded to the package substrate 13 by the bumps 12 and electrically connected to the BGA solder balls 14 by the wiring inside the package substrate 13. It is connected. A structure called an underfill material 15 is filled between the silicon chip 11 and the package substrate 13, and the silicon chip 11 and the package substrate 13 are bonded in a plane.
In the flip chip BGA substrate thus generated, the package substrate 13 is warped due to the difference in thermal expansion coefficient between the silicon chip 11 and the package substrate 13, but the thickness of the package substrate 13 is thin due to the groove 18 (rigidity). Therefore, the distortion due to the deformation of the silicon chip mounting portion is absorbed, and the warpage of the entire substrate is reduced as compared with the case without the groove 18.

図４は、溝１８を形成したフリップチップＢＧＡ基板であるパッケージ基板１３をマザーボード１６に部品実装した断面図であり、実装後のＢＧＡはんだボール１４の変形は溝１８のない場合に比べて低減される。バンプ１２でフリップチップ接合されたシリコンチップ１１とパッケージ基板１３の凸状の反りはそのままにして、反りから外れた位置に設けた溝１８によりマザーボード１６上にパッケージ基板１３が装着されるため、反りの部分のバンプ１２へのせん断応力は増加せすその分シリコンチップ１１とパッケージ基板１３との接続強度を維持或いは増加させることができる。   FIG. 4 is a cross-sectional view in which a package substrate 13, which is a flip-chip BGA substrate in which grooves 18 are formed, is mounted on a mother board 16, and deformation of the BGA solder balls 14 after mounting is reduced compared to the case without the grooves 18. The Since the convex warpage of the silicon chip 11 and the package substrate 13 flip-chip bonded by the bumps 12 is left as it is, the package substrate 13 is mounted on the mother board 16 by the groove 18 provided at a position away from the warpage. As the shear stress applied to the bump 12 in this portion increases, the connection strength between the silicon chip 11 and the package substrate 13 can be maintained or increased.

次に、本願発明の第２実施例のフリップチップＢＧＡ基板について、図面を参照して説明する。 Next, a flip chip BGA substrate according to a second embodiment of the present invention will be described with reference to the drawings.

第２実施例のフリップチップＢＧＡ基板は、図５に示すように、シリコンチップ１１が実装される実装位置と同じ基板表面に、シリコンチップ外形よりも外側外周に沿って溝１９を形成した構造となっている。
この場合も、シリコンチップ１１とパッケージ基板１３との熱膨張係数差によりパッケージ基板１３に反りが発生するが、実装したシリコンチップ１１側の基板面に設けた溝１９によりパッケージ基板１３の板厚の薄い（剛性の低い）部分が形成されているため、シリコンチップ実装部分の変形による歪が吸収され、溝１９のない場合に比べて基板全体の反りが低減される。 As shown in FIG. 5, the flip chip BGA substrate of the second embodiment has a structure in which grooves 19 are formed on the same substrate surface as the mounting position where the silicon chip 11 is mounted along the outer periphery outside the silicon chip outer shape. It has become.
Also in this case, the package substrate 13 is warped due to the difference in thermal expansion coefficient between the silicon chip 11 and the package substrate 13, but the thickness of the package substrate 13 is reduced by the groove 19 provided on the substrate surface on the mounted silicon chip 11 side. Since the thin (low rigidity) portion is formed, the distortion due to the deformation of the silicon chip mounting portion is absorbed, and the warpage of the entire substrate is reduced as compared with the case without the groove 19.

次に、本願発明の第３実施例のフリップチップＢＧＡ基板について、図面を参照して説明する。 Next, a flip chip BGA substrate according to a third embodiment of the present invention will be described with reference to the drawings.

第３実施例のフリップチップＢＧＡ基板は、図６に示すように、シリコンチップ１１が実装される実装位置の裏面に相当するパッケージ基板１３表面に、シリコンチップ１１外形よりも大きく板厚を薄くした窪み部分２１を形成した構造となっている。
この場合、ＢＧＡは窪み部分２１にＢＧＡはんだボール１４を配置することができないためフルグリッドにはできない。シリコンチップ実装部分全体のパッケージ基板１３の板厚が薄いため、この窪み部分２１の変形は大きくなるが、パッケージ基板１３全体の変形は抑えられる。
この窪み部分２１を作成するためには、完成基板のルータ加工、レーザ加工の他に、予め穴を形成した基板を積層する方法でも可能である。 As shown in FIG. 6, the flip chip BGA substrate of the third embodiment has a plate thickness that is larger than the outer shape of the silicon chip 11 on the surface of the package substrate 13 corresponding to the back surface of the mounting position where the silicon chip 11 is mounted. The hollow portion 21 is formed.
In this case, the BGA cannot be a full grid because the BGA solder balls 14 cannot be disposed in the recessed portion 21. Since the thickness of the package substrate 13 of the entire silicon chip mounting portion is thin, the deformation of the recessed portion 21 is increased, but the deformation of the entire package substrate 13 can be suppressed.
In order to create the hollow portion 21, in addition to router processing and laser processing of a completed substrate, a method of laminating a substrate in which holes are formed in advance is also possible.

パッケージ基板のシリコンチップを実装する位置に溝或いは窪みを形成する構造にしたことにより、フリップチップＢＧＡパッケージの反りへの影響を低減させるためのフリップチップＢＧＡ基板を提供する。 A flip chip BGA substrate for reducing the influence on the warp of the flip chip BGA package is provided by forming a groove or a recess at a position where the silicon chip of the package substrate is mounted.

本願発明の第１実施例のフリップチップＢＧＡ基板の断面図である。It is sectional drawing of the flip chip BGA board | substrate of 1st Example of this invention. 同、パッケージ基板の裏面からみた溝の様子を示す平面図である。It is a top view which shows the mode of the groove | channel seen from the back surface of the package substrate. 同、シリコンチップをフリップチップした様子を示す説明図である。It is explanatory drawing which shows a mode that the silicon chip was flip-chip same as the above. 同、マザーボードに取り付けた様子を示す説明図である。It is explanatory drawing which shows a mode that it was attached to the motherboard similarly. 本願発明の第２実施例のフリップチップＢＧＡ基板のシリコンチップをフリップチップした様子を示す説明図である。It is explanatory drawing which shows a mode that the silicon chip of the flip chip BGA board | substrate of 2nd Example of this invention was flip-chipped. 本願発明の第３実施例のフリップチップＢＧＡ基板のシリコンチップをフリップチップした様子を示す説明図である。It is explanatory drawing which shows a mode that the silicon chip of the flip chip BGA board | substrate of 3rd Example of this invention was flip-chipped. 従来技術のシリコンチップをフリップチップした様子を示す説明図である。It is explanatory drawing which shows a mode that the silicon chip of the prior art was flip-chipped. 従来技術のマザーボードに取り付けた様子を示す説明図である。It is explanatory drawing which shows a mode that it attached to the motherboard of a prior art. 従来技術の基板端部にスティフナを取り付けた様子を示す説明図である。It is explanatory drawing which shows a mode that the stiffener was attached to the board | substrate edge part of a prior art.

符号の説明Explanation of symbols

１１ シリコンチップ
１２ バンプ
１３ パッケージ基板
１４ ＢＧＡはんだボール
１５ アンダフィル材
１６ マザーボード
１８ 溝
１９ 溝
２１ 窪み部分 11 Silicon chip 12 Bump 13 Package substrate 14 BGA solder ball 15 Underfill material 16 Motherboard 18 Groove 19 Groove 21 Recessed portion

Claims (3)

フリップチップＢＧＡパッケージに用いられる基板において、
前記基板は、シリコンチップが実装される実装位置の裏面に相当する基板表面に、シリコンチップ外形と同じか、又は外側外周に沿って溝を形成したことを特徴とするフリップチップＢＧＡ基板。 In a substrate used for a flip chip BGA package,
The flip chip BGA substrate, wherein the substrate is formed on the substrate surface corresponding to the back surface of the mounting position on which the silicon chip is mounted, with a groove that is the same as the outer shape of the silicon chip or along the outer periphery. フリップチップＢＧＡパッケージに用いられる基板において、
前記基板は、シリコンチップが実装される実装位置と同じ基板表面に、シリコンチップ外形よりも外側外周に沿って溝を形成したことを特徴とするフリップチップＢＧＡ基板。 In a substrate used for a flip chip BGA package,
A flip-chip BGA substrate, wherein a groove is formed on the same substrate surface as the mounting position on which the silicon chip is mounted along the outer periphery outside the outer shape of the silicon chip. フリップチップＢＧＡパッケージに用いられる基板において、
前記基板は、シリコンチップが実装される実装位置の裏面に相当する基板表面に、シリコンチップ外形よりも大きく板厚を薄くした窪み部分を形成したことを特徴とするフリップチップＢＧＡ基板。 In a substrate used for a flip chip BGA package,
The flip-chip BGA substrate, wherein the substrate is formed with a recessed portion whose thickness is larger than the outer shape of the silicon chip on the substrate surface corresponding to the back surface of the mounting position where the silicon chip is mounted.
JP2007241112A 2007-09-18 2007-09-18 Flip chip bga substrate Pending JP2009071251A (en)

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