JP2011243624A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2011243624A
JP2011243624A JP2010112023A JP2010112023A JP2011243624A JP 2011243624 A JP2011243624 A JP 2011243624A JP 2010112023 A JP2010112023 A JP 2010112023A JP 2010112023 A JP2010112023 A JP 2010112023A JP 2011243624 A JP2011243624 A JP 2011243624A
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resin
semiconductor element
semiconductor device
circuit board
recess
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JP2011243624A5 (en
JP5877291B2 (en
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Kazumichi Shimizu
一路 清水
Masahiro Ono
正浩 小野
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a flip chip-mounted semiconductor device, which is reduced in the warp quantity and in which a semiconductor element is protected properly.SOLUTION: A semiconductor device manufacturing method includes: flip-chip connecting a semiconductor element 2 and a resin circuit board 4 through a bump electrode 3 formed on the semiconductor element 2; sealing a gap between the semiconductor element 2 and the resin circuit board 4 with a first resin 5; covering a face of the resin circuit board 4 with the semiconductor element 2 mounted thereon with a second resin 6 different from the first resin 5 in its entirety; providing a concavity 7 in part of the second resin 6 covering the semiconductor element 2; and putting, in the concavity 7, a third resin other than the first and second resins 5 and 6 or metal 8.

Description

本発明は、半導体チップが樹脂回路基板にフリップチップにて実装された半導体装置に係り、特に反りを低減する半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a resin circuit board by a flip chip, and more particularly to a semiconductor device that reduces warpage and a manufacturing method thereof.

電子回路基板はあらゆる製品に使用されるようになり、また、携帯機器の増加から半導体装置に対して小型化，軽量化が求められている。そのため現状では、ＢＧＡ（Ball Grid Array）やＣＳＰ（Chip Size Package）において、樹脂製の回路基板が用いられている。   Electronic circuit boards have come to be used in various products, and due to the increase in portable devices, miniaturization and weight reduction of semiconductor devices are required. Therefore, at present, resin circuit boards are used in BGA (Ball Grid Array) and CSP (Chip Size Package).

従来、半導体素子をフリップチップにより実装した後に、半導体素子を保護する目的ために、半導体素子を覆うようにして回路基板の上面を封止する場合がある。この封止を行うためには、金型を用いて射出成形する方法、あるいはディスペンサを用いて樹脂を塗布する方法が用いられている。   Conventionally, after a semiconductor element is mounted by flip chip, the upper surface of a circuit board is sometimes sealed so as to cover the semiconductor element in order to protect the semiconductor element. In order to perform this sealing, a method of injection molding using a mold or a method of applying a resin using a dispenser is used.

しかしながら、上記のように半導体素子を覆うように封止すると、封止された半導体装置は、常温で凹型に反り、高温時に凸型に反りを発生する。このような大きな反りを持つ半導体装置は、その半導体装置の厚みが厚くなることと同様になり、しかも半導体装置を別の基板に実装する際の接合不良につながる。   However, when the semiconductor element is sealed as described above, the sealed semiconductor device warps in a concave shape at room temperature and warps in a convex shape at high temperature. A semiconductor device having such a large warp is the same as an increase in the thickness of the semiconductor device, and leads to poor bonding when the semiconductor device is mounted on another substrate.

そこで、本件本出願人は、特願２００９−０１７４１３として、半導体装置において、フリップチップ接続された半導体素子を覆う樹脂に凹部を設けて、反り量をコントロールする技術に関する発明を出願した。この発明の構成について図７の半導体装置の断面図を参照して説明する。   Therefore, the present applicant has filed an invention relating to a technique for controlling the amount of warpage in a semiconductor device by providing a recess in a resin covering a flip-chip connected semiconductor element in Japanese Patent Application No. 2009-017413. A structure of the present invention will be described with reference to a cross-sectional view of the semiconductor device in FIG.

図７において、１は半導体装置、２は半導体素子、３は突起電極、４は樹脂回路基板、５は第１の樹脂、６は第２の樹脂、７は凹部を示す。   In FIG. 7, 1 is a semiconductor device, 2 is a semiconductor element, 3 is a protruding electrode, 4 is a resin circuit board, 5 is a first resin, 6 is a second resin, and 7 is a recess.

図７に示す半導体装置１において、樹脂回路基板４における半導体素子２が実装されている第１の面を、半導体素子２と樹脂回路基板４間に設けられる第１の樹脂５とは異なる第２の樹脂６により、半導体素子２と樹脂回路基板４とを含めて覆い、半導体素子２の裏面（図における上面）上の第２の樹脂６により覆われている部分に凹部７を設けている。   In the semiconductor device 1 shown in FIG. 7, the first surface of the resin circuit board 4 on which the semiconductor element 2 is mounted is different from the first resin 5 provided between the semiconductor element 2 and the resin circuit board 4. The resin 6 covers the semiconductor element 2 and the resin circuit board 4, and a recess 7 is provided in a portion covered with the second resin 6 on the back surface (upper surface in the drawing) of the semiconductor element 2.

前記構成によって、半導体素子２を保護しつつ、第２の樹脂６の熱収縮，熱膨張によって半導体装置１６の反りを低減し、凹部７の設置数，高，幅によって反り量をコントロールするようにしている。   With the above configuration, the warp of the semiconductor device 16 is reduced by the thermal contraction and thermal expansion of the second resin 6 while protecting the semiconductor element 2, and the warp amount is controlled by the number, height, and width of the recesses 7. ing.

また、前記反りに対応する他の技術として、半導体素子を覆う樹脂をさらに別の樹脂で覆うようにした構成の発明が提案されている（例えば、特許文献１参照）。この構成について図８を参照して説明する。   As another technique corresponding to the warp, an invention has been proposed in which a resin covering a semiconductor element is further covered with another resin (see, for example, Patent Document 1). This configuration will be described with reference to FIG.

図８（ａ）は半導体装置の断面図、図８（ｂ）は図８（ａ）の半導体装置の底面図であって、１は半導体装置、２は半導体素子、３は突起電極、４は樹脂回路基板、１８は第１の樹脂、１９は第２の樹脂、２０は第３の樹脂を示す。   8A is a cross-sectional view of the semiconductor device, FIG. 8B is a bottom view of the semiconductor device of FIG. 8A, 1 is the semiconductor device, 2 is the semiconductor element, 3 is the protruding electrode, 4 is A resin circuit board, 18 is a first resin, 19 is a second resin, and 20 is a third resin.

図８に示す半導体装置１において、半導体素子２はフリップチップ方法にて樹脂回路基板４に接合される。半導体素子２と樹脂回路基板４間には第１の樹脂１８が設けられ、その後、第１の樹脂１８とは異なる第２の樹脂１９により半導体素子２を覆い、第１の樹脂１８と第２の樹脂１９とは異なる第３の樹脂２０により第２の樹脂１９を覆う。さらに第３の樹脂２０は半導体素子２の辺の中央付近よりも角部に向けて長く配置される構成になっている。   In the semiconductor device 1 shown in FIG. 8, the semiconductor element 2 is bonded to the resin circuit board 4 by a flip chip method. A first resin 18 is provided between the semiconductor element 2 and the resin circuit board 4, and then the semiconductor element 2 is covered with a second resin 19 different from the first resin 18, and the first resin 18 and the second resin 18 The second resin 19 is covered with a third resin 20 different from the resin 19. Further, the third resin 20 is arranged longer toward the corner than the vicinity of the center of the side of the semiconductor element 2.

特開２００８−２７０４５４号公報JP 2008-270454 A

しかしながら、本件出願人による特願２００９−０１７４１３の発明では、半導体素子２を覆う第２の樹脂６に凹部７を設けると、半導体装置１の反り量は低減するものの、半導体素子２を保護する目的の第２の樹脂６が少なくなることにより、半導体装置１自体の強度が低下する。また、凹部７の溝の幅，深さによっては、半導体装置１の曲げに対して応力が凹部７の溝に集中し、半導体装置１の強度不足あるいはフリップチップ接合部の接合不良が発生するという課題を有する。   However, in the invention of Japanese Patent Application No. 2009-017413 by the present applicant, if the recess 7 is provided in the second resin 6 covering the semiconductor element 2, the amount of warpage of the semiconductor device 1 is reduced, but the semiconductor element 2 is protected. As the second resin 6 decreases, the strength of the semiconductor device 1 itself decreases. Further, depending on the width and depth of the groove of the recess 7, stress concentrates on the groove of the recess 7 with respect to the bending of the semiconductor device 1, and the semiconductor device 1 has insufficient strength or a defective bonding of the flip chip joint. Has a problem.

また、特許文献１に記載の発明では、半導体素子２を覆う第２の樹脂６とは異なる第３の樹脂８を、半導体素子２を覆う第２の樹脂６を覆うように設ける。このため樹脂をディスペンスにより塗布すると、塗布される樹脂量，樹脂の濡れ性を精密にコントロールすることが困難である。このため、塗布された第３の樹脂８の高さや幅の形状が不安定になり、結果として、半導体装置１の反り量にばらつきが発生するという課題を有していた。   In the invention described in Patent Document 1, a third resin 8 different from the second resin 6 covering the semiconductor element 2 is provided so as to cover the second resin 6 covering the semiconductor element 2. For this reason, when the resin is applied by dispensing, it is difficult to precisely control the amount of resin applied and the wettability of the resin. For this reason, the shape of the height and width of the applied third resin 8 becomes unstable, and as a result, the amount of warpage of the semiconductor device 1 varies.

本発明は、前記従来の課題を解決するものであり、半導体装置の強度低下を防ぐことにより保護を図ることができ、しかも反りをコントロールしながら反りの低減化を図ることができる半導体装置およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and can provide protection by preventing a reduction in the strength of the semiconductor device, and can reduce warpage while controlling warpage, and its semiconductor device An object is to provide a manufacturing method.

上記課題を解決するため、本発明に係る半導体装置は、突起電極が形成された半導体素子と、前記半導体素子が前記突起電極を介して実装された回路基板と、前記半導体素子と前記回路基板間の隙間を封止する第１の樹脂と、前記半導体素子の実装面と対向する上面を覆い、かつ前記半導体素子の上部に凹部が形成される第２の樹脂とを備え、第３の樹脂または金属が前記凹部に設けられることを特徴とする。   In order to solve the above problems, a semiconductor device according to the present invention includes a semiconductor element on which a protruding electrode is formed, a circuit board on which the semiconductor element is mounted via the protruding electrode, and between the semiconductor element and the circuit board. A first resin that seals the gap between the semiconductor element and a second resin that covers an upper surface that faces the mounting surface of the semiconductor element and that has a recess formed in the upper part of the semiconductor element. A metal is provided in the recess.

また、前記凹部の高さが、前記第２の樹脂で覆われる部分より低く、かつ前記半導体素子の裏面より高いことを特徴とする。   Further, the height of the concave portion is lower than the portion covered with the second resin and higher than the back surface of the semiconductor element.

また、前記凹部が少なくとも１本の直線状の溝によって形成され、前記直線状の溝の幅が前記半導体素子の短辺の幅より小さいことを特徴とする。   The concave portion is formed by at least one linear groove, and the width of the linear groove is smaller than the width of the short side of the semiconductor element.

また、複数本の前記溝が、前記半導体素子の中心上で交差することを特徴とする。   The plurality of grooves intersect with each other on the center of the semiconductor element.

また、前記第２の樹脂の熱膨張係数が、前記回路基板の熱膨張係数よりも大きく、かつ前記第１の樹脂の熱膨張係数より小さく、前記第３の樹脂または金属の熱膨張係数が前記第２の樹脂の熱膨張係数よりも小さいことを特徴とする。   The thermal expansion coefficient of the second resin is larger than the thermal expansion coefficient of the circuit board and smaller than the thermal expansion coefficient of the first resin, and the thermal expansion coefficient of the third resin or metal is It is smaller than the thermal expansion coefficient of the second resin.

また、前記第２の樹脂のガラス転移温度が前記回路基板のガラス転移温度よりも低く、前記第３の樹脂または金属のガラス転移温度が前記第２の樹脂のガラス転移温度よりも低いことを特徴とする。   The glass transition temperature of the second resin is lower than the glass transition temperature of the circuit board, and the glass transition temperature of the third resin or metal is lower than the glass transition temperature of the second resin. And

さらに、本発明に係る半導体装置の製造方法は、基板の一主面に第１の樹脂を塗布する工程と、前記第１の樹脂を介して前記回路基板の一主面上に複数の半導体素子を実装する工程と、実装した前記複数の半導体素子を前記第２の樹脂で封止する工程と、前記第２の樹脂における前記半導体素子の上部に凹部を形成する工程と、前記凹部に第３の樹脂または金属を塗布する工程と、前記半導体素子が少なくとも１個含まれるように前記基板を分割して、それぞれを半導体装置とする工程とを有することを特徴とする。   Furthermore, the method for manufacturing a semiconductor device according to the present invention includes a step of applying a first resin to one principal surface of a substrate, and a plurality of semiconductor elements on the one principal surface of the circuit substrate via the first resin. A step of sealing the plurality of mounted semiconductor elements with the second resin, a step of forming a recess in the upper portion of the semiconductor element in the second resin, and a third step in the recess. A step of applying the resin or metal, and a step of dividing the substrate so that at least one of the semiconductor elements is included, thereby forming each of the semiconductor devices.

本発明によれば、半導体装置の強度低下を防ぎながら半導体素子を保護しつつ、半導体装置の反り量を安定してコントロールすることができ、半導体装置を別の基板に実装する際の接合不良を低減することができる。   According to the present invention, it is possible to stably control the amount of warpage of a semiconductor device while protecting the semiconductor element while preventing the strength reduction of the semiconductor device, and to prevent a bonding failure when the semiconductor device is mounted on another substrate. Can be reduced.

図１（ａ）は本発明の実施の形態１における半導体装置の斜視図、図１（ｂ）は図１（ａ）におけるＡ−Ａ’断面図、図１（ｃ）は実施の形態１の変形例の図１（ａ）におけるＡ−Ａ’断面図1A is a perspective view of the semiconductor device according to the first embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line AA ′ in FIG. 1A, and FIG. AA ′ cross-sectional view in FIG. 本発明の実施の形態１における半導体装置の各部の高さを説明するための断面図Sectional drawing for demonstrating the height of each part of the semiconductor device in Embodiment 1 of this invention 図３（ａ）は本発明の実施の形態２における半導体装置の斜視図、図３（ｂ）は図３（ａ）におけるＡ−Ａ’断面図3A is a perspective view of the semiconductor device according to the second embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the line A-A ′ in FIG. 図４（ａ）は本発明の実施の形態３における半導体装置の斜視図、図４（ｂ）は図４（ａ）におけるＡ−Ａ’断面図4A is a perspective view of the semiconductor device according to the third embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along the line A-A ′ in FIG. 本発明の実施の形態における製造工程に係るフローチャートThe flowchart which concerns on the manufacturing process in embodiment of this invention 本発明の実施の形態における各製造工程の半導体装置の状態を示す斜視図The perspective view which shows the state of the semiconductor device of each manufacturing process in embodiment of this invention 従来の半導体装置の一例の断面図Sectional view of an example of a conventional semiconductor device 図８（ａ）は従来の半導体装置の断面図、図８（ｂ）は図８（ａ）の半導体装置の平面図8A is a cross-sectional view of a conventional semiconductor device, and FIG. 8B is a plan view of the semiconductor device of FIG.

以下、本発明の実施の形態について、図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は本発明の実施の形態１における半導体装置の構成図であって、図１（ａ）は本発明の実施の形態１における半導体装置の構成を示す斜視図である。図１（ｂ）と図１（ｃ）は図１（ａ）のＡ−Ａ’線断面図であって、図１（ｂ）にはＡ−Ａ’線上における半導体素子裏面が露出しない状態において他の樹脂で覆う場合の構成例を示す。図１（ｃ）にはＡ−Ａ’線上における半導体素子裏面が露出する状態において他の樹脂で覆う場合の構成例を示す。   FIG. 1 is a configuration diagram of the semiconductor device according to the first embodiment of the present invention, and FIG. 1A is a perspective view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIGS. 1B and 1C are cross-sectional views taken along line AA ′ of FIG. 1A. FIG. 1B shows a state in which the back surface of the semiconductor element on the line AA ′ is not exposed. The structural example in the case of covering with other resin is shown. FIG. 1C shows a configuration example in the case where the back surface of the semiconductor element on the A-A ′ line is exposed with another resin.

図１において、１は半導体装置、２は半導体素子、３は突起電極、４は樹脂回路基板、５は第１の樹脂、６は第２の樹脂、７は凹部、８は第３の樹脂（または金属）を示す。   In FIG. 1, 1 is a semiconductor device, 2 is a semiconductor element, 3 is a protruding electrode, 4 is a resin circuit board, 5 is a first resin, 6 is a second resin, 7 is a recess, and 8 is a third resin ( Or metal).

図１に示す半導体装置１において、半導体素子２は、その電極上に突起電極３を形成し、樹脂回路基板４の基板電極にフリップチップにて接合されている。半導体素子２と樹脂回路基板４間には第１の樹脂５を設け、この第１の樹脂５によって半導体素子２と樹脂回路基板４との接合を維持している。   In the semiconductor device 1 shown in FIG. 1, the semiconductor element 2 has a protruding electrode 3 formed on the electrode, and is bonded to the substrate electrode of the resin circuit substrate 4 by flip chip. A first resin 5 is provided between the semiconductor element 2 and the resin circuit board 4, and the bonding between the semiconductor element 2 and the resin circuit board 4 is maintained by the first resin 5.

第１樹脂５は、本例では熱硬化性エポキシ樹脂であり、その使用形態としてはフィルム状でも液状の樹脂でもよい。ただし、第１樹脂５がフィルム状の樹脂の場合には、フリップチップ実装する前に樹脂回路基板４に貼り付けられ、熱圧着することにより半導体素子２と樹脂回路基板４間に充填されるようにする。第１樹脂５が液状の場合には、フリップチップ実装する前に樹脂回路基板４に塗布して熱圧着しても、また、フリップチップ実装した後に半導体素子２の側面から流し込み熱硬化させてもよい。第１の樹脂５は、熱圧着により熱硬化して収縮することによって、半導体素子２と樹脂回路基板４との接合を維持させる。   The first resin 5 is a thermosetting epoxy resin in this example, and may be used in the form of a film or a liquid. However, when the first resin 5 is a film-like resin, the first resin 5 is affixed to the resin circuit board 4 before flip chip mounting, and is filled between the semiconductor element 2 and the resin circuit board 4 by thermocompression bonding. To. When the first resin 5 is in a liquid state, it may be applied to the resin circuit board 4 and thermocompression bonded before flip chip mounting, or may be poured from the side surface of the semiconductor element 2 and thermally cured after flip chip mounting. Good. The first resin 5 maintains the bonding between the semiconductor element 2 and the resin circuit board 4 by thermosetting and shrinking by thermocompression bonding.

さらに、半導体素子２を覆うように、樹脂回路基板４における半導体素子２が搭載される面を熱硬化性エポキシ樹脂からなる第２の樹脂６で封止し、半導体素子２の裏面（図では上面部）上の第２の樹脂６に凹部７を形成する。第２の樹脂６は、金型を用いて射出成形することにより成形する一般的なトランスファーモールド手法を用いて形成することが可能であって、熱硬化する。   Further, the surface of the resin circuit board 4 on which the semiconductor element 2 is mounted is sealed with a second resin 6 made of a thermosetting epoxy resin so as to cover the semiconductor element 2, and the back surface of the semiconductor element 2 (upper surface in the figure). The concave portion 7 is formed in the second resin 6 on the upper portion. The second resin 6 can be formed using a general transfer molding method in which the second resin 6 is molded by injection molding using a mold, and is cured by heat.

凹部７は、図１（ｂ）に示すように、半導体素子２の裏面を露出させないように形成しても、図１（ｃ）に示すように、半導体素子２の裏面を露出させるように形成してもよい。   As shown in FIG. 1B, the recess 7 is formed so as to expose the back surface of the semiconductor element 2 as shown in FIG. 1C, even if it is formed so as not to expose the back surface of the semiconductor element 2. May be.

凹部７は、樹脂回路基板４を分割する際に用いられるダイシング装置を用いて形成することができるため、ダイシングの刃の幅と、ダイシング回数や切り込み深さとにより、凹部７の数，高さ，幅を容易にコントロールして形成することが可能である。   Since the recesses 7 can be formed by using a dicing apparatus used when the resin circuit board 4 is divided, the number, the height, and the number of the recesses 7 depends on the width of the dicing blade, the number of dicings, and the cutting depth. The width can be easily controlled and formed.

具体的には、１０ミリメートル角の半導体素子２を、１５ミリメートル角の樹脂回路基板４の中心に実装し、第２の樹脂６をトランスファーモールドして、凹部７を、半導体素子２の中心で交わるように、ダイシング装置を用いて８ミリメートルの幅、かつ５００マイクロメートルの高さで形成した。   Specifically, the 10 mm square semiconductor element 2 is mounted on the center of the 15 mm square resin circuit board 4, the second resin 6 is transfer molded, and the recess 7 intersects with the center of the semiconductor element 2. As described above, a dicing apparatus was used to form a width of 8 millimeters and a height of 500 micrometers.

そして本実施の形態では、凹部７に熱硬化性エポキシ樹脂である第３の樹脂８を用いてディスペンスし、第２の樹脂６を４３パーセント、当該第３の樹脂８に置き換えた。第３の樹脂８の熱膨張係数を１３ｐｐｍとして、第２の樹脂６の熱膨張係数２５ｐｐｍよりも小さいものとした。なお、第３の樹脂８の弾性率は１８ＧＰａ、第２の樹脂６の弾性率は８ＧＰａとした。第３の樹脂８の熱膨張係数を第２の樹脂６の熱膨張係数よりも小さくするために、第３の樹脂８の弾性率が第２の樹脂６の弾性率よりも大きくなっているが、弾性率の増加ができるだけ少なくなる樹脂を選択した。熱硬化性エポキシ樹脂である第２の樹脂６と第３の樹脂８には、主剤に加えて硬化剤と無機充填剤が含まれる。硬化剤については、フェノール系の硬化剤を一例として用いた。   In this embodiment, the concave portion 7 is dispensed with the third resin 8 which is a thermosetting epoxy resin, and the second resin 6 is replaced with the third resin 8 by 43 percent. The thermal expansion coefficient of the third resin 8 was 13 ppm, and the thermal expansion coefficient of the second resin 6 was smaller than 25 ppm. The elastic modulus of the third resin 8 was 18 GPa, and the elastic modulus of the second resin 6 was 8 GPa. In order to make the thermal expansion coefficient of the third resin 8 smaller than the thermal expansion coefficient of the second resin 6, the elastic modulus of the third resin 8 is larger than the elastic modulus of the second resin 6. A resin was selected that would minimize the increase in elastic modulus. The second resin 6 and the third resin 8 that are thermosetting epoxy resins contain a curing agent and an inorganic filler in addition to the main agent. For the curing agent, a phenolic curing agent was used as an example.

この結果、３０℃から２４０℃までの加熱環境下において、半導体装置１の反り量が低減することを観察した。   As a result, it was observed that the amount of warpage of the semiconductor device 1 was reduced in a heating environment from 30 ° C. to 240 ° C.

ここで、加熱環境下では、凹部７および第３の樹脂８を形成しない半導体装置の場合には、第２の樹脂６の熱膨張によって凸型に反りを発生する。しかし、本実施の形態では、凹部７および第３の樹脂８を形成し、第３の樹脂８の熱膨張係数を第２の樹脂６の熱膨張係数より小さい樹脂を用いたことにより、加熱環境下の凹部７の第２の樹脂６と第３の樹脂８との界面において、第２の樹脂６には収縮する方向に力が作用する。よって、その結果、加熱環境下の半導体装置１の凸型の反りは低減した。   Here, in a heating environment, in the case of a semiconductor device in which the concave portion 7 and the third resin 8 are not formed, the convex shape warps due to the thermal expansion of the second resin 6. However, in the present embodiment, the recess 7 and the third resin 8 are formed, and the thermal expansion coefficient of the third resin 8 is smaller than that of the second resin 6, so that the heating environment At the interface between the second resin 6 and the third resin 8 in the lower recess 7, a force acts on the second resin 6 in a contracting direction. Therefore, as a result, the convex warpage of the semiconductor device 1 under the heating environment is reduced.

また、室温においては、凹部７および第３の樹脂８を形成しない半導体装置の場合には、第２の樹脂６の熱収縮によって凹型に反りを発生する。しかし、本実施の形態では、第３の樹脂８の熱膨張係数が第２の樹脂６の熱膨張係数よりも小さいために、第３の樹脂８の硬化温度から冷却される過程において、第２の樹脂６の収縮の方が第３の樹脂８よりも大きく、凹部７の第２の樹脂６と第３の樹脂８の界面において、第２の樹脂６は膨張する方向に力が作用する。よって、その結果、室温での半導体装置１における凹型の反りは低減した。   Further, at room temperature, in the case of a semiconductor device in which the concave portion 7 and the third resin 8 are not formed, the concave shape warps due to the thermal contraction of the second resin 6. However, in the present embodiment, since the thermal expansion coefficient of the third resin 8 is smaller than the thermal expansion coefficient of the second resin 6, in the process of cooling from the curing temperature of the third resin 8, The contraction of the resin 6 is larger than that of the third resin 8, and a force acts in the direction in which the second resin 6 expands at the interface between the second resin 6 and the third resin 8 in the recess 7. As a result, the concave warpage of the semiconductor device 1 at room temperature is reduced.

半導体素子２の大きさ，厚み、あるいは樹脂回路基板４の大きさ，厚みが変化すれば、半導体装置１の反り量は異なる。本実施の形態では、第２の樹脂６を第３の樹脂（または金属）８に置き換える割合を、凹部７の数，高さ，幅によって自由に変化させることが可能であり、このため半導体装置１の反り量の低減化が可能である。   If the size and thickness of the semiconductor element 2 or the size and thickness of the resin circuit board 4 are changed, the warpage amount of the semiconductor device 1 is different. In the present embodiment, the ratio of replacing the second resin 6 with the third resin (or metal) 8 can be freely changed depending on the number, height, and width of the recesses 7, and thus the semiconductor device. The amount of warpage 1 can be reduced.

なお、第３の樹脂（または金属）８として、樹脂を使用する場合には熱硬化性エポキシ樹脂が望ましく、金属を使用する場合にはステンレス（ＳＵＳ）が望ましい。   As the third resin (or metal) 8, a thermosetting epoxy resin is desirable when using a resin, and stainless steel (SUS) is desirable when using a metal.

通常、半導体素子２を、第１樹脂５を用いて樹脂回路基板４にフリップチップ実装し、第２の樹脂６を設けない場合、半導体素子２と樹脂回路基板４と第１の樹脂５との各熱膨張係数の差より、半導体装置１は、常温では凸型に、また高温時には凹型に反りを発生する。   Usually, when the semiconductor element 2 is flip-chip mounted on the resin circuit board 4 using the first resin 5 and the second resin 6 is not provided, the semiconductor element 2, the resin circuit board 4, and the first resin 5 Due to the difference in coefficient of thermal expansion, the semiconductor device 1 warps in a convex shape at room temperature and in a concave shape at high temperature.

一方、半導体素子２を保護するために第２の樹脂６を設けることにより、半導体装置は、第２の樹脂６が常温では収縮して凹型に、また高温では膨張して凸型に反りを発生するようになる。   On the other hand, by providing the second resin 6 to protect the semiconductor element 2, the semiconductor device causes the second resin 6 to shrink into a concave shape at room temperature and expand at a high temperature to generate a convex warp. Will come to do.

ここで、例えば第３の樹脂（または金属）８の熱膨張係数を第２の樹脂６の熱膨張係数より小さくすると、樹脂回路基板４上では半導体素子２を覆う部分の熱膨張係数が見かけ上、小さくなる。このため常温における収縮および高温における膨張が抑えられ、反り量が常温時、高温時ともに低減する。   Here, for example, if the thermal expansion coefficient of the third resin (or metal) 8 is made smaller than the thermal expansion coefficient of the second resin 6, the thermal expansion coefficient of the portion covering the semiconductor element 2 on the resin circuit board 4 is apparent. , Get smaller. For this reason, shrinkage at normal temperature and expansion at high temperature are suppressed, and the amount of warpage is reduced both at normal temperature and at high temperature.

凹部７および第３の樹脂（または金属）８を設けない場合、反り量を低減するためには第２の樹脂６に求められる熱膨張係数は１〜１０ｐｐｍ程度になり、第２の樹脂６の粘度が高くなる。このため、金型を用いて射出成形する一般的なトランスファーモールド手法を用いて第２の樹脂６を形成することが困難になる。   When the concave portion 7 and the third resin (or metal) 8 are not provided, the thermal expansion coefficient required for the second resin 6 is about 1 to 10 ppm in order to reduce the amount of warpage. Viscosity increases. For this reason, it becomes difficult to form the second resin 6 using a general transfer mold method in which injection molding is performed using a mold.

また、凹部７に第３の樹脂（または金属）８を設けない場合、凹部７において半導体装置１の曲げに対し応力を集中させることになる。このため本実施の形態のように、半導体装置１の凹部７に第３の樹脂（または金属）８を設けることにより応力集中を回避することができ、半導体装置１の強度が向上する。   Further, when the third resin (or metal) 8 is not provided in the recess 7, stress is concentrated on the bending of the semiconductor device 1 in the recess 7. Therefore, stress concentration can be avoided by providing the third resin (or metal) 8 in the recess 7 of the semiconductor device 1 as in the present embodiment, and the strength of the semiconductor device 1 is improved.

さらに、半導体素子２は駆動時に発熱するため、凹部７に第３の樹脂（または金属）８を設けることにより、半導体装置１の上面における選択された部位から放熱する作用を期待することができる。なお、凹部７に配置する第３の樹脂（または金属）８を、樹脂にすることにより、これを凹部７の形状に沿って容易に設けることが可能になる。   Furthermore, since the semiconductor element 2 generates heat during driving, it is possible to expect an effect of radiating heat from a selected portion on the upper surface of the semiconductor device 1 by providing the third resin (or metal) 8 in the recess 7. In addition, when the third resin (or metal) 8 disposed in the recess 7 is made of resin, it can be easily provided along the shape of the recess 7.

また、第２の樹脂６に凹部７を形成して第３の樹脂（または金属）８を設けるために、半導体装置１の厚みを厚くする必要がなく、半導体装置１の低背化が可能である。   In addition, since the concave portion 7 is formed in the second resin 6 and the third resin (or metal) 8 is provided, it is not necessary to increase the thickness of the semiconductor device 1, and the semiconductor device 1 can be reduced in height. is there.

本実施の形態１において、図２に示すように、凹部７の高さＴ１は、０ｍｍ以上かつ半導体素子２の裏面から第２の樹脂６の高さＴ２よりも低く形成し、半導体素子２の裏面を露出しない凹部７を形成する。半導体素子２の裏面を露出させないことにより、凹部７を形成して該凹部７に第３の樹脂（または金属）８を配置するまでの工程間において、半導体素子２を保護することが可能である。無論、既述したように、半導体装置１の放熱作用の効果も期待できる。   In the first embodiment, as shown in FIG. 2, the height T 1 of the recess 7 is 0 mm or more and lower than the height T 2 of the second resin 6 from the back surface of the semiconductor element 2. A recess 7 that does not expose the back surface is formed. By not exposing the back surface of the semiconductor element 2, it is possible to protect the semiconductor element 2 during the process from the formation of the recess 7 to the placement of the third resin (or metal) 8 in the recess 7. . Of course, as described above, the effect of the heat dissipation action of the semiconductor device 1 can also be expected.

図３は本発明の実施の形態２における半導体装置の構成図であって、図３（ａ）は本発明の実施の形態２における半導体装置の構成を示す斜視図であり、図３（ｂ）は図３（ａ）のＡ−Ａ’線断面図である。なお、以下の説明において、図１の実施の形態１にて説明した構成要素と同じ構成要素については同じ符号を用い、詳しい説明を省略する。   FIG. 3 is a configuration diagram of the semiconductor device according to the second embodiment of the present invention, and FIG. 3A is a perspective view showing the configuration of the semiconductor device according to the second embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view taken along line AA ′ of FIG. In the following description, the same components as those described in Embodiment 1 in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

半導体素子２の裏面の上に設けられている第２樹脂６の凹部７の形成としては各種の構造が考えられる。実施の形態２では、半導体素子２の裏面の上に設けられている第２樹脂６の凹部７は、一方向にのみ延在する１本の直線状をなす溝からなるものであって、実施の形態１と同様に、凹部７に第３の樹脂（または金属）８が設けられている。   Various structures are conceivable for forming the recesses 7 of the second resin 6 provided on the back surface of the semiconductor element 2. In the second embodiment, the concave portion 7 of the second resin 6 provided on the back surface of the semiconductor element 2 is composed of a single linear groove extending only in one direction. Similar to the first embodiment, a third resin (or metal) 8 is provided in the recess 7.

このように、半導体装置１の樹脂回路基板４の配線パターンや残銅率による反りの方向、当該半導体装置１が実装される他の基板の反り量を考慮して、半導体装置１の反りの方向性と反り量とをコントロールするために、凹部７を少なくても１本の直線的な溝として形成し、凹部７に第３の樹脂（または金属）８を配置する。   Thus, in consideration of the direction of warping due to the wiring pattern of the resin circuit board 4 of the semiconductor device 1 and the remaining copper ratio and the amount of warping of the other substrate on which the semiconductor device 1 is mounted, the direction of warping of the semiconductor device 1. In order to control the property and the amount of warpage, the recess 7 is formed as at least one linear groove, and a third resin (or metal) 8 is disposed in the recess 7.

方向性のある反り低減をする場合、反りを低減したい方向と平行する方向に凹部７の溝を形成し、第３の樹脂（または金属）８を設けるようにする。   When reducing warping with directionality, the groove of the recess 7 is formed in a direction parallel to the direction in which the warping is desired to be reduced, and the third resin (or metal) 8 is provided.

また、凹部７の溝の幅は、大きくても半導体素子２の短辺の長さ以下とする。反りを低減するためには、凹部７の有無にかかわらず、半導体素子２の裏面上に第２の樹脂６が配置されていることが必要である。   In addition, the width of the groove of the concave portion 7 is not more than the length of the short side of the semiconductor element 2 at most. In order to reduce the warpage, it is necessary that the second resin 6 be disposed on the back surface of the semiconductor element 2 regardless of the presence or absence of the recess 7.

無論、凹部７溝の幅を制御することにより、２本以上、例えば４本，８本でもよく、その場合、各凹部７の溝内に第３の樹脂（または金属）８を配置する。凹部７の溝の本数を増やすことによって、半導体装置１内の小さい領域ごとに反り量を低減することができ、半導体装置１全体の反り量を低減することが可能になる。   Of course, by controlling the width of the recess 7 groove, two or more, for example, 4 or 8, may be used. In this case, the third resin (or metal) 8 is disposed in the groove of each recess 7. By increasing the number of grooves in the recess 7, the warpage amount can be reduced for each small region in the semiconductor device 1, and the warpage amount of the entire semiconductor device 1 can be reduced.

前記実施の形態１では、図１に示すように、半導体装置１に設けられる凹部７の溝を２本以上（図１では２本を示す）とし、各溝が半導体素子２の中心を通り、半導体素子２の各辺に対して鉛直方向、かつ互いに直交する方向に延在するようにしている。   In the first embodiment, as shown in FIG. 1, the groove of the recess 7 provided in the semiconductor device 1 is two or more (two are shown in FIG. 1), and each groove passes through the center of the semiconductor element 2. Each side of the semiconductor element 2 extends in a vertical direction and in a direction orthogonal to each other.

図４は本発明の実施の形態３における半導体装置の構成図であって、図４（ａ）は本発明の実施の形態３における半導体装置の構成を示す斜視図であり、図４（ｂ）は図４（ａ）のＡ−Ａ’線断面図である。   FIG. 4 is a configuration diagram of the semiconductor device according to the third embodiment of the present invention, and FIG. 4A is a perspective view showing the configuration of the semiconductor device according to the third embodiment of the present invention, and FIG. FIG. 5 is a cross-sectional view taken along line AA ′ of FIG.

実施の形態３では、図４に示すように、半導体装置１に設けられる凹部７の溝を２本以上（図４では２本を示す）とし、各溝が半導体素子２の中心、および半導体素子２の略各角部を通り、かつ互いに直交する方向に延在するようにしている。   In the third embodiment, as shown in FIG. 4, the recess 7 provided in the semiconductor device 1 has two or more grooves (two are shown in FIG. 4), each groove being the center of the semiconductor element 2 and the semiconductor element. 2 extends substantially in the direction perpendicular to each other.

通常、半導体装置１の反りは、凹部７を形成せずに第２の樹脂６のみの場合、半導体素子２の中心が最も高い凸型、あるいは半導体素子２の中心が最も低い凹型の形状に発生する。   In general, the warp of the semiconductor device 1 occurs in a convex shape having the highest center of the semiconductor element 2 or a concave shape having the lowest center of the semiconductor element 2 when only the second resin 6 is formed without forming the concave portion 7. To do.

そのために、上記した実施の形態のように複数本の凹部７の溝を形成し、該凹部７内に第３の樹脂（または金属）８を設ける構成の場合、複数本の溝は、半導体素子２の中心を通って互いに直交する構造にすることが望ましい。既述したように、凹部７の溝幅を制御することにより、複数本の凹部７の溝を形成してもよく、その場合、各凹部７の溝に第３の樹脂（または金属）８を設けるようにする。凹部７の溝の本数を増やすことにより、半導体装置１内の小さい領域ごとに反り量を低減することができ、半導体装置１全体の反り量を低減することが可能になる。   Therefore, in the case of the structure in which the grooves of the plurality of recesses 7 are formed and the third resin (or metal) 8 is provided in the recesses 7 as in the above-described embodiment, the plurality of grooves It is desirable to make the structure perpendicular to each other through the center of the two. As described above, by controlling the groove width of the recess 7, a plurality of grooves of the recess 7 may be formed. In that case, the third resin (or metal) 8 is put in the groove of each recess 7. Make it. By increasing the number of grooves in the recess 7, the warpage amount can be reduced for each small region in the semiconductor device 1, and the warpage amount of the entire semiconductor device 1 can be reduced.

なお、本実施の形態において、第２の樹脂６の熱膨張係数は、樹脂回路基板４の熱膨張係数よりも大きく、かつ第１の樹脂５の熱膨張係数より小さいものとし、さらに第３の樹脂（または金属）８が樹脂の場合、第３の樹脂８の熱膨張係数が第２の樹脂６の熱膨張係数よりも小さいものとする。通常、第１の樹脂５は熱硬化性のエポキシ樹脂と、熱膨張係数を下げるために３０〜６０重量％の無機質充填材料を含み、３０〜５０ｐｐｍの熱膨張係数を有している。   In the present embodiment, the thermal expansion coefficient of the second resin 6 is larger than the thermal expansion coefficient of the resin circuit board 4 and smaller than the thermal expansion coefficient of the first resin 5. When the resin (or metal) 8 is a resin, it is assumed that the thermal expansion coefficient of the third resin 8 is smaller than the thermal expansion coefficient of the second resin 6. In general, the first resin 5 includes a thermosetting epoxy resin and 30 to 60% by weight of an inorganic filler in order to lower the thermal expansion coefficient, and has a thermal expansion coefficient of 30 to 50 ppm.

また、樹脂回路基板４は、通常、ガラス繊維などが編みこまれていることから、９〜２０ｐｐｍの熱膨張係数を有している。第２の樹脂６は、反りを低減効果を発揮させるために、樹脂回路基板４の熱膨張係数より大きくする必要がある。   The resin circuit board 4 has a thermal expansion coefficient of 9 to 20 ppm because glass fibers are usually woven. The second resin 6 needs to be larger than the thermal expansion coefficient of the resin circuit board 4 in order to exhibit the effect of reducing warpage.

さらに、凹部７を設けずに第２の樹脂のみで半導体素子２を覆う場合よりも反りを低減するためには、第３の樹脂（または金属）８は第２の樹脂６よりも熱膨張係数を小さくする必要がある。   Furthermore, the third resin (or metal) 8 has a thermal expansion coefficient higher than that of the second resin 6 in order to reduce the warpage as compared with the case where the semiconductor element 2 is covered only with the second resin without providing the recess 7. Need to be small.

半導体素子２と樹脂回路基板４との接合は、第１の樹脂５で維持されていることから、第２の樹脂６の熱膨張係数は、第１の樹脂５の熱膨張係数よりも小さい必要がある。第１の樹脂５より熱膨張係数が大きい第２の樹脂６を用いると、第１の樹脂５の熱膨張に加えて、さらに第２の樹脂６の熱膨張により、接合部に存在する突起電極３に加わる応力は大きくなり、温度サイクルなどの負荷が半導体装置１に加わった場合、接合を維持することができなくなる。   Since the bonding between the semiconductor element 2 and the resin circuit board 4 is maintained by the first resin 5, the thermal expansion coefficient of the second resin 6 needs to be smaller than the thermal expansion coefficient of the first resin 5. There is. When the second resin 6 having a thermal expansion coefficient larger than that of the first resin 5 is used, in addition to the thermal expansion of the first resin 5, the protruding electrode existing at the joint portion is further expanded by the thermal expansion of the second resin 6. The stress applied to 3 increases, and when a load such as a temperature cycle is applied to the semiconductor device 1, the bonding cannot be maintained.

このため、樹脂回路基板４と第１の樹脂５との組み合わせにもよるが、第２の樹脂６の熱膨張係数は２０〜４５ｐｐｍ、第３の樹脂（または金属）８は１〜４０ｐｐｍ程度であり、熱膨張係数は第３の樹脂（または金属）＜第２の樹脂＜第１の樹脂とすることが望ましい。第３の樹脂（または金属）８は、必ずしも樹脂回路基板４の熱膨張係数より大きい必要はない。   Therefore, although depending on the combination of the resin circuit board 4 and the first resin 5, the thermal expansion coefficient of the second resin 6 is 20 to 45 ppm, and the third resin (or metal) 8 is about 1 to 40 ppm. The coefficient of thermal expansion is desirably the third resin (or metal) <the second resin <the first resin. The third resin (or metal) 8 is not necessarily larger than the thermal expansion coefficient of the resin circuit board 4.

また、金型を用いて射出成形する一般的なトランスファーモールド法では、金型が高価であるために、半導体装置１の半導体素子２のサイズや厚み、あるいは樹脂回路基板４の配線パターンや厚みなどを変更した場合に、同様の反り低減効果を得るために第２の樹脂６の厚みを変更することはコストがかかる。   Further, in a general transfer mold method in which injection molding is performed using a mold, the mold is expensive, and therefore the size and thickness of the semiconductor element 2 of the semiconductor device 1 or the wiring pattern and thickness of the resin circuit board 4 are used. If the thickness of the second resin 6 is changed in order to obtain the same warp reduction effect, it is costly.

また、ディスペンス法などにより第２の樹脂６を設ける方法は、第２の樹脂６の厚みのばらつきが大きく、その結果、半導体装置１の反り量がばらつくことになる。そこで、第２の樹脂６の熱膨張係数を樹脂回路基板４の熱膨張係数以上、かつ第１の樹脂５の熱膨張係数以下にし、さらに凹部７を設けることによって定量的に反りをコントロールすることが必要になる。   In addition, in the method of providing the second resin 6 by the dispensing method or the like, the thickness of the second resin 6 varies greatly, and as a result, the warpage amount of the semiconductor device 1 varies. Therefore, the warpage is quantitatively controlled by setting the thermal expansion coefficient of the second resin 6 to be equal to or higher than the thermal expansion coefficient of the resin circuit board 4 and lower than the thermal expansion coefficient of the first resin 5 and further providing the recess 7. Is required.

凹部７の寸法は、具体的な一例として、１０ミリメートル角の半導体素子２を実装している場合、凹部７を２本の直線状の溝とすると、８ミリメートル程度の幅、５０マイクロメートル程度の高さで形成すればよい。その後、第３の樹脂（または金属）８が樹脂の場合、第３の樹脂８を設ける際に凹部７が所定の寸法に加工されているために、ディスペンスなどで第３の樹脂８を配置しても、反りのばらつきは大きくない。   As a specific example, when the semiconductor element 2 of 10 mm square is mounted, the dimension of the concave portion 7 is about 8 mm wide and about 50 micrometers when the concave portion 7 is two linear grooves. What is necessary is just to form by height. After that, when the third resin (or metal) 8 is a resin, the concave portion 7 is processed to a predetermined size when the third resin 8 is provided. Therefore, the third resin 8 is disposed by dispensing or the like. However, the variation in warpage is not large.

しかし、第３の樹脂（または金属）８が金属の場合には、所定の寸法に加工された凹部７に、所定の寸法に加工された金属８を配置することになるため、反りのばらつきは大きくならない。   However, when the third resin (or metal) 8 is a metal, the metal 8 processed to a predetermined dimension is disposed in the concave portion 7 processed to a predetermined dimension, so that variation in warpage is not caused. It doesn't grow up.

また、第２の樹脂６のガラス転移温度は、樹脂回路基板４のガラス転移温度より低いことが望ましい。さらに、第３の樹脂（または金属）８は、第２の樹脂６よりも低いガラス転移温度であることが望ましい。通常、樹脂回路基板４は１５０〜２２０℃のガラス転移温度である。また、第２の樹脂のガラス転移温度は１２０〜１９０℃であり、第３の樹脂は１００〜１７０℃のガラス転移温度である。   The glass transition temperature of the second resin 6 is preferably lower than the glass transition temperature of the resin circuit board 4. Furthermore, it is desirable that the third resin (or metal) 8 has a glass transition temperature lower than that of the second resin 6. Usually, the resin circuit board 4 has a glass transition temperature of 150 to 220 ° C. The glass transition temperature of the second resin is 120 to 190 ° C, and the third resin has a glass transition temperature of 100 to 170 ° C.

樹脂は、ガラス転移温度以上の温度になると、その弾性率は急激に低くなる。弾性率が低くなれば、反りを発生するための応力は小さくなり、反りは低減される。このため第２の樹脂６の一部が、第３の樹脂８に置き換わることにより、特に、高温時の樹脂回路基板４上で半導体素子２を覆う部分の弾性率が見かけ上小さくなり、反りを発生する応力が抑えられ、反り量が低減される。第３の樹脂８のみの弾性率が低くなることにより、半導体装置１の反りを部分的に緩和する効果もある。   When the temperature of the resin becomes equal to or higher than the glass transition temperature, the elastic modulus of the resin rapidly decreases. When the elastic modulus is lowered, the stress for generating the warp is reduced and the warp is reduced. For this reason, when a part of the second resin 6 is replaced with the third resin 8, in particular, the elastic modulus of the portion covering the semiconductor element 2 on the resin circuit board 4 at the time of high temperature is apparently reduced, and the warp is reduced. The generated stress is suppressed and the amount of warpage is reduced. Since the elastic modulus of only the third resin 8 is lowered, there is also an effect of partially relaxing the warp of the semiconductor device 1.

無論、既述したように、金型を用いて射出成形することにより第２の樹脂６を成形する一般的なトランスファーモールド手法や、ディスペンスなどで第２の樹脂６を設ける方法と比べて、凹部７を設けて、所定の寸法に形成された凹部７に第３の樹脂（または金属）８を配置することが、定量的に反りをコントロールするために有効であることは言うまでもない。   Of course, as described above, the concave portion is smaller than the general transfer molding method of molding the second resin 6 by injection molding using a mold or the method of providing the second resin 6 by dispensing or the like. It is needless to say that it is effective to quantitatively control the warpage by providing the third resin (or metal) 8 in the concave portion 7 formed to have a predetermined size by providing 7.

次に、本発明における半導体装置の製造方法について説明する。本発明における半導体装置は、フリップチップ実装工程、封止樹脂形成工程、封止樹脂凹部形成工程、凹部樹脂塗布工程、半導体装置切断工程などを経て製造される。樹脂回路基板は、半導体装置が多数個取れるように形成されているものとする。   Next, a method for manufacturing a semiconductor device in the present invention will be described. The semiconductor device in the present invention is manufactured through a flip chip mounting process, a sealing resin forming process, a sealing resin recess forming process, a recess resin applying process, a semiconductor device cutting process, and the like. The resin circuit board is formed so that a large number of semiconductor devices can be taken.

図５は本発明の半導体装置の製造方法に係る実施の形態の製造工程のフローチャート、図６は本実施の形態における各製造工程の半導体装置の状態を示す斜視図である。   FIG. 5 is a flowchart of the manufacturing process according to the embodiment of the semiconductor device manufacturing method of the present invention, and FIG. 6 is a perspective view showing the state of the semiconductor device in each manufacturing process according to the present embodiment.

ステップ（Ｓ１）において、図６（ａ）に示すフリップチップ実装が行われ、実施の形態１にて説明したように、半導体素子２が樹脂回路基板４に接合される。接合のために半導体素子２と樹脂回路基板４間の隙間に熱硬化性エポキシ樹脂である第１の樹脂５が設けられて、フリップチップ実装された樹脂回路基板９となる。   In step (S1), the flip chip mounting shown in FIG. 6A is performed, and the semiconductor element 2 is bonded to the resin circuit board 4 as described in the first embodiment. A first resin 5, which is a thermosetting epoxy resin, is provided in the gap between the semiconductor element 2 and the resin circuit board 4 for bonding, thereby forming a resin circuit board 9 that is flip-chip mounted.

次に、ステップ（Ｓ２）において、図６（ｂ）に示す封止樹脂形成が行われ、フリップチップ接合された樹脂回路基板９上に第２の樹脂６を形成する。本実施の形態では、金型を用いて射出成形する一般的なトランスファーモールド手法を用いて、第２の樹脂６を熱硬化により成形して、第２の樹脂６が形成された樹脂回路基板１０となる。   Next, in step (S2), the sealing resin shown in FIG. 6B is formed, and the second resin 6 is formed on the resin circuit board 9 that is flip-chip bonded. In the present embodiment, the resin circuit board 10 on which the second resin 6 is formed by molding the second resin 6 by thermosetting using a general transfer mold method in which injection molding is performed using a mold. It becomes.

その後、ステップ（Ｓ３）において、図６（ｃ）に示す封止樹脂凹部形成が行われ、第２の樹脂６が形成された樹脂回路基板１０に凹部７を形成する。本実施の形態では、第２の樹脂６が形成された樹脂回路基板１０に、回転ブレード１１を移動させることによって凹部７を形成して樹脂回路基板１２を得る。例えば、凹部７を形成するために、回転ブレード１１を複数回往復移動する。   Thereafter, in step (S3), the concave portion 7 is formed in the resin circuit board 10 on which the sealing resin concave portion shown in FIG. 6C is formed and the second resin 6 is formed. In the present embodiment, the concave portion 7 is formed by moving the rotary blade 11 on the resin circuit board 10 on which the second resin 6 is formed, and the resin circuit board 12 is obtained. For example, the rotary blade 11 is reciprocated a plurality of times to form the recess 7.

次に、ステップ（Ｓ４）において、図６（ｄ）に示す凹部樹脂塗布が行われ、本実施の形態では、ディスペンサ１３によって凹部７に第３の樹脂８を供給する。あらかじめ凹部７が形成されているために、その凹部７に容易に第３の樹脂８を流し込むことが可能である。その後、第３の樹脂８が熱硬化して、第３の樹脂８が設けられた樹脂回路基板１４となる。   Next, in step (S4), the concave resin application shown in FIG. 6D is performed, and in the present embodiment, the third resin 8 is supplied to the concave portion 7 by the dispenser 13. Since the recess 7 is formed in advance, the third resin 8 can be easily poured into the recess 7. Thereafter, the third resin 8 is thermally cured to form a resin circuit board 14 provided with the third resin 8.

ステップ（Ｓ５）において、図６（ｅ）に示す半導体装置切断が行われ、樹脂回路基板１４を分割する。本実施の形態では、回転ブレード１５により樹脂回路基板１４を分割し、図６（ｆ）に示す個々の半導体装置１が製造される。   In step (S5), the semiconductor device shown in FIG. 6E is cut, and the resin circuit board 14 is divided. In the present embodiment, the resin circuit board 14 is divided by the rotating blade 15, and the individual semiconductor devices 1 shown in FIG. 6F are manufactured.

本発明は、樹脂回路基板に半導体素子がフリップチップ実装される小型軽量の半導体装置およびその製造方法に適用できる。   The present invention can be applied to a small and lightweight semiconductor device in which a semiconductor element is flip-chip mounted on a resin circuit board and a manufacturing method thereof.

１ 半導体装置
２ 半導体素子
３ 突起電極
４ 樹脂回路基板
５ 第１の樹脂
６ 第２の樹脂
７ 凹部
８ 第３の樹脂または金属
９ フリップチップ実装された樹脂回路基板
１０ 第２の樹脂により封止樹脂が形成された樹脂回路基板
１１，１５ 回転ブレード
１２ 封止樹脂に凹部を形成した樹脂回路基板
１３ ディスペンサ
１４ 第３の樹脂により封止樹脂が形成された樹脂回路基板 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor element 3 Protruding electrode 4 Resin circuit board 5 1st resin 6 2nd resin 7 Recessed part 8 3rd resin or metal 9 Resin circuit board 10 flip-chip mounted The sealing resin by 2nd resin Resin circuit boards 11, 15 formed with a rotating blade 12 Resin circuit board 13 with a recess formed in the sealing resin 13 Dispenser 14 Resin circuit board with a sealing resin formed of a third resin

Claims (7)

突起電極が形成された半導体素子と、前記半導体素子が前記突起電極を介して実装された回路基板と、前記半導体素子と前記回路基板間の隙間を封止する第１の樹脂と、前記半導体素子の実装面と対向する上面を覆い、かつ前記半導体素子の上部に凹部が形成される第２の樹脂とを備え、第３の樹脂または金属が前記凹部に設けられることを特徴とする半導体装置。   A semiconductor element on which a protruding electrode is formed; a circuit board on which the semiconductor element is mounted via the protruding electrode; a first resin that seals a gap between the semiconductor element and the circuit board; and the semiconductor element A semiconductor device comprising: a second resin that covers an upper surface facing the mounting surface of the semiconductor element and has a second resin in which a recess is formed on the semiconductor element, and a third resin or metal is provided in the recess. 前記凹部の高さが、前記第２の樹脂で覆われる部分より低く、かつ前記半導体素子の裏面より高いことを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a height of the concave portion is lower than a portion covered with the second resin and higher than a back surface of the semiconductor element. 前記凹部が少なくとも１本の直線状の溝によって形成され、前記直線状の溝の幅が前記半導体素子の短辺の幅より小さいことを特徴とする請求項１または２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the recess is formed by at least one linear groove, and the width of the linear groove is smaller than the width of the short side of the semiconductor element. 複数本の前記溝が、前記半導体素子の中心上で交差することを特徴とする請求項１〜３のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the plurality of grooves intersect on the center of the semiconductor element. 前記第２の樹脂の熱膨張係数が、前記回路基板の熱膨張係数よりも大きく、かつ前記第１の樹脂の熱膨張係数より小さく、前記第３の樹脂または金属の熱膨張係数が前記第２の樹脂の熱膨張係数よりも小さいことを特徴とする請求項１〜請求項４のいずれか１項に記載の半導体装置。   The thermal expansion coefficient of the second resin is larger than the thermal expansion coefficient of the circuit board and smaller than the thermal expansion coefficient of the first resin, and the thermal expansion coefficient of the third resin or metal is the second thermal expansion coefficient. The semiconductor device according to claim 1, wherein the coefficient of thermal expansion is smaller than that of the resin. 前記第２の樹脂のガラス転移温度が前記回路基板のガラス転移温度よりも低く、前記第３の樹脂または金属のガラス転移温度が前記第２の樹脂のガラス転移温度よりも低いことを特徴とする請求項１〜５のいずれか１項に記載の半導体装置。   The glass transition temperature of the second resin is lower than the glass transition temperature of the circuit board, and the glass transition temperature of the third resin or metal is lower than the glass transition temperature of the second resin. The semiconductor device according to claim 1. 基板の一主面に第１の樹脂を塗布する工程と、前記第１の樹脂を介して前記回路基板の一主面上に複数の半導体素子を実装する工程と、実装した前記複数の半導体素子を前記第２の樹脂で封止する工程と、前記第２の樹脂における前記半導体素子の上部に凹部を形成する工程と、前記凹部に第３の樹脂または金属を塗布する工程と、前記半導体素子が少なくとも１個含まれるように前記基板を分割して、それぞれを半導体装置とする工程とを有することを特徴とする半導体装置の製造方法。   Applying a first resin to one principal surface of the substrate; mounting a plurality of semiconductor elements on one principal surface of the circuit board via the first resin; and mounting the plurality of semiconductor elements Sealing with the second resin, forming a recess in the upper portion of the semiconductor element in the second resin, applying a third resin or metal to the recess, and the semiconductor element Dividing the substrate so that at least one is included, and forming each of the substrates into a semiconductor device.
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