JP2007194543A - Semiconductor device, and method of manufacturing same - Google Patents

Semiconductor device, and method of manufacturing same Download PDF

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JP2007194543A
JP2007194543A JP2006013581A JP2006013581A JP2007194543A JP 2007194543 A JP2007194543 A JP 2007194543A JP 2006013581 A JP2006013581 A JP 2006013581A JP 2006013581 A JP2006013581 A JP 2006013581A JP 2007194543 A JP2007194543 A JP 2007194543A
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substrate
semiconductor device
semiconductor
semiconductor chip
semiconductor element
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Eiji Takano
野 英 治 高
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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Abstract

<P>PROBLEM TO BE SOLVED: To remove a defect of an underfill film caused by stress concentration in a semiconductor device which is filled up with an underfill after a substrate and a semiconductor chip are connected, and in which a heat spreader is attached to the semiconductor chip. <P>SOLUTION: A semiconductor device comprises a substrate including an element mounting electrode on its principal surface; a semiconductor element which includes an electrode connected with the mounting electrode on its lower surface, and in which a gap between the substrate and the lower surface is filled with a resin; and a heat sink which is attached onto an upper surface of the semiconductor element, and of which an edge is directed downward and reaches the substrate. The edge of the heat sink is fixed on the substrate by a resin adhesive material in a portion other than the portion corresponding to a corner of the semiconductor element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置およびその製造方法に係り、特にフリップチップ型の半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a flip chip type semiconductor device and a manufacturing method thereof.

半導体装置には多くの型式のものがあるが、最近はフリップチップ型のものも多用されている。これは半導体素子（半導体チップ）をフェイスダウンの形で樹脂等でなる基板に取り付け、この基板には半導体チップを接続するための接続電極および配線と裏面に実装用のパッドを設けるようにしたものである。この実装用パッドはマトリクス状に配設され、はんだボールが形成されるボールグリッドアレイ（ＢＧＡ）の形式をとるものが知られている（特許文献１参照）。   There are many types of semiconductor devices, but flip-chip types are also frequently used recently. This is a semiconductor element (semiconductor chip) attached to a substrate made of resin or the like in a face-down manner, and this substrate is provided with connection electrodes for connecting the semiconductor chip, wiring, and mounting pads on the back surface. It is. It is known that the mounting pads are arranged in a matrix and take the form of a ball grid array (BGA) in which solder balls are formed (see Patent Document 1).

このような形式の半導体装置では、半導体チップの電極と接続電極を接続することにより基板に取り付けた後、半導体チップと基板との間の空隙にアンダーフィルと称される樹脂が流入され、硬化される。このアンダーフィルは基板と半導体チップの接続強度を増加させ、信頼性を向上させるために採用されるが、その硬化によって基板が半導体チップの外方で下方に反る傾向が一般的に見られる。   In such a type of semiconductor device, after being attached to the substrate by connecting the electrodes of the semiconductor chip and the connection electrodes, a resin called underfill is poured into the gap between the semiconductor chip and the substrate and cured. The This underfill is employed to increase the connection strength between the substrate and the semiconductor chip and to improve the reliability. However, the substrate generally warps downward outside the semiconductor chip due to its curing.

一方、半導体チップは発熱が大きいため、自己の発熱による熱暴走で誤動作が生じたり、焼損が起きたりすることのないように、適当な放熱を行う必要がある。このため、ヒートスプレッダと称される放熱用の金属板を半導体チップの上面に取り付け、放熱面積を増加させるとともに熱を移動させてチップ表面から放熱を行っている。一般に、ヒートスプレッダの周縁部は基板の形状に合わせて折り曲げられ、その先端は全周で基板と接着される。
特開２０００−３４９２０３号 On the other hand, since the semiconductor chip generates a large amount of heat, it is necessary to perform appropriate heat dissipation so that a malfunction due to thermal runaway due to its own heat generation or burning does not occur. For this reason, a heat radiating metal plate called a heat spreader is attached to the upper surface of the semiconductor chip to increase the heat radiating area and move heat to radiate heat from the chip surface. In general, the peripheral edge of the heat spreader is bent in accordance with the shape of the substrate, and its tip is bonded to the substrate all around.
JP 2000-349203 A

ヒートスプレッダをその周縁部で基板と接着させることにより、前述した基板が下方に反ることを防止できるため、反り量は著しく少なくなる。しかしながら、ヒートスプレッダ接着による反り矯正力が強すぎ、半導体チップの周端部におけるアンダーフィルに応力が集中し、この部分にクラックが生じるという問題が生じている。このクラックは、特に半導体チップのコーナ部で生じやすい。   By adhering the heat spreader to the substrate at the peripheral edge thereof, the above-described substrate can be prevented from warping downward, and the amount of warpage is significantly reduced. However, there is a problem in that the warp correction force due to heat spreader adhesion is too strong, stress concentrates on the underfill at the peripheral edge of the semiconductor chip, and cracks occur in this portion. This crack is particularly likely to occur at the corner of the semiconductor chip.

したがって、本発明の目的は、基板と半導体チップを接続後にアンダーフィルが充填され、かつ半導体チップ表面にヒートスプレッダが取りつけられた半導体装置において、アンダーフィル膜クラックの発生がない半導体装置を提供することである。   Accordingly, an object of the present invention is to provide a semiconductor device in which an underfill film is not generated in a semiconductor device in which an underfill is filled after a substrate and a semiconductor chip are connected and a heat spreader is attached to the surface of the semiconductor chip. is there.

本発明にかかる半導体装置は、素子実装用電極をその主表面に有する基板と、下面に前記実装用電極と接続された電極を有し、前記基板と下面との間に樹脂が充填された半導体素子と、前記半導体素子の上面に取り付けられ、その端辺部が下方に向けられて前記基板に達する放熱板とを備え、前記放熱板の端辺部は、前記半導体素子のコーナ部に対応する部分以外の部分で前記基板に樹脂接着材で固着されたことを特徴とするものである。   A semiconductor device according to the present invention includes a substrate having an element mounting electrode on its main surface, an electrode connected to the mounting electrode on the lower surface, and a semiconductor filled with resin between the substrate and the lower surface An element and a heat sink attached to the upper surface of the semiconductor element, the end of which is directed downward and reaches the substrate, and the end of the heat sink corresponds to a corner of the semiconductor element The substrate is fixed to the substrate with a resin adhesive at a portion other than the portion.

また、本発明にかかる半導体装置の製造方法は、素子接続用電極をその主表面に有する基板を準備し、下面に前記接続用電極を有する半導体素子を前記素子接続用電極により接続し、前記素子の下面と前記基板との間に樹脂を充填し、前記半導体素子の上面に、端辺部が下方に向けられて前記基板に達する放熱板を取り付け、前記放熱板の端辺部を、前記半導体素子のコーナ部に対応する部分以外の部分で前記基板に樹脂接着材で固着することを特徴とするものである。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a substrate having an element connection electrode on a main surface thereof; connecting a semiconductor element having the connection electrode on a lower surface by the element connection electrode; A resin is filled between the lower surface of the semiconductor substrate and the substrate, and a heat radiating plate is attached to the upper surface of the semiconductor element so that the edge portion is directed downward and reaches the substrate. The substrate is fixed to the substrate with a resin adhesive at a portion other than the portion corresponding to the corner portion of the element.

本発明の半導体装置においては、ヒートスプレッダの半導体チップのコーナ部に対応する部分は基板とは接着されていないので、半導体チップのコーナ部において半導体チップと基板との間に流し込まれたアンダーフィル樹脂で発生する応力が低減され、クラックや膜はがれが生じにくくなり、半導体装置の信頼性が向上する。   In the semiconductor device of the present invention, since the portion corresponding to the corner portion of the semiconductor chip of the heat spreader is not bonded to the substrate, the underfill resin poured between the semiconductor chip and the substrate at the corner portion of the semiconductor chip. The generated stress is reduced, cracks and film peeling are less likely to occur, and the reliability of the semiconductor device is improved.

本発明の半導体装置の製造方法においては、上述のような特徴を有する半導体装置を確実に得ることができる。   In the method for manufacturing a semiconductor device of the present invention, a semiconductor device having the above-described characteristics can be obtained with certainty.

以下、図面を参照して本願発明の実施の形態を説明する。なお、図面における寸法は模式的なもので、実際の寸法と正確な比例関係にあるものではない。   Embodiments of the present invention will be described below with reference to the drawings. In addition, the dimension in drawing is typical and does not have an exact proportional relationship with an actual dimension.

図１は本発明にかかる半導体装置の外観を示す斜視図、図２は内部の接着状態を示す、ヒートスプレッダの上面を除去して表した平面図である。また、図３および図４は図１および図２のＡ−Ａ線に沿った断面図であり、図３はヒートスプレッダ装着前、図４はヒートスプレッダ装着後の様子を示している。   FIG. 1 is a perspective view showing an external appearance of a semiconductor device according to the present invention, and FIG. 2 is a plan view showing an internal bonding state with the upper surface of a heat spreader removed. 3 and 4 are cross-sectional views taken along line AA in FIGS. 1 and 2, FIG. 3 shows a state before the heat spreader is mounted, and FIG. 4 shows a state after the heat spreader is mounted.

一般にフレキシブル基板である基板１１の上面には、半導体素子である半導体チップ２１の電極と対応するように設けられた素子接続電極１２が設けられており、この素子接続電極は半導体チップの電極２２と接続される。この際、半導体チップ２１はその本来の上面の周囲に電極２２が配置されたものが多く、このような半導体チップ２１を用いる場合には基板への接続時にはこの上面が下向きになるフェイスダウンの形となる。以下の説明においてフェイスダウンで接続された半導体チップにおいても、実際に上側の面を上面と称することとする。   In general, an element connection electrode 12 provided so as to correspond to an electrode of a semiconductor chip 21 which is a semiconductor element is provided on the upper surface of the substrate 11 which is a flexible substrate. The element connection electrode is connected to the electrode 22 of the semiconductor chip. Connected. At this time, many of the semiconductor chips 21 have electrodes 22 arranged around the original upper surface. When such a semiconductor chip 21 is used, the semiconductor chip 21 is face-down shaped such that the upper surface faces downward when connected to the substrate. It becomes. In the following description, even in a semiconductor chip connected face down, the upper surface is actually referred to as the upper surface.

基板１１の素子接続電極１２に半導体チップ２１の電極２２を接続した後、基板と半導体チップ間の間隙にはアンダーフィル樹脂３１が充填されるが、このアンダーフィル樹脂３１の収縮により図４に示すように基板１１は周辺部は下方に反る現象が見られる。   After the electrode 22 of the semiconductor chip 21 is connected to the element connection electrode 12 of the substrate 11, the gap between the substrate and the semiconductor chip is filled with an underfill resin 31. Thus, the substrate 11 has a phenomenon that the peripheral portion warps downward.

また、基板には素子接続用電極を外部接続部へ導く配線も形成されている。典型的なものは、基板裏面に設けられたアレイ状の実装用電極１３であり、この実装用電極と素子接続用電極とは、一般に基板を貫通して表裏導通を行うスルーホール１４と配線を介して接続される。そしてこのアレイ状の実装用電極には最終的にははんだボール１５が付着される。この形式の実装構造は、ボールグリッドアレイ（ＢＧＡ）と称されている。   In addition, wiring for guiding the element connection electrode to the external connection portion is also formed on the substrate. A typical one is an array-like mounting electrode 13 provided on the back surface of the substrate. The mounting electrode and the element connecting electrode are generally connected to a through hole 14 and a wiring that penetrate the substrate and conducts conduction between the front and back sides. Connected through. Finally, solder balls 15 are attached to the arrayed mounting electrodes. This type of mounting structure is called a ball grid array (BGA).

また、図４を参照すると、半導体チップ２１の上面２１ａにはヒートスプレッダ４１が取り付けられている。このヒートスプレッダ４１は放熱性の良い銅等の材料でなり、半導体チップ２１とは熱伝導性の優れたベーストにより貼り付けられている。ヒートスプレッダの周辺部４１ａは半導体チップを取り囲むように下方に折り曲げられ、その下端４１ｂが基板面に達するように成形されている。また、２辺の周辺部４１ａは側辺４１ｃで互いに当接するが、この部分は半導体チップ２１のコーナ部２１ｂに対応するものである。   Referring to FIG. 4, a heat spreader 41 is attached to the upper surface 21 a of the semiconductor chip 21. The heat spreader 41 is made of a material such as copper having good heat dissipation, and is attached to the semiconductor chip 21 with a base having excellent heat conductivity. The peripheral portion 41a of the heat spreader is bent downward so as to surround the semiconductor chip, and is shaped so that its lower end 41b reaches the substrate surface. Further, the peripheral portions 41a of the two sides are in contact with each other at the side sides 41c, and this portion corresponds to the corner portion 21b of the semiconductor chip 21.

ヒートスプレッダ４１の厚さは（約２ｍｍ？）で周辺部の折り曲げ高さは約３ｍｍとなっている。なお、ヒートスプレッダはこの実施例のように折り曲げで製作する以外に、金属ブロックの切削やプレス成形、ダイキャストモールドなどで製作することができる。   The thickness of the heat spreader 41 is (about 2 mm?) And the bending height of the peripheral portion is about 3 mm. The heat spreader can be manufactured by cutting a metal block, press forming, die casting mold or the like in addition to manufacturing by bending as in this embodiment.

このヒートスプレッダの下端４１ｂと基板面１１ａ間には接着樹脂４２が塗布され、固定される。この固定により、前述したように基板１１の反りが矯正される。   Adhesive resin 42 is applied and fixed between the lower end 41b of the heat spreader and the substrate surface 11a. By this fixing, the warp of the substrate 11 is corrected as described above.

図１、図２、図４から明らかなように、この実施の形態においては、半導体チップ２１のコーナ部２１ｂに対応するヒートスプレッダ部分４１ｂには接着剤は塗布されておらず、その結果接着が行われていない。従来の同形式の半導体装置では、ヒートスプレッダの折り曲げられた先端の全面に接着剤が塗布されている点がこの実施例とは相違する。   As is apparent from FIGS. 1, 2, and 4, in this embodiment, no adhesive is applied to the heat spreader portion 41b corresponding to the corner portion 21b of the semiconductor chip 21, and as a result, adhesion is performed. I have not been told. A conventional semiconductor device of the same type is different from this embodiment in that an adhesive is applied to the entire surface of the bent end of the heat spreader.

図１および図２に示された本実施例の場合には、従来のものと異なってヒートスプレッダ先端の全面には接着材は塗布されていないが、コーナ部に対応する部分を除けばヒートスプレッダの各辺の大部分は基板と接着されているため、全体として基板の反りを矯正する効果は残存している。しかも半導体チップのコーナ部に対応する部分が接着されないことにより過度の反り矯正が行われないため、半導体チップのコーナ部でのアンダーフィル樹脂に過大な応力が集中することはなく、アンダーフィル樹脂のクラックや膜剥がれの発生は著しく減少する。   In the case of this embodiment shown in FIGS. 1 and 2, unlike the conventional one, no adhesive is applied to the entire surface of the heat spreader tip, but each part of the heat spreader is excluded except for the portion corresponding to the corner portion. Since most of the sides are bonded to the substrate, the effect of correcting the warpage of the substrate remains as a whole. Moreover, since excessive warp correction is not performed because the portion corresponding to the corner portion of the semiconductor chip is not adhered, excessive stress is not concentrated on the underfill resin at the corner portion of the semiconductor chip, and the underfill resin The occurrence of cracks and film peeling is significantly reduced.

図５は図１から図３までに示した実施例の変形例を示すもので、図１における折り曲げられた周辺部４１ａの一部を示している。この例によれば、半導体チップのコーナ部２１ｂに対応するヒートスプレッダの部分４１ｃにおいて、傾斜辺を有する切り欠き部４１ｄが形成されている。   FIG. 5 shows a modification of the embodiment shown in FIGS. 1 to 3, and shows a part of the bent peripheral portion 41a in FIG. According to this example, a notch portion 41d having an inclined side is formed in the heat spreader portion 41c corresponding to the corner portion 21b of the semiconductor chip.

このように構成することにより、ヒートスプレッダ側に接着剤を塗布する際、確実に予定範囲のみに塗布することができ、半導体チップのコーナ対応部への接着剤付着を避けることができるため、作業性が良好で、迅速な作業が可能であり、かつ一定品質を保つことができる。   By configuring in this way, when applying the adhesive to the heat spreader side, it can be surely applied only to a predetermined range, and adhesion of the adhesive to the corner-corresponding portion of the semiconductor chip can be avoided. Is good, can work quickly, and can maintain a certain quality.

この切り欠き部の形状の他の一例としては、図６に示すように矩形状の切り欠き部４１ｅを有するものも考えられるが、要は半導体チップ２１のコーナ部２１ｂ近傍のヒートスプレッダの下方に向かう先端部が基板１１から少しでも離れるような形状になっていればどのような形状であっても良い。   As another example of the shape of the cutout portion, a shape having a rectangular cutout portion 41e as shown in FIG. 6 is conceivable, but the main point is to go below the heat spreader in the vicinity of the corner portion 21b of the semiconductor chip 21. Any shape may be used as long as the tip is separated from the substrate 11 even a little.

本発明にかかる半導体装置の外観を示す斜視図である。It is a perspective view which shows the external appearance of the semiconductor device concerning this invention. ヒートスプレッダ内部の半導体チップ、ヒートスプレッダ、基板の位置関係を示す、ヒートスプレッダの上面を除去して表した平面図である。It is the top view which removed and represented the upper surface of the heat spreader which shows the positional relationship of the semiconductor chip inside a heat spreader, a heat spreader, and a board | substrate. 図１および図２のＡ−Ａ線に沿った断面図であり、ヒートスプレッダ装着前の様子を示すものである。It is sectional drawing along the AA line of FIG. 1 and FIG. 2, and shows the mode before heat spreader mounting | wearing. 図１および図２のＡ−Ａ線に沿った断面図であり、ヒートスプレッダ装着後の様子を示すものである。It is sectional drawing along the AA line of FIG. 1 and FIG. 2, and shows the mode after heat spreader mounting | wearing. 図１における折り曲げられた周辺部において切り欠き部が形成された例を示す正面図である。It is a front view which shows the example in which the notch part was formed in the bent periphery part in FIG. 図１における折り曲げられた周辺部において図５とは異なる形状の切り欠き部が形成された例を示す正面図である。FIG. 6 is a front view showing an example in which a cutout portion having a shape different from that in FIG. 5 is formed in the bent peripheral portion in FIG. 1.

符号の説明Explanation of symbols

１１ 基板
１１ａ 基板上面
２１ 半導体チップ
２１ａ 半導体チップ上面
２１ｂ 半導体チップコーナ部
３１ アンダーフィル樹脂
４１ ヒートスプレッダ
４１ａ 周辺部
４１ｂ 周辺部先端
４１ｃ 半導体チップコーナ対応部
４１ｄ、４１ｅ 切り欠き部 11 substrate 11a substrate upper surface 21 semiconductor chip 21a semiconductor chip upper surface 21b semiconductor chip corner part 31 underfill resin 41 heat spreader 41a peripheral part 41b peripheral part tip 41c semiconductor chip corner corresponding part 41d, 41e notch part

Claims (5)

素子接続用電極をその主表面に有する基板と、
下面に前記接続用電極と接続された電極を有し、前記基板と前記下面との間に樹脂が充填された半導体素子と、
前記半導体素子の上面に取り付けられ、その端辺部が下方に向けられて前記基板に達する放熱板とを備え、
前記放熱板の端辺部は、前記半導体素子のコーナ部に対応する部分以外の部分で前記基板に樹脂接着材で固着されたことを特徴とする半導体装置。 A substrate having element connection electrodes on its main surface;
A semiconductor element having an electrode connected to the connection electrode on the lower surface and filled with a resin between the substrate and the lower surface;
A heat sink attached to the upper surface of the semiconductor element, the end of which is directed downward and reaches the substrate;
The semiconductor device according to claim 1, wherein an end side portion of the heat radiating plate is fixed to the substrate with a resin adhesive at a portion other than a portion corresponding to a corner portion of the semiconductor element. 前記放熱板の折り曲げ先端部の前記半導体素子のコーナ部に対応する部分は、前記基板から離れるように除去されていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a portion corresponding to a corner portion of the semiconductor element at a bent front end portion of the heat radiating plate is removed away from the substrate. 前記基板の下面には実装用電極が形成されていることを特徴とする請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein a mounting electrode is formed on a lower surface of the substrate. 前記実装用電極はボールグリッドアレイであることを特徴とする請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein the mounting electrode is a ball grid array. 素子接続用電極をその主表面に有する基板を準備し、
下面に前記接続用電極を有する半導体素子を前記素子接続用電極により接続し、
前記素子の下面と前記基板との間に樹脂を充填し、
前記半導体素子の上面に、端辺部が下方に向けられて前記基板に達する放熱板を取り付け、
前記放熱板の端辺部を、前記半導体素子のコーナ部に対応する部分以外の部分で前記基板に樹脂接着材で固着する、半導体装置の製造方法。 Preparing a substrate having element connection electrodes on its main surface,
A semiconductor element having the connection electrode on the lower surface is connected by the element connection electrode,
Filling a resin between the lower surface of the element and the substrate,
On the upper surface of the semiconductor element, a heat radiating plate whose end is directed downward and reaches the substrate is attached,
A manufacturing method of a semiconductor device, wherein an end side portion of the heat radiating plate is fixed to the substrate with a resin adhesive at a portion other than a portion corresponding to a corner portion of the semiconductor element.
JP2006013581A 2006-01-23 2006-01-23 Semiconductor device, and method of manufacturing same Pending JP2007194543A (en)

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