JP5212392B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5212392B2
JP5212392B2 JP2010018471A JP2010018471A JP5212392B2 JP 5212392 B2 JP5212392 B2 JP 5212392B2 JP 2010018471 A JP2010018471 A JP 2010018471A JP 2010018471 A JP2010018471 A JP 2010018471A JP 5212392 B2 JP5212392 B2 JP 5212392B2
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substrate
radiating plate
heat radiating
semiconductor element
solder
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JP2011159702A (en
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重信 稲葉
嘉治 原田
幸宏 前田
真治 太田
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent occurrence of void in an underfill as much as possible with respect to a semiconductor device constituted so that a semiconductor element is mounted on a substrate via a bump, a heat sink is provided on a substrate side of the semiconductor element, and the underfill is charged between the semiconductor element and substrate. <P>SOLUTION: The semiconductor device is constituted so that the semiconductor element 20 is mounted on the substrate 10 via the bump 30, the heat sink 40 is provided on one surface on the side of the substrate 10 of the semiconductor element 20, and the underfill 60 is charged between the one surface of the semiconductor element 20 and the substrate 10. The semiconductor device is provided with a through hole 11 penetrating the substrate 10 from the one surface to the other surface, and the heat sink 40 is inserted into the through hole 11 with a gap left with an inner surface of the through hole 11 and protruded from the other surface of the substrate 10. The gap between the heat sink 40 and the inner surface of the through hole 11 is used as an injection hole 12 for injecting the underfill 60, which is charged between the substrate 10 and semiconductor element 20 through the injection hole 12. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

本発明は、基板上にバンプを介して半導体素子を搭載し、半導体素子における基板側に放熱板を設けるとともに、半導体素子と基板との間にアンダーフィルを充填してなる半導体装置に関する。 The present invention, a semiconductor device is mounted via a bump on a substrate, provided with a heat sink substrate side of the semiconductor device, relates to a semiconductor equipment comprising filling an underfill between the semiconductor element and the substrate.

従来より、この種の半導体装置としては、基板と、一面をバンプを介して基板の一面に対向させた状態で基板の一面上に搭載された半導体素子と、半導体素子の一面のうちバンプ以外の部位に接続された放熱板と、半導体素子の一面と基板の一面との間にて、バンプおよび放熱板以外の部位に充填されたアンダーフィルとを備えた構成のものが一般的であり、そのようなものとして、特許文献１の半導体装置が開示されている
ここで、この特許文献１のものでは、半導体素子を基板にバンプにてフリップチップ実装する場合に、基板に貫通穴を設け、ここに放熱板を埋め込むことで、フェースダウン実装形態において素子裏面側への放熱性を向上させている。 Conventionally, as this type of semiconductor device, a substrate, a semiconductor element mounted on one surface of the substrate in a state where one surface is opposed to one surface of the substrate via bumps, and one surface of the semiconductor element other than the bump It is common to have a configuration including a heat sink connected to a part, and an underfill filled in a part other than the bump and the heat sink between one side of the semiconductor element and one side of the substrate, As such, the semiconductor device of Patent Document 1 is disclosed. In this Patent Document 1, when a semiconductor element is flip-chip mounted on a substrate by a bump, a through hole is provided in the substrate. By embedding a heat sink in the face-down mounting form, the heat dissipation to the back side of the element is improved.

特開特開２００８−２７０５１１号公報JP 2008-270511 A

しかし、上記特許文献１の構造では、半導体素子の中央部に大きな放熱板が存在する構造となっているため、従来通りアンダーフィルを半導体素子の端部における半導体素子と基板との隙間から注入すると、当該隙間にて半導体素子の中央部に位置する放熱板がアンダーフィル充填の妨げとなり、その充填性が低下し、アンダーフィルが空気を巻き込むといった問題がある。   However, since the structure of Patent Document 1 has a structure in which a large heat sink exists in the central portion of the semiconductor element, if underfill is injected from the gap between the semiconductor element and the substrate at the end of the semiconductor element as usual. The heat sink located at the center of the semiconductor element in the gap hinders underfill filling, and the fillability is lowered, and the underfill entraps air.

本発明は、上記問題に鑑みてなされたものであり、基板上にバンプを介して半導体素子を搭載し、半導体素子における基板側に放熱板を設けるとともに、半導体素子と基板との間にアンダーフィルを充填してなる半導体装置において、アンダーフィル内のボイド発生を極力防止することを目的とする。   The present invention has been made in view of the above problems. A semiconductor element is mounted on a substrate via bumps, a heat sink is provided on the substrate side of the semiconductor element, and an underfill is provided between the semiconductor element and the substrate. An object of the present invention is to prevent the generation of voids in the underfill as much as possible.

上記目的を達成するため、請求項１に記載の発明では、基板（１０）の一面上にバンプ（３０）を介して半導体素子（２０）を搭載し、半導体素子（２０）における基板（１０）側の一面に放熱板（４０）を設けるとともに、半導体素子（２０）の一面と基板（１０）の一面との間にアンダーフィル（６０）を充填してなる半導体装置において、基板（１０）には基板（１０）の一面から他面へ貫通し、放熱板（４０）よりも大きな貫通穴（１１）が設けられており、放熱板（４０）は貫通穴（１１）に対して貫通穴（１１）の内面と隙間を有した状態で挿入されるとともに、基板（１０）の他面より突出しており、放熱板（４０）と貫通穴（１１）の内面との隙間は、アンダーフィル（６０）が注入される注入口（１２）として構成され、この注入口（１２）を介して、基板（１０）の一面と半導体素子（２０）の一面との間にアンダーフィル（６０）が充填されており、放熱板（４０）のうち貫通穴（１１）内に位置する部位の側面は、基板（１０）の一面側から他面側へ拡がるテーパ面（４０ａ）とされており、当該側面と貫通穴（１１）の内面との隙間は基板（１０）の一面側から他面側へ向かって広くなっていることを特徴とする。 In order to achieve the above object, according to the first aspect of the present invention, the semiconductor element (20) is mounted on one surface of the substrate (10) via the bump (30), and the substrate (10) in the semiconductor element (20) is mounted. In a semiconductor device in which a heat sink (40) is provided on one side and an underfill (60) is filled between one side of the semiconductor element (20) and one side of the substrate (10), the substrate (10) Is penetrated from one surface of the substrate (10) to the other surface, and a through hole (11) larger than the heat radiating plate (40) is provided. The heat radiating plate (40) has a through hole ( 11) is inserted in a state having a gap with the inner surface of 11) and protrudes from the other surface of the substrate (10), and the gap between the heat sink (40) and the inner surface of the through hole (11) is underfill (60). ) Is injected as an inlet (12), Through the inlet (12), the substrate underfill (60) is filled between the one surface and one surface of the semiconductor element (20) in (10), the through hole of the heat radiating plate (40) (11 ) Is a tapered surface (40a) extending from one side of the substrate (10) to the other side, and the gap between the side surface and the inner surface of the through hole (11) is the substrate (10). ) It is widened from one side to the other side .

それによれば、基板（１０）の他面から上記隙間としての注入口（１２）を介して放熱板（４０）の周囲部分にアンダーフィル（６０）を注入できるので、従来のような半導体素子の端部から注入する場合に比べて、充填完了に必要なアンダーフィル（６０）の流れる距離を短くすることができ、また、放熱板（４０）の周囲にてアンダーフィル（６０）が空気を巻き込むのを極力抑制できる。よって、本発明によれば、アンダーフィル（６０）内のボイド発生を極力防止することができる。   According to this, since the underfill (60) can be injected from the other surface of the substrate (10) into the peripheral portion of the heat sink (40) through the injection port (12) as the gap, Compared with the case of injecting from the end, the distance through which the underfill (60) flows necessary for completion of filling can be shortened, and the underfill (60) entrains air around the heat sink (40). Can be suppressed as much as possible. Therefore, according to the present invention, generation of voids in the underfill (60) can be prevented as much as possible.

また、本発明の半導体装置を基板（１０）の他面側にて、マザーボードなどの外部の部材に対してはんだバンプ（８０）を介して実装する場合、当該外部の部材と基板（１０）との間に隙間が生じるが、この場合でも、本半導体装置では、基板（１０）の他面より放熱板（４０）を突出させているので、この突出部分にて放熱板（４０）と外部の部材との接続が適切に行える。   When the semiconductor device of the present invention is mounted on the other surface side of the substrate (10) with respect to an external member such as a mother board via the solder bump (80), the external member and the substrate (10) Even in this case, in this semiconductor device, the heat sink (40) protrudes from the other surface of the substrate (10). Connection with a member can be performed appropriately.

また、請求項１に記載の発明によれば、放熱板（４０）の側面を上記テーパ面（４０ａ）とすることで、その側面と貫通穴（１１）の内面との隙間も基板（１０）の一面側から他面側に向かって広くなるので、上記注入口（１２）としての当該隙間にて基板（１０）の他面側から、アンダーフィル（６０）を注入しやすくなる。 According to the invention described in claim 1, the side surface of the heat radiating plate (40) is the tapered surface (40 a), so that the gap between the side surface and the inner surface of the through hole (11) is also the substrate (10). Therefore, it is easy to inject the underfill (60) from the other surface side of the substrate (10) through the gap as the injection port (12).

また、本発明の半導体装置を基板（１０）の他面側にて、マザーボードなどの外部の部材に対してはんだバンプ（８０）を介して実装する場合において、基板（１０）の他面より突出する放熱板（４０）を外部の部材にはんだ付けするとき、放熱板（４０）や当該はんだバンプ（８０）の較差やはんだバンプ（８０）の潰れ具合によって、放熱板（４０）が高すぎて、つっかえ棒のようになったり、低すぎて外部の部材にはんだ付け出来なかったりなどの不具合が発生する恐れがある。請求項２、３、４の発明は、更にこのような点も考慮して創出されたものである。 Further, when the semiconductor device of the present invention is mounted on the other surface side of the substrate (10) to an external member such as a mother board via the solder bumps (80), it protrudes from the other surface of the substrate (10). When the heat sink (40) to be soldered to an external member, the heat sink (40) is too high due to the difference between the heat sink (40) and the solder bump (80) or the collapse of the solder bump (80). There is a risk of problems such as a stick stick or too low to be soldered to an external member. The inventions of claims 2 , 3 , and 4 have been created in consideration of such points.

まず、請求項２に記載の発明では、基板（１０）の一面上にバンプ（３０）を介して半導体素子（２０）を搭載し、半導体素子（２０）における基板（１０）側の一面に放熱板（４０）を設けるとともに、半導体素子（２０）の一面と基板（１０）の一面との間にアンダーフィル（６０）を充填してなる半導体装置において、基板（１０）には基板（１０）の一面から他面へ貫通し、一面側放熱板（４０）よりも大きな貫通穴（１１）が設けられており、放熱板（４０）は貫通穴（１１）に対して貫通穴（１１）の内面と隙間を有した状態で挿入されるとともに、基板（１０）の他面より突出しており、放熱板（４０）と貫通穴（１１）の内面との隙間は、アンダーフィル（６０）が注入される注入口（１２）として構成され、この注入口（１２）を介して、基板（１０）の一面と半導体素子（２０）の一面との間にアンダーフィル（６０）が充填されており、放熱板（４０）は、半導体素子（２０）側から第１の放熱板（４１）、第２の放熱板（４２）が、はんだ（４３）を介して重ね合わされた構成よりなり、放熱板（４０）において第１の放熱板（４１）と第２の放熱板（４２）との間のはんだ（４３）は、互いに離間して配置された複数個のはんだボール（４３ａ）よりなることを特徴とする。 First , in the invention according to claim 2 , the semiconductor element (20) is mounted on one surface of the substrate (10) via the bump (30), and heat is radiated on one surface of the semiconductor element (20) on the substrate (10) side. In a semiconductor device in which a plate (40) is provided and an underfill (60) is filled between one surface of a semiconductor element (20) and one surface of a substrate (10), the substrate (10) includes a substrate (10). A through hole (11) larger than the one-surface side heat sink (40) is provided from one surface to the other surface, and the heat sink (40) has a through hole (11) with respect to the through hole (11). It is inserted with a gap from the inner surface and protrudes from the other surface of the substrate (10), and the underfill (60) is injected into the gap between the heat sink (40) and the inner surface of the through hole (11). This inlet (12) is configured as this inlet (12) 2), an underfill (60) is filled between one surface of the substrate (10) and one surface of the semiconductor element (20), and the heat radiating plate (40) is formed from the semiconductor element (20) side. 1 of the heat radiation plate (41), a second heat radiating plate (42) is Ri Na from structure superimposed via a solder (43), the first heat radiating plate in the heat radiating plate (40) and (41) second The solder (43) between the heat radiation plate (42) is composed of a plurality of solder balls (43a) spaced apart from each other .

それによれば、上記請求項１の半導体装置と同様に、基板（１０）の他面から上記隙間としての注入口（１２）を介して放熱板（４０）の周囲部分にアンダーフィル（６０）を注入できるので、従来のような半導体素子の端部から注入する場合に比べて、充填完了に必要なアンダーフィル（６０）の流れる距離を短くすることができ、また、放熱板（４０）の周囲にてアンダーフィル（６０）が空気を巻き込むのを極力抑制できる。よって、本発明によれば、アンダーフィル（６０）内のボイド発生を極力防止することができる。   According to this, similarly to the semiconductor device of claim 1, the underfill (60) is provided from the other surface of the substrate (10) to the peripheral portion of the heat sink (40) through the inlet (12) as the gap. Since the injection can be performed, the distance through which the underfill (60) flows necessary for completion of filling can be shortened as compared with the case where the injection is performed from the end of the semiconductor element as in the prior art. It is possible to suppress the underfill (60) from entraining air as much as possible. Therefore, according to the present invention, generation of voids in the underfill (60) can be prevented as much as possible.

さらに、本発明によれば、放熱板（４０）を、半導体素子（２０）側から第１の放熱板（４１）、第２の放熱板（４２）が、はんだ（４３）を介して重ね合わされた構成としているので、基板（１０）の他面より突出する放熱板（４０）の突出先端部を外部の部材に、はんだ付けするときに、第１の放熱板（４１）と第２の放熱板（４２）との間のはんだ（４３）が、当該はんだ付け時のリフローの熱によって溶融もしくは軟化して変形するので、放熱板（４０）全体の高さが調整されるという利点がある。   Further, according to the present invention, the heat radiating plate (40) is overlapped with the first heat radiating plate (41) and the second heat radiating plate (42) via the solder (43) from the semiconductor element (20) side. Therefore, when the projecting tip of the heat radiating plate (40) protruding from the other surface of the substrate (10) is soldered to an external member, the first heat radiating plate (41) and the second heat radiating Since the solder (43) between the plate (42) is melted or softened and deformed by the heat of reflow during the soldering, there is an advantage that the overall height of the heat radiating plate (40) is adjusted.

つまり、本発明によれば、本半導体装置を基板（１０）の他面側にて、マザーボードなどの外部の部材に対してはんだバンプ（８０）を介して実装する場合において、基板（１０）の他面より突出する放熱板（４０）を外部の部材にはんだ付けするとき、そのはんだ付けを適切に行えるのである。   That is, according to the present invention, when the semiconductor device is mounted on the other surface side of the substrate (10) to an external member such as a mother board via the solder bumps (80), the substrate (10) When the heat sink (40) protruding from the other surface is soldered to an external member, the soldering can be performed appropriately.

また、請求項２に記載の発明では、第１の放熱板（４１）と第２の放熱板（４２）との間のはんだ（４３）は、互いに離間して配置された複数個のはんだボール（４３ａ）よりなるものとしており、それによれば、はんだ（４３）を上記はんだボール（４３ａ）より構成することで、当該はんだ（４３）の熱変形の自由度が大きくなるので、放熱板（４０）全体の高さ調整をより行いやすくなる。 In the second aspect of the present invention, the solder (43) between the first heat radiating plate (41) and the second heat radiating plate (42) is a plurality of solder balls arranged apart from each other. It is assumed consisting of (43a), according to which, the solder (43) by configuring than the solder balls (43a), since the degree of freedom in thermal deformation of the solder (43) is increased, the heat dissipation plate (40 ) It becomes easier to adjust the overall height.

さらに、請求項３に記載の発明のように、請求項２に記載の半導体装置において、第１の放熱板（４１）および第２の放熱板（４２）ともに、はんだボール（４３ａ）と接触する面には、はんだボール（４３ａ）の溶融時に個々のはんだボール（４３ａ）の位置を規定するための領域が設けられているものにすれば、複数個のはんだボール（４３ａ）のそれぞれを、当該はんだボール（４３ａ）の溶融時に適切に位置決めすることができる。 Further, as in the invention described in claim 3 , in the semiconductor device described in claim 2 , both the first heat radiating plate (41) and the second heat radiating plate (42) are in contact with the solder balls (43a). If the surface is provided with a region for defining the position of each solder ball (43a) when the solder ball (43a) is melted, each of the plurality of solder balls (43a) When the solder ball (43a) is melted, it can be properly positioned.

また、請求項４に記載の発明では、基板（１０）の一面上にバンプ（３０）を介して半導体素子（２０）を搭載し、半導体素子（２０）における基板（１０）側の一面に放熱板（４０）を設けるとともに、半導体素子（２０）の一面と基板（１０）の一面との間にアンダーフィル（６０）を充填してなる半導体装置において、基板（１０）には基板（１０）の一面から他面へ貫通し、一面側放熱板（４０）よりも大きな貫通穴（１１）が設けられており、放熱板（４０）は貫通穴（１１）に対して貫通穴（１１）の内面と隙間を有した状態で挿入されるとともに、基板（１０）の他面より突出しており、放熱板（４０）と貫通穴（１１）の内面との隙間は、アンダーフィル（６０）が注入される注入口（１２）として構成され、この注入口（１２）を介して、基板（１０）の一面と半導体素子（２０）の一面との間にアンダーフィル（６０）が充填されており、放熱板（４０）は、半導体素子（２０）側から第１の放熱板（４１）、第２の放熱板（４２）が、はんだ（４３）を介して重ね合わされた構成よりなり、第１の放熱板（４１）と第２の放熱板（４２）とでは、その平面サイズが異なるものであり、当該両放熱板（４１、４２）のうち平面サイズの大きい方におけるはんだ（４３）と接触する面には、はんだ（４３）の溶融時に溶融したはんだ（４３）を介して当該平面サイズの大きい方に対し平面サイズの小さい方の位置を規定するための領域が設けられていることを特徴とする。 According to a fourth aspect of the present invention, the semiconductor element (20) is mounted on one surface of the substrate (10) via the bump (30), and heat is dissipated on one surface of the semiconductor element (20) on the substrate (10) side. In a semiconductor device in which a plate (40) is provided and an underfill (60) is filled between one surface of a semiconductor element (20) and one surface of a substrate (10), the substrate (10) includes a substrate (10). A through-hole (11) larger than the one-surface side heat sink (40) is provided from one surface to the other surface, and the heat sink (40) is formed between the through-hole (11) and the through-hole (11). It is inserted with a gap from the inner surface and protrudes from the other surface of the substrate (10), and the underfill (60) is injected into the gap between the heat sink (40) and the inner surface of the through hole (11). This inlet (12) is configured as this inlet (12) 2), an underfill (60) is filled between one surface of the substrate (10) and one surface of the semiconductor element (20), and the heat radiating plate (40) is formed from the semiconductor element (20) side. 1 heat sink (41) and 2nd heat sink (42) consist of the structure piled up via the solder (43), 1st heat sink (41), 2nd heat sink (42), Then, the plane sizes thereof are different, and the surface of the heat radiating plates (41, 42) that comes into contact with the solder (43) on the larger one of the plane sizes is melted when the solder (43) is melted ( 43), an area for defining the position of the smaller plane size with respect to the larger plane size is provided.

それによれば、はんだ（４３）の溶融時にて溶融したはんだ（４３）のセルフアライメントにより、平面サイズの異なる両放熱板（４１、４２）を、適切に位置決めすることができる。   According to this, both the radiator plates (41, 42) having different plane sizes can be appropriately positioned by self-alignment of the solder (43) melted when the solder (43) is melted.

なお、特許請求の範囲およびこの欄で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。   In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

（ａ）は本発明の第１実施形態に係る半導体装置の概略断面図であり、（ｂ）は（ａ）中のＡ矢視の部分平面図である。(A) is a schematic sectional drawing of the semiconductor device which concerns on 1st Embodiment of this invention, (b) is a fragmentary top view of A arrow in (a). 第１実施形態の半導体装置の製造方法におけるアンダーフィルの充填工程を示す概略断面図である。It is a schematic sectional drawing which shows the filling process of the underfill in the manufacturing method of the semiconductor device of 1st Embodiment. 本発明の第２実施形態に係る半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態に係る半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device which concerns on 4th Embodiment of this invention. 本発明の第５実施形態に係る半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device which concerns on 5th Embodiment of this invention. 本発明の第６実施形態に係る半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device which concerns on 6th Embodiment of this invention. 本発明の第７実施形態に係る半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device which concerns on 7th Embodiment of this invention.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、説明の簡略化を図るべく、図中、同一符号を付してある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

（第１実施形態）
図１（ａ）は、本発明の第１実施形態に係る半導体装置の概略断面構成を示す図であり、図１（ｂ）は、図１（ａ）中の矢印Ａ方向から見たときの部分平面図である。 (First embodiment)
FIG. 1A is a diagram showing a schematic cross-sectional configuration of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a view as seen from the direction of arrow A in FIG. It is a partial top view.

本実施形態の半導体装置は、大きくは、基板１０と、バンプ３０を介して一面を基板１０の一面に対向させた状態で基板１０の一面上に搭載された半導体素子２０と、半導体素子２０の一面のうちバンプ３０以外の部位に接続された一面側放熱板４０と、半導体素子２０の他面に接続された他面側放熱板５０と、半導体素子２０の一面と基板１０の一面との間にて、バンプ３０および一面側放熱板４０以外の部位に充填されたアンダーフィル６０とを備えて構成されている。   The semiconductor device of the present embodiment is broadly divided into a substrate 10, a semiconductor element 20 mounted on one surface of the substrate 10 with one surface facing the one surface of the substrate 10 via the bumps 30, and the semiconductor element 20. Between one surface side heat sink 40 connected to a part other than the bump 30 in one surface, the other surface side heat sink 50 connected to the other surface of the semiconductor element 20, and between one surface of the semiconductor element 20 and one surface of the substrate 10. The underfill 60 filled in the parts other than the bumps 30 and the one-surface-side heat radiation plate 40 is configured.

基板１０は、本半導体装置をマザーボードなどの外部の部材に搭載するときに、半導体素子２０のインターポーザとして機能するものであり、たとえばセラミック基板、プリント基板、ガラスエポキシ基板などが挙げられる。   The substrate 10 functions as an interposer of the semiconductor element 20 when the semiconductor device is mounted on an external member such as a mother board, and examples thereof include a ceramic substrate, a printed substrate, and a glass epoxy substrate.

半導体素子２０は、基板１０の一面上にフリップチップ接合することのできるものであり、一般的な半導体プロセスにより形成されるＩＣチップなどである。また、バンプ３０は、半導体素子２０の周辺部寄りに設けられており、はんだや金、Ｃｕなど一般的なフリップチップ接合に用いられるバンプよりなる。   The semiconductor element 20 can be flip-chip bonded on one surface of the substrate 10 and is an IC chip formed by a general semiconductor process. The bumps 30 are provided near the periphery of the semiconductor element 20 and are made of bumps used for general flip chip bonding such as solder, gold, and Cu.

また、一面側放熱板４０および他面側放熱板５０は、ＣｕやＦｅなどの放熱性に優れた材料よりなり、それぞれ、半導体素子２０の一面（図１中の下面）、半導体素子２０の他面（図１中の上面）に対して、Ａｇペーストやはんだなどの熱伝導性の接合材７０を介して接合されている。   Further, the one-surface-side heat sink 40 and the other-surface heat-radiating plate 50 are made of a material having excellent heat dissipation properties such as Cu and Fe, and the other surface of the semiconductor element 20 (the lower surface in FIG. It is bonded to the surface (the upper surface in FIG. 1) via a heat conductive bonding material 70 such as Ag paste or solder.

ここで、一面側放熱板４０は、半導体素子２０よりも平面サイズが小さく、半導体素子２０の一面においてバンプ３０よりも当該一面の中央部寄りに位置している。また、他面側放熱板５０は、半導体素子２０よりも平面サイズが大きく、半導体素子２０の他面全体を覆うように設けられている。なお、これら半導体素子２０および両放熱板４０、５０の平面形状は、たとえば矩形状をなすものである。   Here, the one-surface-side heat radiating plate 40 has a smaller planar size than the semiconductor element 20, and is located closer to the center of the one surface than the bump 30 on one surface of the semiconductor element 20. Further, the other surface side heat dissipation plate 50 has a larger planar size than the semiconductor element 20 and is provided so as to cover the entire other surface of the semiconductor element 20. The planar shape of the semiconductor element 20 and the heat radiating plates 40 and 50 is, for example, rectangular.

また、アンダーフィル６０は、一般的なアンダーフィル材料よりなり、たとえばエポキシ樹脂や、エポキシ樹脂にガラスフィラーを含有させたものなどよりなる。   The underfill 60 is made of a general underfill material, and is made of, for example, an epoxy resin or an epoxy resin containing a glass filler.

ここで、基板１０のうち一面側放熱板４０に対応する部位には、基板１０の一面（図１中の上面）から他面（図１中の下面）へ貫通し、放熱板４０よりも大きな貫通穴１１が設けられている。つまり、貫通穴１１の開口サイズは一面側放熱板４０の平面サイズよりも大きいものである。具体的には、図１に示されるように、貫通穴１１は平面矩形の一面側放熱板４０よりも一回り大きい矩形開口形状の穴である。   Here, a portion of the substrate 10 corresponding to the one-surface side heat radiation plate 40 penetrates from one surface (upper surface in FIG. 1) to the other surface (lower surface in FIG. 1) and is larger than the heat radiation plate 40. A through hole 11 is provided. That is, the opening size of the through hole 11 is larger than the planar size of the one-surface side heat sink 40. Specifically, as shown in FIG. 1, the through hole 11 is a hole having a rectangular opening shape that is slightly larger than the one-surface side heat sink 40 of the planar rectangle.

そして、一面側放熱板４０は貫通穴１１に対して貫通穴１１の内面と隙間を有した状態で挿入されるとともに、基板１０の他面より突出している。具体的には、図１に示されるように、一面側放熱板４０の半導体素子２０の一面からの突出高さ（つまり厚さ）は、バンプ３０の高さおよび基板１０の厚さの合計寸法よりも大きいものとすることで、一面側放熱板４０の先端を基板１０の他面よりも突出させている。   The one-surface-side heat radiating plate 40 is inserted into the through hole 11 with a gap from the inner surface of the through hole 11, and protrudes from the other surface of the substrate 10. Specifically, as shown in FIG. 1, the protruding height (that is, the thickness) of the one-surface-side heat sink 40 from one surface of the semiconductor element 20 is the total dimension of the height of the bump 30 and the thickness of the substrate 10. By making it larger than this, the front end of the one-surface-side heat radiating plate 40 protrudes from the other surface of the substrate 10.

また、一面側放熱板４０と貫通穴１１の内面との隙間は、アンダーフィル６０が注入される注入口１２として構成され、この注入口１２を介して、基板１０の一面と半導体素子２０の一面との間にアンダーフィル６０が充填されている。   Further, a gap between the one-surface side heat sink 40 and the inner surface of the through hole 11 is configured as an injection port 12 into which the underfill 60 is injected, and one surface of the substrate 10 and one surface of the semiconductor element 20 through the injection port 12. Underfill 60 is filled in between.

ここでは、図１（ｂ）に示されるように、一面側放熱板４０の平面形状は矩形であり、貫通穴１１はそれよりも一回り大きい矩形の開口形状であり、一面側放熱板４０の平面形状における４辺すべてに上記隙間が設けられた形とされており、当該隙間としての注入口１２の開口形状は、矩形額縁形状とされている。   Here, as shown in FIG. 1B, the planar shape of the one-surface-side heat radiating plate 40 is a rectangle, and the through hole 11 is a rectangular opening shape that is slightly larger than that. The gap is provided in all four sides of the planar shape, and the opening shape of the injection port 12 as the gap is a rectangular frame shape.

また、注入口１２は、アンダーフィル６０の塗布に使用するシリンジ１のニードル１ａ（後述の図２参照）が十分に入り、かつ注入口１２内にてスムーズな移動ができるように、その開口サイズ、具体的には一面側放熱板４０と貫通穴１１の内面との隙間の幅等が設定されている。   Also, the inlet 12 has an opening size so that a needle 1a (see FIG. 2 described later) of the syringe 1 used for applying the underfill 60 can sufficiently enter and can smoothly move in the inlet 12. Specifically, the width of the gap between the one-surface side heat sink 40 and the inner surface of the through hole 11 is set.

また、図１（ａ）に示されるように、放熱板４０のうち貫通穴１１内に位置する部位の側面は、基板１０の一面側から他面側へ拡がるテーパ面４０ａとされており、当該側面と貫通穴１１の内面との隙間は基板１０の一面側から他面側へ向かって広くなっている。   Further, as shown in FIG. 1A, the side surface of the portion located in the through hole 11 of the heat radiating plate 40 is a tapered surface 40a extending from one surface side of the substrate 10 to the other surface side. A gap between the side surface and the inner surface of the through hole 11 becomes wider from one surface side of the substrate 10 toward the other surface side.

具体的には、一面側放熱板４０は、このテーパ面４０ａを介して半導体素子２０側の部位がそれとは反対側の部位に比べて平面サイズが大きいものとされている。なお、図１（ｂ）では、このテーパ面の構成は図示せずに省略してある。   Specifically, the one-surface-side heat radiating plate 40 is configured such that the portion on the semiconductor element 20 side has a larger planar size than the portion on the opposite side through the tapered surface 40a. In addition, in FIG.1 (b), the structure of this taper surface is abbreviate | omitted not shown.

また、基板１０の他面のうち貫通穴１１の周囲には、複数個のはんだよりなるはんだバンプ８０が設けられている。このはんだバンプ８０によって、本半導体装置はマザーボードなどの外部の部材に対して接合され、当該外部の部材への本半導体装置の搭載が行われるようになっている。   A solder bump 80 made of a plurality of solders is provided around the through hole 11 on the other surface of the substrate 10. By this solder bump 80, the present semiconductor device is bonded to an external member such as a mother board, and the semiconductor device is mounted on the external member.

次に、本半導体装置の製造方法について、図２を参照して述べる。図２は、本半導体装置の製造方法におけるアンダーフィルの充填工程を示す概略断面図である。   Next, a method for manufacturing the semiconductor device will be described with reference to FIG. FIG. 2 is a schematic cross-sectional view showing an underfill filling step in the manufacturing method of the semiconductor device.

本製造方法では、半導体素子２０の一面、他面に、それぞれ一面側放熱板４０、他面側放熱板５０を、接合材７０を介して接合し、その後、バンプ３０を介して半導体素子２０を基板１０の一面に接合する。このバンプ３０を介した接合は、バンプ３０の材質にもよるが、はんだ接合や超音波接合などが挙げられる。   In this manufacturing method, the one surface side heat sink 40 and the other surface side heat sink 50 are bonded to one surface and the other surface of the semiconductor element 20 via the bonding material 70, respectively, and then the semiconductor element 20 is bonded via the bump 30. Bonded to one surface of the substrate 10. The bonding via the bumps 30 may be solder bonding or ultrasonic bonding depending on the material of the bumps 30.

このとき基板１０には、切削やプレスなどの穴開け加工によって、上記貫通穴１１を予め設けておき、半導体素子２０をバンプ３０を介して基板１０に搭載するとき、半導体素子２０の一面に接続した一面側放熱板４０を、貫通穴１１の内面と隙間を有した状態で貫通穴１１に対して挿入し、基板１０の他面より突出させる。   At this time, the substrate 10 is provided with the through holes 11 in advance by drilling such as cutting or pressing, and when the semiconductor element 20 is mounted on the substrate 10 via the bumps 30, it is connected to one surface of the semiconductor element 20. The one-surface-side heat radiating plate 40 is inserted into the through-hole 11 with a gap from the inner surface of the through-hole 11 and protruded from the other surface of the substrate 10.

その後、図２に示されるように、一面側放熱板４０と貫通穴１１の内面との隙間、すなわち上記注入口１２を介して、基板１０の一面と半導体素子２０の一面との間にアンダーフィル６０を充填する。   After that, as shown in FIG. 2, an underfill is formed between one surface of the substrate 10 and one surface of the semiconductor element 20 through the gap between the one-surface side heat sink 40 and the inner surface of the through hole 11, that is, the injection port 12. 60 is filled.

具体的には、アンダーフィル６０注入用のシリンジ１のニードル１ａを注入口１２に挿入し、ニードル１ａを注入口１２内にて移動させつつアンダーフィル６０を吐出することにより、アンダーフィル６０を注入口１２から、半導体素子２０と基板１０との間に行き渡らせる。そして、充填完了後に、アンダーフィル６０を硬化させ、基板１０の他面に、はんだバンプ８０を取り付ければ、本半導体装置ができあがる。   Specifically, the underfill 60 is injected by inserting the needle 1a of the syringe 1 for injecting the underfill 60 into the injection port 12, and discharging the underfill 60 while moving the needle 1a in the injection port 12. From the entrance 12, the semiconductor element 20 and the substrate 10 are distributed. Then, after the filling is completed, the underfill 60 is cured and the solder bumps 80 are attached to the other surface of the substrate 10 to complete the semiconductor device.

ところで、本実施形態によれば、基板１０の他面から上記隙間としての注入口１２を介して一面側放熱板４０の周囲部分にアンダーフィル６０を注入できるので、従来のような半導体素子の端部から注入する場合に比べて、充填完了に必要なアンダーフィル６０の流れる距離を短くすることができ、また、一面側放熱板４０の周囲にてアンダーフィル６０が空気を巻き込むのを極力抑制できる。よって、本実施形態によれば、アンダーフィル６０内のボイド発生を極力防止することができる。   By the way, according to the present embodiment, since the underfill 60 can be injected from the other surface of the substrate 10 to the peripheral portion of the one-side heat sink 40 through the injection port 12 as the gap, the end of the conventional semiconductor element is provided. Compared with the case of injecting from the part, the distance through which the underfill 60 necessary for completion of filling can be shortened, and the underfill 60 can be restrained from entraining air around the one-side heat sink 40 as much as possible. . Therefore, according to the present embodiment, generation of voids in the underfill 60 can be prevented as much as possible.

また、本半導体装置を基板１０の他面側にて、マザーボードなどの外部の部材に対してはんだバンプ８０を介してはんだ付け実装する場合、当該はんだバンプ８０の高さの分、当該外部の部材と基板１０との間に隙間が生じるが、この場合でも、本半導体装置では、基板１０の他面より一面側放熱板４０を突出させているので、この突出部分にて一面側放熱板４０と外部の部材との接続が適切に行える。   Further, when the semiconductor device is soldered and mounted on the other surface side of the substrate 10 to an external member such as a mother board via the solder bumps 80, the external member is increased by the height of the solder bump 80. Even in this case, in this semiconductor device, since the one surface side heat radiating plate 40 protrudes from the other surface of the substrate 10, the protruding portion is connected to the one surface side heat radiating plate 40. Connection with an external member can be performed appropriately.

ここで、この一面側放熱板４０と外部の部材との接続は、典型的には、はんだ付けにより行う。こうして、半導体装置に発生した熱については、一面側放熱板４０から外部の部材へ適切に放熱が行えるようになる。   Here, the connection between the one-surface-side heat sink 40 and an external member is typically performed by soldering. Thus, the heat generated in the semiconductor device can be appropriately radiated from the one-surface-side heat radiating plate 40 to an external member.

また、上述したが、本実施形態では、一面側放熱板４０の側面を上記テーパ面４０ａとすることで、そのテーパ面４０ａと貫通穴１１の内面との隙間も基板１０の一面側から他面側に向かって広くなるようにしている。   In addition, as described above, in the present embodiment, the side surface of the one-surface-side heat radiating plate 40 is the tapered surface 40a, so that the gap between the tapered surface 40a and the inner surface of the through hole 11 is also changed from the one surface side to the other surface. It is getting wider toward the side.

そのため、上記アンダーフィル６０の充填工程において、上記ニードル１ａが挿入しやすく、また注入口１２内でのニードル１ａの移動もスムーズになる。つまり、上記注入口１２としての当該隙間にて基板１０の他面側から、アンダーフィル６０を注入しやすくなる。   Therefore, in the filling process of the underfill 60, the needle 1a is easily inserted, and the movement of the needle 1a in the injection port 12 is smooth. That is, it becomes easy to inject the underfill 60 from the other surface side of the substrate 10 in the gap as the injection port 12.

また、アンダーフィル６０の充填について、さらに述べると、上記注入口１２からのアンダーフィル６０の注入は、上記図１（ｂ）における平面矩形の一面側放熱板４０における４辺のどの辺から行ってもよい。ここで、注入方式としては、当該一面側放熱板４０における４辺について、１辺のみからの注入（いわゆる１辺塗布）、２辺のみからの注入（いわゆる２辺塗布）、３辺のみからの注入（いわゆる３辺塗布）、４辺全部からの注入（いわゆる４辺塗布）が考えられるが、本実施形態では、どの方式でもかまわない。   Further, the filling of the underfill 60 will be further described. The injection of the underfill 60 from the injection port 12 is performed from any of the four sides of the one-surface side radiator plate 40 in the plane rectangle in FIG. Also good. Here, as an injection method, about four sides in the one-surface side heat sink 40, injection from only one side (so-called one-side application), injection from only two sides (so-called two-side application), and from only three sides Injection (so-called three-side coating) and injection from all four sides (so-called four-side coating) can be considered, but any method may be used in this embodiment.

４辺塗布は１辺、２辺、３辺塗布に比べて、アンダーフィル６０を充填するためのアンダーフィル６０の移動量を少なくできるという点では、アンダーフィル６０の塗布方式としては有用である。しかし、従来のような半導体素子の端部からの充填方法では、４辺塗布を行うと空気の逃げ道が無くなり、空気を閉じ込めてしまうため適用できなかった。   The four-side coating is useful as a coating method for the underfill 60 in that the amount of movement of the underfill 60 for filling the underfill 60 can be reduced compared to the one-side, two-side, and three-side coating. However, the conventional filling method from the end of the semiconductor element cannot be applied because four-side coating eliminates air escape and traps air.

しかし、本実施形態の半導体装置あれば、基板１０の他面の注入口１２からアンダーフィル６０の注入を行っているので、たとえ４辺塗布を行ったとしても、半導体素子２０の端部側に空気の逃げ道があるため、よりボイドの少ないアンダーフィル６０の充填が可能となる。   However, in the semiconductor device of this embodiment, since the underfill 60 is injected from the injection port 12 on the other surface of the substrate 10, even if four sides are applied, the end of the semiconductor element 20 is formed. Since there is an air escape path, the underfill 60 with less voids can be filled.

なお、本実施形態では、一面側放熱板４０は、上記テーパ面４０ａを有することで、突出方向と直交する方向の断面積が部分的に異なる放熱板であったが、突出方向の断面積が全体で同一の放熱板、すなわち一面側放熱板４０はたとえば側面全体がストレートな角柱や円柱であってもよい。   In the present embodiment, the one-surface-side heat radiating plate 40 has the tapered surface 40a, so that the cross-sectional area in the direction orthogonal to the projecting direction is partially different, but the cross-sectional area in the projecting direction is different. The same heat radiating plate as a whole, that is, the one-surface-side heat radiating plate 40 may be, for example, a prism or a cylinder whose entire side surface is straight.

（第２実施形態）
図３は、本発明の第２実施形態に係る半導体装置の概略断面構成を示す図である。本実施形態は、上記第１実施形態に比べて、一面側放熱板４０を２段重ねの構成としたことが相違するものであり、ここでは、その相違点を中心に述べることとする。 (Second Embodiment)
FIG. 3 is a diagram showing a schematic cross-sectional configuration of a semiconductor device according to the second embodiment of the present invention. The present embodiment is different from the first embodiment in that the one-side heat radiating plate 40 has a two-tiered structure, and here, the difference will be mainly described.

図３に示されるように、本実施形態の半導体装置では、一面側放熱板４０は、半導体素子２０側から基板１０の他面より突出する部位側に向かって、第１の放熱板４１、第２の放熱板４２が、はんだ４３を介して重ね合わされ接合された構成よりなる。   As shown in FIG. 3, in the semiconductor device according to the present embodiment, the one-surface-side heat dissipation plate 40 has a first heat-dissipation plate 41, a first heat-dissipation plate 41, and a first heat-dissipation plate 41. The two heat radiating plates 42 are superposed and joined via the solder 43.

ここでは、貫通穴１１内部に位置する第１の放熱板４１の側面に上記同様のテーパ面４０ａが形成されており、そのテーパ面４０ａによるアンダーフィル６０の注入性向上の効果は、上記第１実施形態と同様である。また、一面側放熱板４０のうち基板１０の他面より突出する部分を構成する第２の放熱板４２は、第１の放熱板４１よりも平面サイズが小さいものとされている。   Here, a tapered surface 40a similar to the above is formed on the side surface of the first heat radiating plate 41 located inside the through hole 11, and the effect of improving the injectability of the underfill 60 by the tapered surface 40a is the above described first. This is the same as the embodiment. In addition, the second heat radiating plate 42 that constitutes a portion of the one-surface side heat radiating plate 40 that protrudes from the other surface of the substrate 10 has a smaller planar size than the first heat radiating plate 41.

このような半導体装置を製造する場合、たとえば予め第１の放熱板４１と第２の放熱板４２とをはんだ４３を介して接合・一体化して一面側放熱板４０を形成した後、これを半導体素子２０に接合すればよい。それ以外は、上記第１実施形態と同様の製造方法により、本実施形態の半導体装置が製造される。   When manufacturing such a semiconductor device, for example, the first heat radiation plate 41 and the second heat radiation plate 42 are previously joined and integrated via solder 43 to form the one-surface-side heat radiation plate 40, and then this is used as a semiconductor. What is necessary is just to join to the element 20. Other than that, the semiconductor device of this embodiment is manufactured by the same manufacturing method as that of the first embodiment.

ところで、上記第１実施形態の半導体装置では、一面側放熱板４０は単一の部材より構成されていた。そのため、同半導体装置を基板１０の他面側にて、外部の部材に対してはんだバンプ８０を介してはんだ付けする場合において、一面側放熱板４０を外部の部材にはんだ付けするとき、一面側放熱板４０やはんだバンプ８０の較差やはんだバンプ８０の潰れ具合によって、一面側放熱板４０が高すぎて、つっかえ棒のようになり、はんだバンプ８０の接合ができなかったり、低すぎて一面側放熱板４０を外部の部材にはんだ付け出来なかったりなどの不具合が発生する恐れがある。   By the way, in the semiconductor device of the said 1st Embodiment, the one surface side heat sink 40 was comprised from the single member. Therefore, in the case where the semiconductor device is soldered to the external member on the other surface side of the substrate 10 via the solder bumps 80, when the one-surface side heat sink 40 is soldered to the external member, the one-surface side Due to the difference between the heat sink 40 and the solder bump 80 or the collapse of the solder bump 80, the one side heat sink 40 becomes too high and becomes like a stick, and the solder bump 80 cannot be joined, or it is too low and one side There is a risk that problems such as failure to solder the heat sink 40 to an external member may occur.

このような不具合に対しては、はんだバンプ８０の高さ、一面側放熱板４０の高さ、接合材７０の厚み等を管理していけば、回避されるが、高精度な寸法管理が必要となってくる。   Such problems can be avoided by managing the height of the solder bumps 80, the height of the one-side heat sink 40, the thickness of the bonding material 70, etc., but highly accurate dimensional management is required. It becomes.

それに対して、本実施形態によれば、一面側放熱板４０を上記はんだ４３を介した２段重ねの構成としているので、一面側放熱板４０の突出先端部を外部の部材に、はんだ付けするときに、第１の放熱板４１と第２の放熱板４２との間のはんだ４３が、当該はんだ付け時のリフローの熱によって溶融もしくは軟化して変形するので、一面側放熱板４０全体の高さが調整される。   On the other hand, according to the present embodiment, the one-surface-side heat radiating plate 40 is configured in a two-layered manner with the solder 43 interposed therebetween, so that the protruding tip portion of the one-surface-side heat radiating plate 40 is soldered to an external member. Sometimes, the solder 43 between the first heat radiating plate 41 and the second heat radiating plate 42 is deformed by melting or softening due to the heat of reflow at the time of soldering. Is adjusted.

つまり、本実施形態によれば、本半導体装置を基板１０の他面側にて、マザーボードなどの外部の部材に対してはんだバンプ８０を介して実装する場合において、基板１０の他面より突出する一面側放熱板４０を当該外部の部材にはんだ付けするとき、上記した高精度な寸法管理を行うことなく、当該はんだ付けを適切に行える。   That is, according to the present embodiment, when the semiconductor device is mounted on the other surface side of the substrate 10 to an external member such as a mother board via the solder bumps 80, the semiconductor device protrudes from the other surface of the substrate 10. When soldering the one-surface-side heat radiating plate 40 to the external member, the soldering can be appropriately performed without performing the above-described highly accurate dimensional management.

（第３実施形態）
図４は、本発明の第３実施形態に係る半導体装置の概略断面構成を示す図である。本実施形態は、上記第３実施形態において、一面側放熱板４０における両放熱板４１、４２の間のはんだ４３の構成を変形したところが相違するものであり、ここでは、その相違点を中心に述べることとする。 (Third embodiment)
FIG. 4 is a diagram showing a schematic cross-sectional configuration of a semiconductor device according to the third embodiment of the present invention. The present embodiment is different from the third embodiment in that the configuration of the solder 43 between the heat radiating plates 41, 42 in the one-surface-side heat radiating plate 40 is modified. Here, the difference is mainly described. Let's say.

上記第２実施形態では、一面側放熱板４０における両放熱板４１、４２の間のはんだ４３によって、上述したように、一面側放熱板４０の高さ調整を行ったが、その高さの調節幅は、当該はんだ４３の量で決まる。このはんだ４３の量が多いほど、高さの調整能力は高いが、多すぎると、当該はんだ４３がはみ出してブリッジ等の不良が発生する恐れがある。そこで、本実施形態では、当該高さ調節幅が大きい場合に好適なはんだ４３の構成を提供する。   In the second embodiment, as described above, the height adjustment of the one-surface-side heat radiating plate 40 is performed by the solder 43 between the two heat-radiating plates 41, 42 in the one-surface-side heat radiating plate 40. The width is determined by the amount of the solder 43. As the amount of the solder 43 is increased, the height adjustment capability is higher. However, if the amount is too large, the solder 43 may protrude and a defect such as a bridge may occur. Therefore, in the present embodiment, a configuration of the solder 43 that is suitable when the height adjustment width is large is provided.

図４に示されるように、本半導体装置では、一面側放熱板４０のうち基板１０の他面より突出する部分を構成する第２の放熱板４２は、半導体素子２０側の第１の放熱板４１よりも平面サイズが小さいものとされている。   As shown in FIG. 4, in the present semiconductor device, the second heat radiating plate 42 that constitutes a portion of the one-surface-side heat radiating plate 40 that protrudes from the other surface of the substrate 10 is the first heat radiating plate on the semiconductor element 20 side. The plane size is smaller than 41.

そして、この一面側放熱板４０において両放熱板４１、４２の間のはんだ４３は、互いに離間して配置された複数個のはんだボール４３ａにより構成されたものである。それによれば、当該両放熱板４１、４２の間に単一層のはんだ４３を介在させる上記第２実施形態に比べて、個々のはんだボール４３ａが大きく熱変形することが可能なため、上記高さ調節幅も大きくなる。   The solder 43 between the heat radiating plates 41 and 42 in the one-surface side heat radiating plate 40 is constituted by a plurality of solder balls 43a that are spaced apart from each other. According to this, since the individual solder balls 43a can be largely thermally deformed as compared with the second embodiment in which the single layer solder 43 is interposed between the heat radiating plates 41 and 42, the height is increased. The adjustment range is also increased.

また、このようなはんだボール４３ａを配置するためには、通常のＣｕ等よりなる放熱板４１、４２では、はんだボール４３ａがリフロー時に濡れ広がってしまい、その高さを維持することができなくなる。   Further, in order to dispose such solder balls 43a, in the heat sinks 41 and 42 made of ordinary Cu or the like, the solder balls 43a spread out during reflow, and the height cannot be maintained.

そこで、本実施形態では、第１の放熱板４１および第２の放熱板４２ともに、はんだボール４３ａと接触する面に、はんだボール４３ａの溶融時に個々のはんだボール４３ａの位置を規定するための領域を設けている。以下、この領域を、はんだボール位置規定領域ということとする。   Therefore, in the present embodiment, both the first heat radiating plate 41 and the second heat radiating plate 42 are regions for defining the positions of the individual solder balls 43a on the surface in contact with the solder balls 43a when the solder balls 43a are melted. Is provided. Hereinafter, this region is referred to as a solder ball position defining region.

具体的には、このはんだボール位置規定領域は、はんだボール４３ａの溶融時に溶融したはんだボール４３ａのセルフアライメントにより、はんだボール４３ａ自身の位置を規定する領域である。   Specifically, this solder ball position defining region is a region that defines the position of the solder ball 43a itself by self-alignment of the solder ball 43a melted when the solder ball 43a is melted.

本実施形態では、各放熱板４１、４２におけるはんだボール４３ａとの接触面には、当該接触面のうちはんだボール４３ａが位置する領域以外の領域に、レジスト４４が設けられ、このレジスト４４が設けられていない領域が、はんだボール４３ａの位置を規定するための領域として構成されている。   In the present embodiment, a resist 44 is provided on a contact surface of each heat radiating plate 41, 42 with the solder ball 43 a in a region other than the region where the solder ball 43 a is located on the contact surface. The area not formed is configured as an area for defining the position of the solder ball 43a.

このレジスト４４は、たとえばフォトリソグラフ法などにより形成された感光性のポリイミドやポリアクリルなどの樹脂よりなる膜であり、放熱板４１、４２を構成するＣｕなどの金属よりもはんだ濡れ性の小さいものである。つまり、このレジスト４４で囲まれているはんだボール位置規定領域は、当該領域の周囲のレジスト領域よりも、はんだ濡れ性の大きい領域として構成されている。   The resist 44 is a film made of a resin such as photosensitive polyimide or polyacryl formed by, for example, a photolithographic method, and has a lower solder wettability than a metal such as Cu constituting the heat sinks 41 and 42. It is. That is, the solder ball position defining region surrounded by the resist 44 is configured as a region having higher solder wettability than the resist region around the region.

これにより、はんだボール４３ａの溶融時に、溶融したはんだボール４３ａの表面張力が作用して、はんだボール４３ａが狙いの位置、つまり、当該はんだボール位置規定領域に収まるのである。こうして、複数個のはんだボール４３ａのそれぞれが、その溶融時に適切に位置決めされるのである。   Thereby, when the solder ball 43a is melted, the surface tension of the melted solder ball 43a acts, so that the solder ball 43a fits in the target position, that is, the solder ball position defining region. In this way, each of the plurality of solder balls 43a is appropriately positioned at the time of melting.

具体的に、本実施形態の半導体装置を製造する場合、一面側放熱板４０となる両放熱板４１、４２のはんだボール４３ａと接する面に、上記レジスト４４によりはんだボール位置規定領域を形成し、その後、両放熱板４１、４２のうちいずれか一方の放熱板における当該領域にはんだボール４３ａを配置し、その後、はんだボール４３ａを介して、当該両放熱板４１、４２を接合すればよい。このときに、上記セルフアライメントによるはんだボール４３ａの位置決めが行われる。   Specifically, when manufacturing the semiconductor device according to the present embodiment, the solder ball position defining region is formed by the resist 44 on the surface of the heat radiating plates 41 and 42 to be the one surface side heat radiating plate 40 in contact with the solder balls 43a. Thereafter, the solder balls 43a may be disposed in the region of either one of the heat sinks 41 and 42, and then both the heat sinks 41 and 42 may be joined via the solder balls 43a. At this time, the solder balls 43a are positioned by the self-alignment.

（第４実施形態）
図５は、本発明の第４実施形態に係る半導体装置の概略断面構成を示す図である。本実施形態は、上記第２実施形態と同様に、一面側放熱板４０を、第１の放熱板４１、第２の放熱板４２が、はんだ４３を介して重ね合わされ接合された２段重ねの構成としたものであるが、さらに、一面側放熱板４０について一部変形したところが相違するものである。以下、この相違点を中心に述べる。 (Fourth embodiment)
FIG. 5 is a diagram showing a schematic cross-sectional configuration of a semiconductor device according to the fourth embodiment of the present invention. In the present embodiment, similar to the second embodiment, the one-surface side heat radiating plate 40 is overlapped with the first heat radiating plate 41 and the second heat radiating plate 42 via the solder 43 and joined. Although it is set as a structure, the place which partially deformed about the one surface side heat sink 40 is different. Hereinafter, this difference will be mainly described.

図５に示されるように、一面側放熱板４０においては、第１の放熱板４１と第２の放熱板４２とでは、その平面サイズが異なるものとしている。ここでは、一面側放熱板４０は、半導体素子２０側の第１の放熱板４１が平面サイズが小さく、半導体素子２０とは反対側の第２の放熱板４２が平面サイズが大きいものとしている。   As shown in FIG. 5, in the one-side heat radiating plate 40, the first heat radiating plate 41 and the second heat radiating plate 42 have different plane sizes. Here, in the one-surface side heat sink 40, the first heat sink 41 on the semiconductor element 20 side has a small planar size, and the second heat sink 42 on the opposite side to the semiconductor element 20 has a large planar size.

この場合、一面側放熱板４０のうち基板１０の他面より突出し外部の部材と接合される部位である第２の放熱板４２が大きいので、外部の部材との接合面積を大きくして放熱性を向上させるという面で効果的である。   In this case, since the second heat radiating plate 42 that protrudes from the other surface of the substrate 10 and is joined to an external member is large in the one-surface side heat radiating plate 40, the area of joint with the external member is increased to increase heat dissipation. It is effective in terms of improving

そして、これら第１および第２の両放熱板４１、４２のうち平面サイズの大きい方である第２の放熱板４２におけるはんだ４３と接触する面には、はんだ４３の溶融時に溶融したはんだ４３を介して第２の放熱板４２に対して、平面サイズの小さい方の第１の放熱板４１の位置を規定するための領域が設けられている。以下、この領域を放熱板位置規定領域ということとする。   And the solder 43 which melted at the time of melting of the solder 43 is applied to the surface of the second heat radiating plate 42 which is the larger one of the first and second heat radiating plates 41, 42 in contact with the solder 43. A region for defining the position of the first heat radiating plate 41 having a smaller planar size is provided with respect to the second heat radiating plate 42. Hereinafter, this region is referred to as a heat sink position defining region.

具体的には、この放熱板位置規定領域は、はんだ４３の溶融時に溶融したはんだ４３のセルフアライメントにより、両放熱板４１、４２の相対位置を規定する領域である。本実施形態では、平面サイズの大きい方の第２の放熱板４２におけるはんだ４３との接触面には、当該接触面のうちはんだ４３が位置する領域以外の領域に、レジスト４４が設けられており、このレジスト４４が設けられていない領域が、放熱板位置規定領域として構成されている。   Specifically, this heat sink position defining region is a region that defines the relative positions of both heat sinks 41 and 42 by self-alignment of the solder 43 melted when the solder 43 is melted. In the present embodiment, a resist 44 is provided on the contact surface with the solder 43 in the second heat radiating plate 42 having a larger planar size in a region other than the region where the solder 43 is located on the contact surface. The region where the resist 44 is not provided is configured as a heat sink position defining region.

このレジスト４４は、たとえば上記図４のレジスト４４と同様の材質のものであり、当該放熱板位置規定領域は、当該領域の周囲のレジスト領域よりも、はんだ濡れ性の大きい領域として構成されている。そして、はんだ４３の溶融時に、溶融したはんだ４３の表面張力が作用して、はんだ４３を介して第１の放熱板４１が狙いの位置、つまり、当該放熱板位置規定領域に収まるのである。   The resist 44 is made of, for example, the same material as the resist 44 shown in FIG. 4, and the heat sink position defining region is configured as a region having higher solder wettability than the resist region around the region. . When the solder 43 is melted, the surface tension of the melted solder 43 acts, and the first heat radiating plate 41 falls within the target position, that is, the heat radiating plate position defining region via the solder 43.

また、本実施形態の場合、平面サイズが小さく半導体素子２０側に位置する第１の放熱板４１と貫通穴１１との隙間がアンダーフィルを注入するための注入口１２として構成されている。   In the case of the present embodiment, the gap between the first heat radiating plate 41 and the through hole 11 having a small planar size and located on the semiconductor element 20 side is configured as an inlet 12 for injecting underfill.

そして、この場合、第１の放熱板４１を半導体素子２０の一面に接合した状態で、第１の放熱板４１を基板１０の貫通穴１１に挿入しつつ、半導体素子２０を基板１０の一面に搭載、接合した後、その状態で、第１の放熱板４１と貫通穴１１の内面との隙間からアンダーフィル６０を注入することで、アンダーフィル６０の充填を行う。   In this case, the semiconductor element 20 is placed on one surface of the substrate 10 while the first heat sink 41 is inserted into the through hole 11 of the substrate 10 in a state where the first heat sink 41 is bonded to the one surface of the semiconductor element 20. After mounting and joining, the underfill 60 is filled by injecting the underfill 60 from the gap between the first heat radiation plate 41 and the inner surface of the through hole 11 in that state.

そして、当該充填完了後に、第１の放熱板４１に対して第２の放熱板４２をはんだ４３を介して接合する。このとき、上記した放熱板位置規定領域を設けているから、はんだ４３の溶融時にて溶融したはんだ４３のセルフアライメントにより、平面サイズの異なる両放熱板４１、４２が、適切に位置決めされる。   Then, after the filling is completed, the second heat radiating plate 42 is joined to the first heat radiating plate 41 via the solder 43. At this time, since the heat radiating plate position defining region is provided, both the heat radiating plates 41 and 42 having different plane sizes are appropriately positioned by self-alignment of the molten solder 43 when the solder 43 is melted.

なお、本実施形態では、第１の放熱板４１と第２の放熱板４２とをはんだ接合した後であっても、上記注入口１２からアンダーフィル６０を充填できるのであれば、当該充填を両放熱板４１、４２のはんだ接合の後に行ってもよい。   In this embodiment, even if the first heat radiating plate 41 and the second heat radiating plate 42 are solder-bonded, if the underfill 60 can be filled from the inlet 12, the filling is performed on both sides. You may carry out after soldering of the heat sinks 41 and 42.

また、図５の例では、一面側放熱板４０は、半導体素子２０側の第１の放熱板４１が平面サイズが小さく、半導体素子２０とは反対側の第２の放熱板４２が平面サイズが大きいものであったが、これとは逆に、第１の放熱板４１の方が平面サイズが大きく、第１の放熱板４１におけるはんだ４３との接触面に、レジスト４４を設けてもよい。このようにして、第１の放熱板４１に対し第２の放熱板４２の位置を規定するための領域を、第１の放熱板４１に形成してもよい。   Further, in the example of FIG. 5, the one-side heat radiating plate 40 has the first heat radiating plate 41 on the semiconductor element 20 side having a small planar size, and the second heat radiating plate 42 on the side opposite to the semiconductor element 20 has a planar size. On the contrary, the first heat radiating plate 41 has a larger planar size, and a resist 44 may be provided on the contact surface of the first heat radiating plate 41 with the solder 43. In this manner, an area for defining the position of the second heat radiating plate 42 with respect to the first heat radiating plate 41 may be formed in the first heat radiating plate 41.

（第５実施形態）
図６は、本発明の第５実施形態に係る半導体装置の概略断面構成を示す図である。本実施形態は、上記第４実施形態の変形であって、上記第４実施形態において、さらに、一面側放熱板４０における両放熱板４１、４２の間のはんだ４３を、互いに離間して配置された複数個のはんだボール４３ａにより構成したものである。 (Fifth embodiment)
FIG. 6 is a diagram showing a schematic cross-sectional configuration of a semiconductor device according to the fifth embodiment of the present invention. The present embodiment is a modification of the fourth embodiment. In the fourth embodiment, the solder 43 between the heat radiation plates 41 and 42 in the one-surface-side heat radiation plate 40 is further spaced apart from each other. The plurality of solder balls 43a.

それによれば、上記第３実施形態と同様に、はんだボール４３ａの熱変形による上記高さ調節幅の増大が図れる。また、これも上記第３実施形態と同様に、第１の放熱板４１および第２の放熱板４２ともに、レジスト４４によって上記はんだボール位置規定領域を形成しており、それにより、はんだボール４３ａの適切な位置決めが成される。   According to this, as in the third embodiment, the height adjustment width can be increased by thermal deformation of the solder balls 43a. Also, as in the third embodiment, both the first heat radiating plate 41 and the second heat radiating plate 42 form the solder ball position defining region by the resist 44, whereby the solder balls 43a Proper positioning is achieved.

（第６実施形態）
図７は、本発明の第６実施形態に係る半導体装置の概略断面構成を示す図である。この図７に示される本半導体装置は、上記図１に示した半導体装置における基板１０の貫通穴１１の構成を変形したものであり、ここでは、この変形部分を中心に述べる。 (Sixth embodiment)
FIG. 7 is a diagram showing a schematic cross-sectional configuration of a semiconductor device according to the sixth embodiment of the present invention. The semiconductor device shown in FIG. 7 is obtained by modifying the configuration of the through hole 11 of the substrate 10 in the semiconductor device shown in FIG. 1, and here, this deformed portion will be mainly described.

図７に示されるように、本半導体装置においては、基板１０の他面における貫通穴１１の開口部にて、その穴１１の角部を面取りしてテーパ面１０ａを形成したものである。この貫通穴１１の開口部のテーパ面１０ａによって、貫通穴１１の開口サイズは基板１０の一面側から他面側へ拡がっている。そのため、このテーパ面１０ａを設けることで、その分、注入口１２が広くなり、アンダーフィル６０の注入が、さらに行いやすくなる。   As shown in FIG. 7, in this semiconductor device, a tapered surface 10 a is formed by chamfering a corner of the hole 11 at the opening of the through hole 11 on the other surface of the substrate 10. Due to the tapered surface 10 a of the opening of the through hole 11, the opening size of the through hole 11 is expanded from one surface side to the other surface side of the substrate 10. Therefore, by providing this tapered surface 10a, the injection port 12 becomes wider correspondingly, and the underfill 60 can be more easily injected.

なお、本実施形態は、基板１０の他面における貫通穴１１の開口部にテーパ面１０ａを設けるものであり、上記図１に示した半導体装置以外にも、上記各実施形態の半導体装置に組み合わせて適用することが可能である。   In the present embodiment, a tapered surface 10a is provided at the opening of the through hole 11 on the other surface of the substrate 10, and in addition to the semiconductor device shown in FIG. 1, the semiconductor device of each of the above embodiments is combined. It is possible to apply.

（第７実施形態）
図８は、本発明の第６実施形態に係る半導体装置の概略平面構成を示す図である。本実施形態の半導体装置における基板の他面側の平面構成を示している。 (Seventh embodiment)
FIG. 8 is a diagram showing a schematic plan configuration of a semiconductor device according to the sixth embodiment of the present invention. 3 shows a planar configuration of the other side of the substrate in the semiconductor device of the present embodiment.

図８に示されるように、本半導体装置では、一面側放熱板４０において半導体素子２０の一面から突出する方向に沿って延びる面、すなわち一面側放熱板４０の側面に凹凸を設けたものである。この凹凸は、図８の如く、当該突出する方向とは直交する方向に凹と凸が繰り返されている形状である。   As shown in FIG. 8, in this semiconductor device, the surface of the one-side heat radiating plate 40 that extends along the direction protruding from one surface of the semiconductor element 20, that is, the side surface of the one-side heat radiating plate 40 is provided with irregularities. . As shown in FIG. 8, the unevenness has a shape in which concaves and convexes are repeated in a direction orthogonal to the protruding direction.

この側面の凹凸により、貫通穴１１の内面と一面側放熱板４０の側面との隙間が、特に凹部にて大きくなるので、そこから空気が逃げやすくなり、アンダーフィルの注入性が向上する。また、一面側放熱板４０をマザーボードなどの外部の部材に対して、はんだ付けするとき、この凹凸を付けた分、一面側放熱板４０と外部の部材との当該はんだを介した接触面積が増加するため、それによる放熱性の向上が期待できる。   Due to the unevenness on the side surface, the gap between the inner surface of the through hole 11 and the side surface of the one-side heat dissipation plate 40 is increased particularly in the concave portion, so that air easily escapes from there and the underfill injection property is improved. Further, when soldering the one-surface side heat sink 40 to an external member such as a mother board, the contact area between the one-surface side heat sink 40 and the external member through the solder is increased by the amount of the unevenness. Therefore, improvement of heat dissipation can be expected.

そして、このような一面側放熱板４０の側面に凹凸を設けることは、上記各実施形態の半導体装置において、組み合わせて適用することができる。   And providing such unevenness on the side surface of the one-surface side radiator plate 40 can be applied in combination in the semiconductor device of each of the above embodiments.

（他の実施形態）
なお、上記各実施形態のうち２段重ね構成の一面側放熱板４０において、第１の放熱板４１と第２の放熱板４２とを異種材料より構成してもよい。この場合、具体的には、第２の放熱板４２をＣｕで構成した場合、半導体素子２０と第２の放熱板４２との間の第１の放熱板４１を、半導体素子２０を構成するＳｉと第２の放熱板４２を構成するＣｕとの間の線膨張係数を有する材料により構成する。それによれば、冷熱サイクルなどで発生する応力を緩和し、信頼性の向上が期待される。 (Other embodiments)
In the above-described embodiments, the first heat radiating plate 41 and the second heat radiating plate 42 may be made of different materials in the one-surface heat radiating plate 40 having a two-tiered structure. In this case, specifically, when the second heat radiation plate 42 is made of Cu, the first heat radiation plate 41 between the semiconductor element 20 and the second heat radiation plate 42 is replaced with Si constituting the semiconductor element 20. And a material having a linear expansion coefficient between Cu and the second heat radiation plate 42. According to this, it is expected that the stress generated by the cooling cycle etc. is relaxed and the reliability is improved.

また、上記各実施形態では、半導体素子２０の基板１０に対向する一面に接続された一面側放熱板４０、半導体素子２０の一面とは反対側の他面に接続された他面側放熱板５０を備える構成、つまり、半導体素子２０の両面に放熱板４０、５０を設けた構成としたが、上記各実施形態において、一面側放熱板４０のみ設けられ、他面側放熱板は省略された構成であってもよい。   Moreover, in each said embodiment, the one surface side heat sink 40 connected to the one surface facing the board | substrate 10 of the semiconductor element 20 and the other surface side heat sink 50 connected to the other surface on the opposite side to the one surface of the semiconductor element 20. In other words, in the above-described embodiments, only the one-surface-side heat dissipation plate 40 is provided, and the other-surface-side heat dissipation plate is omitted. It may be.

１０ 基板
１１ 貫通穴
１２ 注入口
２０ 半導体素子
３０ バンプ
４０ 一面側放熱板
４０ａ テーパ面
４１ 一面側放熱板の第１の放熱板
４２ 一面側放熱板の第２の放熱板
４３ 一面側放熱板のはんだ
４３ａ はんだボール
６０ アンダーフィル DESCRIPTION OF SYMBOLS 10 Board | substrate 11 Through-hole 12 Inlet 20 Semiconductor element 30 Bump 40 One surface side heat sink 40a Tapered surface 41 1st heat sink of one surface side heat sink 42 Second heat sink of one surface side heat sink 43 Solder of one surface side heat sink 43a Solder ball 60 Underfill

Claims (4)

基板（１０）と、
一面をバンプ（３０）を介して前記基板（１０）の一面に対向させた状態で前記基板（１０）の一面上に搭載された半導体素子（２０）と、
前記半導体素子（２０）の一面のうち前記バンプ（３０）以外の部位に接続された放熱板（４０）と、
前記半導体素子（２０）の一面と前記基板（１０）の一面との間にて、前記バンプ（３０）および前記放熱板（４０）以外の部位に充填されたアンダーフィル（６０）とを備える半導体装置において、
前記基板（１０）には前記基板（１０）の一面から他面へ貫通し、前記放熱板（４０）よりも大きな貫通穴（１１）が設けられており、
前記放熱板（４０）は前記貫通穴（１１）に対して前記貫通穴（１１）の内面と隙間を有した状態で挿入されるとともに、前記基板（１０）の他面より突出しており、
前記放熱板（４０）と前記貫通穴（１１）の内面との隙間は、前記アンダーフィル（６０）が注入される注入口（１２）として構成され、この注入口（１２）を介して、前記基板（１０）の一面と前記半導体素子（２０）の一面との間に前記アンダーフィル（６０）が充填されており、
前記放熱板（４０）のうち前記貫通穴（１１）内に位置する部位の側面は、前記基板（１０）の一面側から他面側へ拡がるテーパ面（４０ａ）とされており、当該側面と前記貫通穴（１１）の内面との隙間は前記基板（１０）の一面側から他面側へ向かって広くなっていることを特徴とする半導体装置。 A substrate (10);
A semiconductor element (20) mounted on one surface of the substrate (10) with one surface opposed to one surface of the substrate (10) via a bump (30);
A heat sink (40) connected to a portion of the one surface of the semiconductor element (20) other than the bump (30);
A semiconductor comprising an underfill (60) filled in a portion other than the bump (30) and the heat sink (40) between one surface of the semiconductor element (20) and one surface of the substrate (10). In the device
The substrate (10) penetrates from one surface of the substrate (10) to the other surface, and has a through hole (11) larger than the heat sink (40),
The heat sink (40) is inserted into the through hole (11) in a state having a gap with the inner surface of the through hole (11), and protrudes from the other surface of the substrate (10),
A gap between the heat radiating plate (40) and the inner surface of the through hole (11) is configured as an inlet (12) into which the underfill (60) is injected, and through the inlet (12), the gap The underfill (60) is filled between one surface of the substrate (10) and one surface of the semiconductor element (20) ,
The side surface of the part located in the through hole (11) of the heat radiating plate (40) is a tapered surface (40a) extending from the one surface side to the other surface side of the substrate (10). A gap between the through hole (11) and the inner surface widens from one side of the substrate (10) toward the other side . 基板（１０）と、
一面をバンプ（３０）を介して前記基板（１０）の一面に対向させた状態で前記基板（１０）の一面上に搭載された半導体素子（２０）と、
前記半導体素子（２０）の一面のうち前記バンプ（３０）以外の部位に接続された放熱板（４０）と、
前記半導体素子（２０）の一面と前記基板（１０）の一面との間にて前記バンプ（３０）および前記放熱板（４０）以外の部位に充填されたアンダーフィル（６０）とを備える半導体装置において、
前記基板（１０）には前記基板（１０）の一面から他面へ貫通し、前記一面側放熱板（４０）よりも大きな貫通穴（１１）が設けられており、
前記放熱板（４０）は前記貫通穴（１１）に対して前記貫通穴（１１）の内面と隙間を有した状態で挿入されるとともに、前記基板（１０）の他面より突出しており、
前記放熱板（４０）と前記貫通穴（１１）の内面との隙間は、前記アンダーフィル（６０）が注入される注入口（１２）として構成され、この注入口（１２）を介して、前記基板（１０）の一面と前記半導体素子（２０）の一面との間にアンダーフィル（６０）が充填されており、
前記放熱板（４０）は、前記半導体素子（２０）側から第１の放熱板（４１）、第２の放熱板（４２）が、はんだ（４３）を介して重ね合わされた構成よりなり、
前記放熱板（４０）において前記第１の放熱板（４１）と前記第２の放熱板（４２）との間の前記はんだ（４３）は、互いに離間して配置された複数個のはんだボール（４３ａ）よりなることを特徴とする半導体装置。 A substrate (10);
A semiconductor element (20) mounted on one surface of the substrate (10) with one surface opposed to one surface of the substrate (10) via a bump (30);
A heat sink (40) connected to a portion of the one surface of the semiconductor element (20) other than the bump (30);
A semiconductor device comprising an underfill (60) filled in a portion other than the bump (30) and the heat sink (40) between one surface of the semiconductor element (20) and one surface of the substrate (10). In
The substrate (10) is provided with a through hole (11) that penetrates from one surface of the substrate (10) to the other surface and is larger than the one-surface-side heat sink (40),
The heat sink (40) is inserted into the through hole (11) in a state having a gap with the inner surface of the through hole (11), and protrudes from the other surface of the substrate (10),
A gap between the heat radiating plate (40) and the inner surface of the through hole (11) is configured as an inlet (12) into which the underfill (60) is injected, and through the inlet (12), the gap An underfill (60) is filled between one surface of the substrate (10) and one surface of the semiconductor element (20),
Said radiating plate (40), said first radiator plate from the semiconductor element (20) side (41), a second heat radiating plate (42) is Ri Na from structure superimposed via a solder (43),
In the heat radiating plate (40), the solder (43) between the first heat radiating plate (41) and the second heat radiating plate (42) is a plurality of solder balls ( 43a) . A semiconductor device comprising: 前記第１の放熱板（４１）および前記第２の放熱板（４２）ともに、前記はんだボール（４３ａ）と接触する面には、前記はんだボール（４３ａ）の溶融時に個々の前記はんだボール（４３ａ）の位置を規定するための領域が設けられていることを特徴とする請求項２に記載の半導体装置。 Both the first heat radiating plate (41) and the second heat radiating plate (42) are in contact with the solder balls (43a) on the surfaces of the individual solder balls (43a) when the solder balls (43a) are melted. 3. The semiconductor device according to claim 2 , further comprising a region for defining a position of (). 基板（１０）と、
一面をバンプ（３０）を介して前記基板（１０）の一面に対向させた状態で前記基板（１０）の一面上に搭載された半導体素子（２０）と、
前記半導体素子（２０）の一面のうち前記バンプ（３０）以外の部位に接続された放熱板（４０）と、
前記半導体素子（２０）の一面と前記基板（１０）の一面との間にて前記バンプ（３０）および前記放熱板（４０）以外の部位に充填されたアンダーフィル（６０）とを備える半導体装置において、
前記基板（１０）には前記基板（１０）の一面から他面へ貫通し、前記一面側放熱板（４０）よりも大きな貫通穴（１１）が設けられており、
前記放熱板（４０）は前記貫通穴（１１）に対して前記貫通穴（１１）の内面と隙間を有した状態で挿入されるとともに、前記基板（１０）の他面より突出しており、
前記放熱板（４０）と前記貫通穴（１１）の内面との隙間は、前記アンダーフィル（６０）が注入される注入口（１２）として構成され、この注入口（１２）を介して、前記基板（１０）の一面と前記半導体素子（２０）の一面との間にアンダーフィル（６０）が充填されており、
前記放熱板（４０）は、前記半導体素子（２０）側から第１の放熱板（４１）、第２の放熱板（４２）が、はんだ（４３）を介して重ね合わされた構成よりなり、
前記第１の放熱板（４１）と前記第２の放熱板（４２）とでは、その平面サイズが異なるものであり、
当該両放熱板（４１、４２）のうち平面サイズの大きい方における前記はんだ（４３）と接触する面には、前記はんだ（４３）の溶融時に溶融した前記はんだ（４３）を介して当該平面サイズの大きい方に対し平面サイズの小さい方の位置を規定するための領域が設けられていることを特徴とする半導体装置。 A substrate (10);
A semiconductor element (20) mounted on one surface of the substrate (10) with one surface opposed to one surface of the substrate (10) via a bump (30);
A heat sink (40) connected to a portion of the one surface of the semiconductor element (20) other than the bump (30);
A semiconductor device comprising an underfill (60) filled in a portion other than the bump (30) and the heat sink (40) between one surface of the semiconductor element (20) and one surface of the substrate (10). In
The substrate (10) is provided with a through hole (11) that penetrates from one surface of the substrate (10) to the other surface and is larger than the one-surface-side heat sink (40),
The heat sink (40) is inserted into the through hole (11) in a state having a gap with the inner surface of the through hole (11), and protrudes from the other surface of the substrate (10),
A gap between the heat radiating plate (40) and the inner surface of the through hole (11) is configured as an inlet (12) into which the underfill (60) is injected, and through the inlet (12), the gap An underfill (60) is filled between one surface of the substrate (10) and one surface of the semiconductor element (20),
The heat radiating plate (40) has a configuration in which a first heat radiating plate (41) and a second heat radiating plate (42) are overlapped via a solder (43) from the semiconductor element (20) side.
The first heat radiating plate (41) and the second heat radiating plate (42) have different plane sizes,
Of the heat radiating plates (41, 42), the surface in contact with the solder (43) on the larger planar size is connected to the planar size via the solder (43) melted when the solder (43) is melted. semi conductor arrangement you characterized in that the region for defining the position of the smaller plane size is provided to the larger.
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