JP2010267792A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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JP2010267792A
JP2010267792A JP2009117728A JP2009117728A JP2010267792A JP 2010267792 A JP2010267792 A JP 2010267792A JP 2009117728 A JP2009117728 A JP 2009117728A JP 2009117728 A JP2009117728 A JP 2009117728A JP 2010267792 A JP2010267792 A JP 2010267792A
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electrode pad
connection terminal
semiconductor device
mounting target
main body
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Yosuke Kondo
洋介 近藤
Kazuhiro Yamaguchi
和宏 山口
Jihei Takano
自平 高野
Jun Mitani
潤 見谷
Seishi Nakano
聖之 中野
Kazunori Ishida
和範 石田
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15182Fan-in arrangement of the internal vias
    • H01L2924/15184Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing crack formation caused by heat stress, and a manufacturing method for the semiconductor device. <P>SOLUTION: According to the semiconductor device 1, a subject to be mounted 2 is mounted on a mounted subject 3 via a plurality of arrayed or randomly arranged connection terminals 41. The semiconductor device 1 includes a means that forms a plurality of electrode pads 43a and 43b on the mounted subject 3, and a means that melts and solidifies the connection terminals 41 on the electrode pads 43a and 43b to join the connection terminals 41 to the mounted subject 3. Some electrode pads 43a each have a body 431 that regulates the solidified shape of the connection terminal 41, and a guide portion 432 that guides part of the connection terminal 41 to the outer periphery of the body 431 when the connection terminal 41 melts. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は、半導体装置およびその製造方法に関し、さらに詳しくは、熱応力によるクラックの発生を抑制できる半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device capable of suppressing the occurrence of cracks due to thermal stress and a manufacturing method thereof.

近年の半導体装置では、電子部品あるいは回路基板を配線基板に実装する構造として、BGA(Ball Grid Array)接続構造が採用されている。BGA接続構造は、アレイ状あるいはランダム状に配列された複数の接続端子を介して被実装対象を実装対象に実装する構造である。かかるBGA接続構造では、複数の接続端子がアレイ状あるいはランダム状に配列されるので、パッケージの小型化や電子部品類の高密度実装が可能となる。これにより、電子機器の小型化が実現される。また、BGA接続構造は、リードレス構造を有するので、被実装対象と実装対象との接続距離が短縮される。これにより、電子機器の信号処理速度が向上する。   In recent semiconductor devices, a BGA (Ball Grid Array) connection structure is adopted as a structure for mounting an electronic component or a circuit board on a wiring board. The BGA connection structure is a structure in which a mounting target is mounted on a mounting target via a plurality of connection terminals arranged in an array or at random. In such a BGA connection structure, since a plurality of connection terminals are arranged in an array or in a random manner, the package can be downsized and electronic components can be mounted at high density. Thereby, size reduction of an electronic device is implement | achieved. In addition, since the BGA connection structure has a leadless structure, the connection distance between the mounting target and the mounting target is shortened. This improves the signal processing speed of the electronic device.

ここで、例えば、セラミック材を導電性配線材とともに積層・焼成して多層化したセラミック基板からなるBGA型セラミック回路モジュールでは、配線基板への実装状態にて、BGA接続部の電極パッドの外周部に熱応力が集中して、電極パッド周囲のセラミック基板にクラックが発生する場合があった。そこで、電極パッドの外周部をガラス保護膜で覆うことにより、クラックが生じ難い端子構造を提供するとともに、その端子構造を少ない工程数で得ることを可能とするセラミック回路モジュールの製造方法が示されている。かかる構成として、例えば、特許文献1に記載される技術が知られている。   Here, for example, in a BGA type ceramic circuit module composed of a ceramic substrate obtained by laminating and firing a ceramic material together with a conductive wiring material, the outer peripheral portion of the electrode pad of the BGA connection portion is mounted on the wiring substrate. In some cases, thermal stress concentrates on the ceramic substrate and cracks occur in the ceramic substrate around the electrode pad. Thus, by covering the outer periphery of the electrode pad with a glass protective film, a method for manufacturing a ceramic circuit module is provided that provides a terminal structure in which cracks are unlikely to occur and enables the terminal structure to be obtained with a small number of steps. ing. As such a configuration, for example, a technique described in Patent Document 1 is known.

また、線膨張係数の異なる二種類の基板をつなぐBGA接続構造では、熱履歴が加わったときに、接続端子であるハンダの一部に熱応力が集中する。すると、ハンダと基板の電極パッドとの接合面付近にて、ハンダにクラックが生じて、ハンダが破断する問題がある。この解決策として、BGA接続部のハンダの一部に熱応力が集中することを防ぐ構成が採用されている。すなわち、ハンダ中にプラスチックボールが配合され、そのプラスチックボールの線膨張係数が適当に選択される。これにより、プラスチックボールと下地ハンダ層との間に隙間が形成されて、BGA接続部の温度変化による歪みが吸収される。また、BGA接続部が鼓形状の断面形状を有することにより、ハンダと電極パッドとの接合面付近に生ずる熱応力が分散される。かかる構成として、例えば、特許文献2に記載される技術が知られている。   In addition, in the BGA connection structure that connects two types of substrates having different linear expansion coefficients, thermal stress is concentrated on a part of the solder that is the connection terminal when a thermal history is applied. Then, there is a problem that the solder is cracked in the vicinity of the joint surface between the solder and the electrode pad of the substrate, and the solder is broken. As a solution to this problem, a configuration is adopted in which thermal stress is prevented from concentrating on a part of the solder of the BGA connection portion. That is, a plastic ball is blended in the solder, and the linear expansion coefficient of the plastic ball is appropriately selected. As a result, a gap is formed between the plastic ball and the underlying solder layer, and distortion due to temperature change of the BGA connection portion is absorbed. Further, since the BGA connection portion has a drum-shaped cross-sectional shape, thermal stress generated in the vicinity of the joint surface between the solder and the electrode pad is dispersed. As such a configuration, for example, a technique described in Patent Document 2 is known.

その他、セラミック基板と配線基板との間にアンダーフィル材が充填される構成がある。かかる構成では、電極パッド全体もしくはその一部が補強されることにより、ハンダボールと電極パッドとの接合部付近におけるクラックの発生あるいは電極パッドの周囲の基材におけるクラックの発生が防止される。かかる構成として、例えば、特許文献3に記載される技術が知られている。   In addition, there is a configuration in which an underfill material is filled between the ceramic substrate and the wiring substrate. In such a configuration, the entire electrode pad or a part thereof is reinforced, thereby preventing the occurrence of cracks in the vicinity of the joint between the solder ball and the electrode pad or the generation of cracks in the base material around the electrode pad. As such a configuration, for example, a technique described in Patent Document 3 is known.

特開2007−250564号公報JP 2007-250564 A 特許第2856197号公報Japanese Patent No. 2856197 特許第3644340号公報Japanese Patent No. 3644340

しかしながら、特許文献1の構成では、電極パッドの周囲にクラックが生じ難いものの、接続部分のハンダボールがつぶれて、ハンダボールの中央部が膨らみ易い。このため、電極パッドの接合面付近では、ハンダボールがくびれた形状を有し、このくびれ部に応力が集中してクラックが発生するおそれがあった。また、半導体装置に要求される耐久温度範囲が広がると、熱膨張差によりパッド接合部への熱応力が増大する。このため、例えば、電極パッドの導体厚さを厚くして応力を緩和させる方法が考えられている。しかし、導体厚が厚くなると、導体の使用量が増加し、結果としてコストUPの原因となる。また、一般的な厚さの導体を有する構成では、導体膜が導体ペーストのスクリーン印刷によって形成される。しかし、厚い導体を有する構成では、印刷工程におけるスクリーンマスクへの充填およびマスクの抜け性が悪化するため、導体膜の形成が困難である。さらに、かかる構成では、使用可能な導体材料として、基材との密着強度が十分にある材料(セラミック材など)しか選択できないという問題がある。つまり、先述のように、ハンダボールのつぶれ、接続部中央の膨らみ、および、電極パッドの接合面付近のくびれを有するBGA接続構造では、力学的に電極パッドの接合部付近に最も大きく熱応力が作用する。このため、上記のような基板の補強だけでは、耐久温度範囲の拡大または基板サイズの拡大という要求を満足できない。   However, in the configuration of Patent Document 1, although cracks are unlikely to occur around the electrode pad, the solder ball at the connection portion is crushed and the central portion of the solder ball tends to swell. For this reason, the solder ball has a constricted shape in the vicinity of the joint surface of the electrode pad, and there is a possibility that stress concentrates on the constricted portion and cracks occur. Further, when the endurance temperature range required for the semiconductor device is widened, the thermal stress on the pad bonding portion increases due to the difference in thermal expansion. For this reason, for example, a method of relaxing the stress by increasing the conductor thickness of the electrode pad is considered. However, as the conductor thickness increases, the amount of conductor used increases, resulting in increased costs. In a configuration having a conductor having a general thickness, the conductor film is formed by screen printing of a conductor paste. However, in the structure having a thick conductor, filling of the screen mask and the removal of the mask in the printing process are deteriorated, so that it is difficult to form a conductor film. Furthermore, in such a configuration, there is a problem that only a material (ceramic material or the like) having sufficient adhesion strength to the base material can be selected as a usable conductor material. That is, as described above, in the BGA connection structure having the collapse of the solder ball, the bulge in the center of the connection portion, and the constriction near the bonding surface of the electrode pad, the largest thermal stress is mechanically near the bonding portion of the electrode pad. Works. For this reason, only the reinforcement of the substrate as described above cannot satisfy the requirement of extending the durable temperature range or the substrate size.

また、特許文献2の構成では、ハンダボールのつぶれ、BGA接続部中央の膨らみ、および、電極パッドの接合面付近のくびれを解決するために、ハンダと電極パッドとの接合面付近に集中する熱応力を分散させる構成が採用されている。すなわち、BGA接続部のハンダ中にプラスチックボール等が配合され、このプラスチックボール径よりも基板の電極パッド径が大きく設定されることにより、BGA接続部の中央がくびれた鼓形状となるように構成されている。しかし、かかる構成では、ハンダ中にプラスチックボールを内包する工程が必要となり、製造コストや工程数が増えるという問題がある。   Further, in the configuration of Patent Document 2, in order to solve the collapse of the solder ball, the swelling at the center of the BGA connection portion, and the constriction near the bonding surface of the electrode pad, the heat concentrated on the bonding surface between the solder and the electrode pad is concentrated. A configuration that disperses the stress is employed. That is, a plastic ball or the like is blended in the solder of the BGA connection portion, and the electrode pad diameter of the substrate is set larger than the plastic ball diameter, so that the center of the BGA connection portion has a constricted drum shape. Has been. However, such a configuration requires a process of enclosing plastic balls in the solder, and there is a problem that the manufacturing cost and the number of processes increase.

また、特許文献3の構成では、アンダーフィル材が半導体装置と配線基板との間のBGA接続部に充填されて、BGA接続部が補強されている。しかし、かかる構成では、BGA接続後にアンダーフィルを充填するための工程が必要となるという問題がある。また、セラミック基板と配線基板との間にアンダーフィル材が存在すると、誘電率が高くなり、高周波の伝送損失が高くなる。このため、アンダーフィル材は、高周波用半導体部品間の接合補強材料としては適さない。   Moreover, in the structure of patent document 3, the underfill material is filled in the BGA connection part between a semiconductor device and a wiring board, and the BGA connection part is reinforced. However, such a configuration has a problem that a process for filling the underfill after the BGA connection is required. In addition, when an underfill material exists between the ceramic substrate and the wiring substrate, the dielectric constant increases and the transmission loss of high frequency increases. For this reason, an underfill material is not suitable as a joint reinforcement material between high frequency semiconductor components.

この発明は、上記に鑑みてなされたものであって、熱応力によるクラックの発生を抑制できる半導体装置およびその製造方法を提供することを目的とする。   The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the occurrence of cracks due to thermal stress.

上述した課題を解決し、目的を達成するために、この発明にかかる半導体装置は、アレイ状あるいはランダム状に配列された複数の接続端子を介して被実装対象が実装対象に実装される半導体装置であって、前記実装対象側に複数の電極パッドを形成する手段と、前記接続端子を前記電極パッド上にて溶融および凝固させて前記実装対象に結合する手段とを備え、且つ、一部の前記電極パッドが、前記接続端子の凝固形状を規定する本体部と、前記接続端子の溶融時にて前記接続端子の一部を前記本体部の外周にガイドするガイド部とを有することを特徴とする。   In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention is a semiconductor device in which a mounting target is mounted on a mounting target via a plurality of connection terminals arranged in an array or at random. And a means for forming a plurality of electrode pads on the mounting target side, a means for melting and solidifying the connection terminal on the electrode pad, and coupling to the mounting target. The electrode pad includes a main body part that defines a solidification shape of the connection terminal, and a guide part that guides a part of the connection terminal to the outer periphery of the main body part when the connection terminal is melted. .

また、この発明にかかる半導体装置では、前記本体部および前記ガイド部を有する前記電極パッドと、前記本体部のみを有する前記電極パッドとの双方が単一の前記実装対象上に配列される。   In the semiconductor device according to the present invention, both the electrode pad having the main body portion and the guide portion and the electrode pad having only the main body portion are arranged on a single mounting target.

また、この発明にかかる半導体装置では、前記本体部および前記ガイド部を有する前記電極パッドが前記実装対象の信号回路部に配置される。   In the semiconductor device according to the present invention, the electrode pad having the main body portion and the guide portion is disposed in the signal circuit portion to be mounted.

また、この発明にかかる半導体装置では、前記本体部および前記ガイド部を有する前記電極パッドが前記実装対象の外周対角部に配置される。   In the semiconductor device according to the present invention, the electrode pad having the main body portion and the guide portion is disposed on an outer peripheral diagonal portion of the mounting target.

また、この発明にかかる半導体装置では、前記ガイド部が前記本体部に対して所定間隔を隔てつつ前記本体部の外周を囲んで配置される環状構造を有すると共に一部にて前記本体部に連結される。   Further, in the semiconductor device according to the present invention, the guide portion has an annular structure arranged to surround the outer periphery of the main body portion with a predetermined distance from the main body portion, and is partially connected to the main body portion. Is done.

また、この発明にかかる半導体装置では、前記ガイド部が前記本体部から突出した島状形状を有する。   In the semiconductor device according to the present invention, the guide portion has an island shape protruding from the main body portion.

また、この発明にかかる半導体装置では、前記被実装対象側に複数の電極パッドを形成する手段を備え、且つ、前記被実装対象と前記実装対象とが相互に異なる靭性を有するときに、低い靭性を有する側の前記電極パッドの径φDaと高い靭性を有する側の前記電極パッドの径φDbとがφDa>φDbの関係を有する。   Further, the semiconductor device according to the present invention includes means for forming a plurality of electrode pads on the mounting target side, and low toughness when the mounting target and the mounting target have different toughness. The diameter φDa of the electrode pad on the side having a thickness and the diameter φDb of the electrode pad on the side having a high toughness have a relationship of φDa> φDb.

また、この発明にかかる半導体装置の製造方法では、アレイ状あるいはランダム状に配列された複数の接続端子を介して被実装対象を実装対象に実装する半導体装置の製造方法であって、前記実装対象側に複数の電極パッドが形成されるステップと、前記接続端子が前記電極パッド上にて溶融および凝固することにより前記実装対象に結合されるステップとを備え、且つ、一部の前記電極パッドが、前記接続端子の凝固形状を規定する本体部と、前記接続端子の溶融時にて前記接続端子の一部を前記本体部の外周にガイドするガイド部とを有することを特徴とする。   The semiconductor device manufacturing method according to the present invention is a method for manufacturing a semiconductor device in which a mounting target is mounted on a mounting target via a plurality of connection terminals arranged in an array or at random. A plurality of electrode pads are formed on the side, and the connection terminals are coupled to the mounting object by melting and solidifying on the electrode pads, and some of the electrode pads are And a main body part that defines a solidification shape of the connection terminal, and a guide part that guides a part of the connection terminal to the outer periphery of the main body part when the connection terminal is melted.

この発明にかかる半導体装置および半導体装置の製造方法では、BGA接続構造を構成する一部の電極パッドが、接続端子の凝固形状を規定する本体部と、接続端子の溶融時にて接続端子の一部を本体部の外周にガイドするガイド部とを有する。かかる構成では、被実装対象の実装工程にて、溶融した接続端子の一部が本体部からガイド部まで移動して、本体部上の接続端子の体積が減少する。すると、ハンダ凝固ステップにて接続端子が凝固したときに、接続端子の中央部がくびれた鼓形状になり、また、接続端子の接合部がフィレット形状になって実装対象の第一電極パッドに結合する。すると、半導体装置の熱履歴により実装対象が熱変形したときに、熱応力が接続端子の中央部に作用し易くなり、接続端子と第一電極パッドとの接合部に作用するせん断熱応力が低減される。すると、熱応力による接続端子のクラックの発生あるいは接続端子と実装対象との接合部におけるクラックの発生が抑制される。これにより、半導体装置の接続不良が抑制される利点がある。   In the semiconductor device and the semiconductor device manufacturing method according to the present invention, a part of the electrode pads constituting the BGA connection structure includes a main body part that defines a solidification shape of the connection terminal, and a part of the connection terminal when the connection terminal is melted And a guide portion for guiding the guide to the outer periphery of the main body portion. In such a configuration, in the mounting process of the mounting target, a part of the molten connection terminal moves from the main body part to the guide part, and the volume of the connection terminal on the main body part decreases. Then, when the connection terminal solidifies in the solder solidification step, the central part of the connection terminal becomes a constricted drum shape, and the connection part of the connection terminal becomes a fillet shape and is coupled to the first electrode pad to be mounted. To do. Then, when the mounting target is thermally deformed due to the thermal history of the semiconductor device, the thermal stress is likely to act on the center portion of the connection terminal, and the shear thermal stress acting on the joint portion between the connection terminal and the first electrode pad is reduced. Is done. Then, generation | occurrence | production of the crack of the connection terminal by a thermal stress or generation | occurrence | production of the crack in the junction part of a connection terminal and mounting object is suppressed. Thereby, there is an advantage that connection failure of the semiconductor device is suppressed.

図1は、この発明の実施の形態にかかる半導体装置を示す構成図である。FIG. 1 is a configuration diagram showing a semiconductor device according to an embodiment of the present invention. 図2は、図1に記載した半導体装置のBGA接続構造を示す拡大図である。FIG. 2 is an enlarged view showing a BGA connection structure of the semiconductor device shown in FIG. 図3は、図1に記載した半導体装置の製造工程を示す説明図である。FIG. 3 is an explanatory view showing a manufacturing process of the semiconductor device shown in FIG. 図4は、BGA接続構造の第一電極パッドを示す平面図である。FIG. 4 is a plan view showing the first electrode pad of the BGA connection structure. 図5は、BGA接続構造の第二電極パッドを示す平面図である。FIG. 5 is a plan view showing a second electrode pad of the BGA connection structure. 図6は、実装対象における第一電極パッドおよび第二電極パッドの配置例を示す平面図である。FIG. 6 is a plan view showing an arrangement example of the first electrode pads and the second electrode pads in the mounting target. 図7は、実装対象における第一電極パッドおよび第二電極パッドの配置例を示す平面図である。FIG. 7 is a plan view showing an arrangement example of the first electrode pads and the second electrode pads on the mounting target. 図8は、第一電極パッド側の接続端子の溶融状態を示す説明図である。FIG. 8 is an explanatory diagram illustrating a melting state of the connection terminal on the first electrode pad side. 図9は、第二電極パッド側の接続端子の溶融状態を示す説明図である。FIG. 9 is an explanatory diagram illustrating a melting state of the connection terminals on the second electrode pad side. 図10は、電極パッドの成形工程を示す説明図である。FIG. 10 is an explanatory view showing a forming process of the electrode pad. 図11は、電極パッドの成形工程を示す説明図である。FIG. 11 is an explanatory view showing a forming process of the electrode pad. 図12は、第一電極パッドの変形例を示す平面図である。FIG. 12 is a plan view showing a modification of the first electrode pad. 図13は、第一電極パッドの変形例を示す平面図である。FIG. 13 is a plan view showing a modification of the first electrode pad. 図14は、被実装対象の電極パッドの径と実装対象の電極パッドの径との関係を示す説明図である。FIG. 14 is an explanatory diagram showing the relationship between the diameter of the electrode pad to be mounted and the diameter of the electrode pad to be mounted. 図15は、被実装対象の電極パッドの径と実装対象の電極パッドの径との関係を示す説明図である。FIG. 15 is an explanatory diagram showing the relationship between the diameter of the electrode pad to be mounted and the diameter of the electrode pad to be mounted.

以下、この発明につき図面を参照しつつ詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。また、この実施の形態の構成要素には、発明の同一性を維持しつつ置換可能かつ置換自明なものが含まれる。また、この実施の形態に記載された複数の変形例は、当業者自明の範囲内にて任意に組み合わせが可能である。   Hereinafter, the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Further, the constituent elements of this embodiment include those that can be replaced while maintaining the identity of the invention and that are obvious for replacement. In addition, a plurality of modifications described in this embodiment can be arbitrarily combined within a range obvious to those skilled in the art.

[半導体装置のBGA接続構造]
この半導体装置1は、BGA(Ball Grid Array)接続構造を有する半導体装置に適用される。BGA接続構造とは、例えば、アレイ状あるいはランダム状に配列された複数の接続端子を介して被実装対象を実装対象に実装する構造をいう。以下、このBGA接続構造を有する半導体装置1について、図面を参照しつつ詳細に説明する。
[BGA connection structure of semiconductor device]
The semiconductor device 1 is applied to a semiconductor device having a BGA (Ball Grid Array) connection structure. The BGA connection structure refers to a structure in which a mounting target is mounted on a mounting target via a plurality of connection terminals arranged in an array or at random. Hereinafter, the semiconductor device 1 having this BGA connection structure will be described in detail with reference to the drawings.

図1は、この発明の実施の形態にかかる半導体装置を示す構成図である。図2は、図1に記載した半導体装置のBGA接続構造を示す拡大図である。図3は、図1に記載した半導体装置の製造工程を示す説明図である。図4および図5は、BGA接続構造の実装対象側の電極パッドを示す平面図である。   FIG. 1 is a configuration diagram showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged view showing a BGA connection structure of the semiconductor device shown in FIG. FIG. 3 is an explanatory view showing a manufacturing process of the semiconductor device shown in FIG. 4 and 5 are plan views showing electrode pads on the mounting target side of the BGA connection structure.

この半導体装置1では、被実装対象2が実装対象3に対してBGA接続構造4を介して実装される(図1および図2参照)。   In this semiconductor device 1, the mounting target 2 is mounted on the mounting target 3 via the BGA connection structure 4 (see FIGS. 1 and 2).

被実装対象2は、半導体素子や受動回路素子(例えば、抵抗、コンデンサ等)などの電子部品、あるいは、これらの電子部品を実装した回路基板により構成される。例えば、この実施の形態では、被実装対象2が半導体素子21を実装した回路基板22により構成されている。また、回路基板22には、所定の信号回路23が形成され、また、カバー部材であるキャップ24が取り付けられている。実装対象3は、例えば、所定のプリント配線パターンを有する配線基板により構成される。   The mounted object 2 is configured by an electronic component such as a semiconductor element or a passive circuit element (for example, a resistor or a capacitor), or a circuit board on which these electronic components are mounted. For example, in this embodiment, the mounting target 2 is constituted by a circuit board 22 on which a semiconductor element 21 is mounted. A predetermined signal circuit 23 is formed on the circuit board 22 and a cap 24 as a cover member is attached. The mounting target 3 is constituted by, for example, a wiring board having a predetermined printed wiring pattern.

BGA接続構造4は、接続端子41と、一対の電極パッド42、43とにより構成される。接続端子41は、球状の金属材料であり、例えば、ハンダボールにより構成される。一対の電極パッド42、43は、被実装対象2側に形成される電極パッド42と、実装対象3側に形成される電極パッド43とにより構成される。このBGA接続構造4では、接続端子41が被実装対象2側の電極パッド42と実装対象3側の電極パッド43とを接続することにより、被実装対象2が実装対象3に実装される。また、複数の接続端子41(および電極パッド42、43)がアレイ状あるいはランダム状に配列されて被実装対象2と実装対象3とを接続する。これにより、パッケージの小型化や電子部品類の高密度実装が可能となり、電子機器の小型化が実現される。また、BGA接続構造4は、リードレス構造を有するので、被実装対象2と実装対象3との接続距離が短縮される。これにより、電子機器の信号処理速度が向上する。なお、実装対象3側の電極パッド43の形状および配列構造については、後述する。   The BGA connection structure 4 includes a connection terminal 41 and a pair of electrode pads 42 and 43. The connection terminal 41 is a spherical metal material and is made of, for example, a solder ball. The pair of electrode pads 42 and 43 includes an electrode pad 42 formed on the mounting target 2 side and an electrode pad 43 formed on the mounting target 3 side. In this BGA connection structure 4, the mounting target 2 is mounted on the mounting target 3 by connecting the electrode pads 42 on the mounting target 2 side and the electrode pads 43 on the mounting target 3 side by the connection terminals 41. In addition, a plurality of connection terminals 41 (and electrode pads 42 and 43) are arranged in an array or a random manner to connect the mounted object 2 and the mounting object 3. Thereby, downsizing of the package and high-density mounting of electronic components are possible, and downsizing of the electronic device is realized. Moreover, since the BGA connection structure 4 has a leadless structure, the connection distance between the mounted object 2 and the mounted object 3 is shortened. This improves the signal processing speed of the electronic device. The shape and arrangement structure of the electrode pads 43 on the mounting target 3 side will be described later.

この半導体装置1の製造工程では、まず、被実装対象2の下面に電極パッド42が形成され、この電極パッド42上に接続端子41が接合される(図3(a)参照)。また、実装対象3の上面に電極パッド43が形成され、この電極パッド43上にクリームハンダ44が印刷される(クリームハンダ印刷ステップ)。なお、クリームハンダ44は、フラックスを添加して粘度調整した粉末状のハンダである。次に、被実装対象2の下面と実装対象3の上面とが貼り合わされ、被実装対象2側の接続端子41が対応する実装対象3側のクリームハンダ44に押し当てられる(基板搭載ステップ)(図3(b)参照)。これにより、接続端子41が被実装対象2側の電極パッド42と実装対象3側の電極パッド43との間に挟み込まれる。   In the manufacturing process of the semiconductor device 1, first, the electrode pad 42 is formed on the lower surface of the mounting target 2, and the connection terminal 41 is bonded onto the electrode pad 42 (see FIG. 3A). Moreover, the electrode pad 43 is formed on the upper surface of the mounting target 3, and the cream solder 44 is printed on the electrode pad 43 (cream solder printing step). The cream solder 44 is powdered solder that is adjusted in viscosity by adding flux. Next, the lower surface of the mounting target 2 and the upper surface of the mounting target 3 are bonded together, and the connection terminals 41 on the mounting target 2 side are pressed against the corresponding cream solder 44 on the mounting target 3 side (substrate mounting step) ( (Refer FIG.3 (b)). As a result, the connection terminal 41 is sandwiched between the electrode pad 42 on the mounting target 2 side and the electrode pad 43 on the mounting target 3 side.

次に、リフロー予備加熱が行われる(リフロー予備加熱ステップ)(図3(c)参照)。すると、クリームハンダ44が軟化して、実装対象3側の電極パッド43上を被覆する。次に、リフロー本加熱が行われる(リフロー本加熱ステップ)(図3(d)参照)。すると、接続端子41がその融点にて溶融し始めて、実装対象3側の電極パッド43上に濡れ広がる(ハンダ溶融ステップ)(図3(e)参照)。その後に、冷却が行われて接続端子41が凝固することにより、被実装対象2側の電極パッド42と実装対象3側の電極パッド43とが接続端子41を介して導通する(ハンダ凝固ステップ)(図3(f)参照)。これにより、被実装対象2と実装対象3とがBGA接続構造4を介して接続される。また、このとき、溶融して凝固した接続端子41の形状が電極パッド43の平面形状により規制される。これにより、接続端子41の形状が適正化される。   Next, reflow preheating is performed (reflow preheating step) (see FIG. 3C). Then, the cream solder 44 is softened and covers the electrode pad 43 on the mounting target 3 side. Next, reflow main heating is performed (reflow main heating step) (see FIG. 3D). Then, the connection terminal 41 starts to melt at the melting point and spreads wet on the electrode pad 43 on the mounting target 3 side (solder melting step) (see FIG. 3E). Thereafter, cooling is performed and the connection terminal 41 is solidified, whereby the electrode pad 42 on the mounting target 2 side and the electrode pad 43 on the mounting target 3 side are conducted through the connection terminal 41 (solder solidification step). (Refer FIG.3 (f)). Thereby, the mounting target 2 and the mounting target 3 are connected through the BGA connection structure 4. At this time, the shape of the connection terminal 41 melted and solidified is regulated by the planar shape of the electrode pad 43. Thereby, the shape of the connection terminal 41 is optimized.

[BGA接続構造の電極パッド]
ここで、被実装対象と実装対象とが相互に異なる線膨張係数を有する構成では、その線膨張係数の差により、BGA接続構造の接続端子に熱応力が発生する。すると、接続端子にクラックが発生したり、接続端子と実装対象との接合部にクラックが発生したりするおそれがある。かかるクラックの発生は、半導体装置の接続不良の原因となる。
[BGA connection structure electrode pads]
Here, in the configuration in which the mounting target and the mounting target have different linear expansion coefficients, thermal stress is generated in the connection terminals of the BGA connection structure due to the difference in the linear expansion coefficients. Then, there is a possibility that a crack is generated in the connection terminal, or a crack is generated in a joint portion between the connection terminal and the mounting target. The occurrence of such a crack causes a connection failure of the semiconductor device.

そこで、この半導体装置1では、かかる課題を解決するために以下の構成が採用されている。まず、実装対象3側の電極パッド43群が、第一電極パッド43aおよび第二電極パッド43bから成る二種類の電極パッドにより構成される(図4〜図7参照)。そして、これらの第一電極パッド43aおよび第二電極パッド43bが、実装対象3の接合面(被実装対象2との接合面)にて、所定間隔を隔てつつ縦横かつアレイ状に配列される(図6あるいは図7参照)。なお、第一電極パッド43aおよび第二電極パッド43bの配置例については、後述する。   Therefore, in the semiconductor device 1, the following configuration is adopted in order to solve such a problem. First, the group of electrode pads 43 on the mounting target 3 side includes two types of electrode pads including a first electrode pad 43a and a second electrode pad 43b (see FIGS. 4 to 7). Then, the first electrode pads 43a and the second electrode pads 43b are arranged in a vertical and horizontal array with a predetermined interval on the bonding surface of the mounting target 3 (the bonding surface with the mounting target 2) ( (See FIG. 6 or FIG. 7). An arrangement example of the first electrode pad 43a and the second electrode pad 43b will be described later.

第一電極パッド43aは、本体部431およびガイド部432から成る(図4参照)。また、第二電極パッド43bは、本体部431のみから成る(図5参照)。本体部431は、接続端子41の凝固形状を規定する部分であり、第一電極パッド43aおよび第二電極パッド43bの双方に共通する部分である。例えば、この実施の形態では、本体部431が円形状(円盤状)に形成されている。ガイド部432は、接続端子41の溶融時にて接続端子41の材料の一部を本体部431の外周にガイドする部分であり、第一電極パッド43aのみに形成される。例えば、この実施の形態では、ガイド部432が円環構造を有しており、本体部431との間に所定の隙間を空けつつ本体部431の外周を囲んで配置されると共に四本の連結部433を介して本体部431に連結されている。   The first electrode pad 43a includes a main body portion 431 and a guide portion 432 (see FIG. 4). The second electrode pad 43b is composed only of the main body 431 (see FIG. 5). The main body 431 is a part that defines the solidification shape of the connection terminal 41, and is a part common to both the first electrode pad 43a and the second electrode pad 43b. For example, in this embodiment, the main body 431 is formed in a circular shape (disc shape). The guide portion 432 is a portion that guides a part of the material of the connection terminal 41 to the outer periphery of the main body portion 431 when the connection terminal 41 is melted, and is formed only on the first electrode pad 43a. For example, in this embodiment, the guide portion 432 has an annular structure, and is arranged so as to surround the outer periphery of the main body portion 431 while leaving a predetermined gap between the guide portion 432 and the four connecting portions. It is connected to the main body portion 431 through the portion 433.

上記の構成では、半導体装置1の製造工程にて、BGA接続構造4により被実装対象2を実装対象3に実装するときに、接続端子41の凝固形状が以下のように形成される(図2、図3、図8および図9参照)。   With the above configuration, when the mounting target 2 is mounted on the mounting target 3 by the BGA connection structure 4 in the manufacturing process of the semiconductor device 1, the solidified shape of the connection terminal 41 is formed as follows (FIG. 2). , FIG. 3, FIG. 8 and FIG. 9).

まず、第一電極パッド43aでは、リフロー本加熱ステップにて、クリームハンダ44が軟化して第一電極パッド43aを被覆するときに、クリームハンダ44が本体部431から連結部433を伝ってガイド部432まで濡れ広がる(図3(d)参照)。すると、ハンダ溶融ステップにて、溶融した接続端子41の一部が本体部431からガイド部432まで移動して、本体部431上の接続端子41の体積が減少する(図3(e)の「a部」参照)。すると、ハンダ凝固ステップにて接続端子41が凝固したときに、接続端子41の中央部411が鼓形状(くびれた形状)になり、また、接続端子41の接合部412がフィレット形状(端部を拡幅した形状)になって第一電極パッド43aに結合する(図3(f)「a部」参照)。これにより、第一電極パッド43aにおける接続端子41の形状が適正化される(図2参照)。   First, in the first electrode pad 43a, when the cream solder 44 is softened and covers the first electrode pad 43a in the reflow main heating step, the cream solder 44 is transmitted from the main body portion 431 through the connecting portion 433 to the guide portion. It spreads wet to 432 (see FIG. 3D). Then, in the solder melting step, a part of the molten connection terminal 41 moves from the main body portion 431 to the guide portion 432, and the volume of the connection terminal 41 on the main body portion 431 decreases (see “ a part "). Then, when the connection terminal 41 is solidified in the solder solidification step, the central portion 411 of the connection terminal 41 has a drum shape (constricted shape), and the joint portion 412 of the connection terminal 41 has a fillet shape (end portion). It becomes a widened shape) and is coupled to the first electrode pad 43a (refer to “a part” in FIG. 3F). Thereby, the shape of the connection terminal 41 in the 1st electrode pad 43a is optimized (refer FIG. 2).

一方、第二電極パッド43bでは、リフロー本加熱ステップにて、クリームハンダ44が軟化して第二電極パッド43bを被覆するときに、クリームハンダ44が本体部431にのみ濡れ広がる(図3(d)参照)。すると、ハンダ溶融ステップにて、溶融した接続端子41が本体部431上に留まり、その体積減少が生じない(図3(e)の「b部」参照)。すると、ハンダ凝固ステップにて接続端子41が凝固したときに、接続端子41の中央部411が膨らんだ形状(扁平したボール形状)になり、また、接続端子41の接合部412がくびれた形状になって第二電極パッド43bに接合する(図3(f)「b部」参照)。   On the other hand, in the second electrode pad 43b, when the cream solder 44 is softened and covers the second electrode pad 43b in the reflow main heating step, the cream solder 44 wets and spreads only on the main body 431 (FIG. 3D )reference). Then, in the solder melting step, the molten connection terminal 41 stays on the main body portion 431, and the volume thereof does not decrease (see “b portion” in FIG. 3E). Then, when the connection terminal 41 is solidified in the solder solidification step, the central portion 411 of the connection terminal 41 has a swelled shape (flat ball shape), and the joint portion 412 of the connection terminal 41 has a constricted shape. It joins to the 2nd electrode pad 43b (refer FIG.3 (f) "b part").

また、複数の第一電極パッド43aと複数の第二電極パッド43bとの双方が単一の実装対象3上に配列されることにより、以下の作用が得られる(図3および図6〜図9参照)。第一電極パッド43aでは、上記のように、ハンダ溶融ステップにて、溶融した接続端子41の一部が本体部431からガイド部432に移動して、本体部431上の接続端子41の体積が減少する(図3(e)の「a部」参照)。このため、被実装対象2と実装対象3との間隔Haが接続端子41の体積減少の分だけ狭くなる(図8参照)。すると、溶融した接続端子41が潰れた形状になり、接続端子41と第一電極パッド43aとの接続形状が安定する。一方、第二電極パッド43bでは、ハンダ溶融ステップにて、第二電極パッド43bがガイド部を有さないので、接続端子41の体積が減少しない(図3(e)の「b部」参照)。このため、被実装対象2と実装対象3との間隔Hbが第一電極パッド43aにおける間隔Haよりも広く(Ha<Hb)、かつ、安定的に維持される(図9参照)。このため、ハンダ凝固ステップにて接続端子41が凝固するときに、第一電極パッド43a側の間隔Haが第二電極パッド43b側の間隔Hbに応じて拡幅される。すると、第一電極パッド43a上の接続端子41が潰れた形状(図8参照)から鼓形状の中央部411およびフィレット形状の接合部412を有する好適な形状(図2および図3(f)「a部」参照)に変形する。これにより、第一電極パッド43aの接続端子41が適正な形状に成形される。なお、被実装対象2と実装対象3との間隔Ha、Hbは、溶融した接続端子41の表面張力および被実装対象2の自重により決定される。   Further, by arranging both the plurality of first electrode pads 43a and the plurality of second electrode pads 43b on a single mounting target 3, the following actions are obtained (FIGS. 3 and 6 to 9). reference). In the first electrode pad 43a, as described above, in the solder melting step, a part of the molten connection terminal 41 moves from the main body portion 431 to the guide portion 432, and the volume of the connection terminal 41 on the main body portion 431 becomes larger. It decreases (refer to “a part” in FIG. 3E). For this reason, the distance Ha between the mounted object 2 and the mounted object 3 is reduced by the volume reduction of the connection terminal 41 (see FIG. 8). Then, the melted connection terminal 41 is crushed, and the connection shape between the connection terminal 41 and the first electrode pad 43a is stabilized. On the other hand, in the second electrode pad 43b, since the second electrode pad 43b does not have a guide part in the solder melting step, the volume of the connection terminal 41 does not decrease (see “b part” in FIG. 3E). . For this reason, the distance Hb between the mounted object 2 and the mounted object 3 is wider than the distance Ha in the first electrode pad 43a (Ha <Hb) and is stably maintained (see FIG. 9). For this reason, when the connection terminal 41 is solidified in the solder solidification step, the interval Ha on the first electrode pad 43a side is widened according to the interval Hb on the second electrode pad 43b side. Then, the suitable shape (FIG. 2 and FIG. 3 (f) “) which has the drum-shaped center part 411 and the fillet-shaped joining part 412 from the shape (refer FIG. 8) which the connection terminal 41 on the 1st electrode pad 43a was crushed. (refer to part a). Thereby, the connection terminal 41 of the first electrode pad 43a is formed into an appropriate shape. Note that the distances Ha and Hb between the mounted object 2 and the mounted object 3 are determined by the surface tension of the molten connection terminal 41 and the weight of the mounted object 2.

なお、電極パッド42、43は、例えば、NSMD(non-Solder Mask Defined)法、SMD(Solder Mask Defined)などの公知の手法により形成され得る(図10および図11参照)。これにより、上記の電極パッド42、43(特に、ガイド部432を有する第一電極パッド43a)が工程数を増加させることなく容易に形成され得る。例えば、NSMD法では、実装対象3に銅箔などの導体が形成され、この導体がエッジングされることにより、電極パッド42、43が形成される(図10参照)。また、SMD法では、実装対象3の導体面(上面)が電極パッド42、43の成形部のみを残してソルダーレジストにより被覆されることにより、電極パッド42、43が形成される(図11参照)。   In addition, the electrode pads 42 and 43 can be formed by well-known methods, such as NSMD (non-Solder Mask Defined) method and SMD (Solder Mask Defined), for example (refer FIG. 10 and FIG. 11). Accordingly, the electrode pads 42 and 43 (particularly, the first electrode pad 43a having the guide portion 432) can be easily formed without increasing the number of steps. For example, in the NSMD method, a conductor such as a copper foil is formed on the mounting target 3, and electrode pads 42 and 43 are formed by edging the conductor (see FIG. 10). Further, in the SMD method, the conductor surface (upper surface) of the mounting target 3 is covered with a solder resist leaving only the molded portions of the electrode pads 42 and 43, thereby forming the electrode pads 42 and 43 (see FIG. 11). ).

[効果]
以上説明したように、この半導体装置1では、BGA接続構造4を構成する一部の電極パッド(第一電極パッド)43aが、接続端子41の凝固形状を規定する本体部431と、接続端子41の溶融時にて接続端子41の一部を本体部431の外周にガイドするガイド部432とを有する(図4参照)。かかる構成では、被実装対象2の実装工程にて、溶融した接続端子41の一部が本体部431からガイド部432まで移動して、本体部431上の接続端子41の体積が減少する(図3(e)の「a部」参照)。すると、ハンダ凝固ステップにて接続端子41が凝固したときに、接続端子41の中央部411がくびれた鼓形状になり、また、接続端子41の接合部412がフィレット形状になって実装対象3の第一電極パッド43aに結合する(図3(f)「a部」参照)。すると、半導体装置1の熱履歴により実装対象3が熱変形したときに、熱応力が接続端子41の中央部411に作用し易くなり、接続端子41と第一電極パッド43aとの接合部412に作用するせん断熱応力が低減される。すると、熱応力による接続端子のクラックの発生あるいは接続端子と実装対象との接合部におけるクラックの発生が抑制される。これにより、半導体装置1の接続不良が抑制される利点がある。
[effect]
As described above, in this semiconductor device 1, a part of the electrode pads (first electrode pads) 43 a constituting the BGA connection structure 4 includes the main body portion 431 that defines the solidification shape of the connection terminals 41, and the connection terminals 41. And a guide portion 432 that guides a part of the connection terminal 41 to the outer periphery of the main body portion 431 when melting (see FIG. 4). In such a configuration, a part of the molten connection terminal 41 moves from the main body part 431 to the guide part 432 in the mounting process of the mounting target 2, and the volume of the connection terminal 41 on the main body part 431 decreases (see FIG. 3 (e) "Part a"). Then, when the connection terminal 41 is solidified in the solder solidification step, the central portion 411 of the connection terminal 41 has a constricted drum shape, and the joint portion 412 of the connection terminal 41 has a fillet shape, so It couple | bonds with the 1st electrode pad 43a (refer FIG.3 (f) "a part"). Then, when the mounting target 3 is thermally deformed due to the thermal history of the semiconductor device 1, the thermal stress is likely to act on the central portion 411 of the connection terminal 41, and the joint portion 412 between the connection terminal 41 and the first electrode pad 43 a becomes easy. The acting shear thermal stress is reduced. Then, generation | occurrence | production of the crack of the connection terminal by a thermal stress or generation | occurrence | production of the crack in the junction part of a connection terminal and mounting object is suppressed. Thereby, there exists an advantage by which the connection failure of the semiconductor device 1 is suppressed.

特に、被実装対象2と実装対象3とが相互に異なる線膨張係数を有する場合には、その線膨張係数の差により、BGA接続構造4の接続端子41に熱応力が発生し易い。かかる場合において、上記の構成では、熱応力による接続端子のクラックの発生あるいは接続端子と実装対象との接合部におけるクラックの発生が効果的に抑制される点で有益である。   In particular, when the mounting target 2 and the mounting target 3 have different linear expansion coefficients, thermal stress is likely to occur at the connection terminals 41 of the BGA connection structure 4 due to the difference in the linear expansion coefficients. In such a case, the above configuration is advantageous in that the generation of cracks in the connection terminals due to thermal stress or the generation of cracks in the joints between the connection terminals and the mounting target is effectively suppressed.

また、上記の構成では、前記本体部および前記ガイド部を有する電極パッド(第一電極パッド)43aが用いられることにより、BGA接続構造4の加工工程にて、上記した鼓形状の中央部411およびフィレット形状の接合部412を有する接続端子41を容易かつ少ない工程にて成形できる利点がある。   Further, in the above configuration, by using the electrode pad (first electrode pad) 43a having the main body portion and the guide portion, in the processing step of the BGA connection structure 4, the above-described drum-shaped central portion 411 and There exists an advantage which can shape | mold the connection terminal 41 which has the fillet-shaped junction part 412 easily and with few processes.

また、この半導体装置1では、本体部431およびガイド部432を有する電極パッド(第一電極パッド)43aと、本体部431のみを有する電極パッド(第二電極パッド)43bとの双方が単一の実装対象3上に配列される(図4〜図6参照)。かかる構成では、被実装対象2の実装工程にて、被実装対象2と実装対象3との間隔Hbが第二電極パッド43bの接続端子41により適正かつ安定的に維持されるので、第一電極パッド43aの接続端子41が溶融および凝固するときに、第一電極パッド43aの接続端子41が潰れ難い(図3、図8および図9参照)。これにより、接続端子41の成形が適正に行われて、接続端子41の好適な形状(鼓形状の中央部411およびフィレット形状の接合部412を有する形状)が確保される利点がある(図3(e)および(f)の「a部」参照)。   In the semiconductor device 1, both the electrode pad (first electrode pad) 43 a having the main body portion 431 and the guide portion 432 and the electrode pad (second electrode pad) 43 b having only the main body portion 431 are single. They are arranged on the mounting target 3 (see FIGS. 4 to 6). In such a configuration, the distance Hb between the mounting target 2 and the mounting target 3 is appropriately and stably maintained by the connection terminal 41 of the second electrode pad 43b in the mounting process of the mounting target 2, so that the first electrode When the connection terminal 41 of the pad 43a is melted and solidified, the connection terminal 41 of the first electrode pad 43a is not easily crushed (see FIGS. 3, 8, and 9). Accordingly, there is an advantage that the connection terminal 41 is appropriately formed, and a suitable shape of the connection terminal 41 (a shape having a drum-shaped center portion 411 and a fillet-shaped joint portion 412) is ensured (FIG. 3). (See “a” in (e) and (f)).

[電極パッドの配置例]
なお、この半導体装置1では、第一電極パッド43aおよび第二電極パッド43bが実装対象3に対して以下のように配置されることが好ましい(図6および図7参照)。
[Example of electrode pad arrangement]
In the semiconductor device 1, the first electrode pad 43a and the second electrode pad 43b are preferably arranged as follows with respect to the mounting target 3 (see FIGS. 6 and 7).

例えば、図6に示す構成では、実装対象3が矩形状の接合面(被実装対象2との接合面)を有しており、この接合面の中央部に半導体装置1の信号回路部31が形成されている。そして、この信号回路部31の領域に複数の第一電極パッド43aが配列されている。また、他の領域(信号回路部31の周囲の領域)に複数の第二電極パッド43bが配列されることにより、第一電極パッド43a群の外周が複数の第二電極パッド43bにより囲まれている。   For example, in the configuration illustrated in FIG. 6, the mounting target 3 has a rectangular joint surface (joint surface with the mounted target 2), and the signal circuit unit 31 of the semiconductor device 1 is located at the center of the joint surface. Is formed. A plurality of first electrode pads 43 a are arranged in the area of the signal circuit unit 31. In addition, by arranging the plurality of second electrode pads 43b in other regions (regions around the signal circuit unit 31), the outer periphery of the first electrode pad 43a group is surrounded by the plurality of second electrode pads 43b. Yes.

図6に示す構成では、上記のように、第一電極パッド43aが本体部431およびガイド部432を有することにより、接続端子41の中央部411が鼓形状に形成されて、接続端子41と第一電極パッド43aとの接合部付近に生ずる熱応力が低減される(図2〜図5参照)。したがって、かかる第一電極パッド43aが実装対象3の信号回路部31に配置されることにより、被実装対象2と実装対象3との接続不良や接続端子41と第一電極パッド43aとの接合部付近におけるクラックの発生が抑制される。これにより、BGA接続構造の信頼性が向上する利点がある。   In the configuration shown in FIG. 6, as described above, the first electrode pad 43 a includes the main body portion 431 and the guide portion 432, whereby the central portion 411 of the connection terminal 41 is formed in a drum shape, Thermal stress generated in the vicinity of the joint with the one electrode pad 43a is reduced (see FIGS. 2 to 5). Therefore, when the first electrode pad 43a is arranged in the signal circuit unit 31 of the mounting target 3, the connection failure between the mounting target 2 and the mounting target 3 and the joint between the connection terminal 41 and the first electrode pad 43a. Occurrence of cracks in the vicinity is suppressed. Thereby, there exists an advantage which the reliability of a BGA connection structure improves.

また、図6に示す構成では、実装対象3の接合面にて、第一電極パッド43a群の外周が複数の第二電極パッド43bにより囲まれるので、第一電極パッド43aの接続端子41が溶融および凝固するときに、被実装対象2と実装対象3との間隔Ha、Hbが適正に確保される(図3、図8および図9参照)。これにより、接続端子41の成形が適正に行われて、接続端子41の好適な形状(鼓形状の中央部411およびフィレット形状の接合部412を有する形状)が確保される利点がある。   Moreover, in the structure shown in FIG. 6, since the outer periphery of the first electrode pad 43a group is surrounded by the plurality of second electrode pads 43b at the joint surface of the mounting target 3, the connection terminal 41 of the first electrode pad 43a is melted. When solidifying, the distances Ha and Hb between the mounted object 2 and the mounted object 3 are ensured appropriately (see FIGS. 3, 8, and 9). Thereby, there exists an advantage by which shaping | molding of the connection terminal 41 is performed appropriately and the suitable shape (shape which has the center part 411 of a drum shape and the joint part 412 of a fillet shape) of the connection terminal 41 is ensured.

また、例えば、図7に示す構成では、複数の第一電極パッド43aが実装対象3の外周対角部に配置されている。具体的には、実装対象3が矩形状の接合面を有し、その長手方向の両端部および四隅の領域に複数の第一電極パッド43aが配置されている。また、他の領域(実装対象3の中央部の領域)には、第二電極パッド43bのみが配置されている。   Further, for example, in the configuration shown in FIG. 7, the plurality of first electrode pads 43 a are arranged on the outer peripheral diagonal portion of the mounting target 3. Specifically, the mounting target 3 has a rectangular bonding surface, and a plurality of first electrode pads 43a are disposed in both end portions and four corner regions in the longitudinal direction. In addition, only the second electrode pad 43b is arranged in the other region (the central region of the mounting target 3).

BGA接続構造の加工工程では、実装対象3の外周部に最も大きな熱応力が作用する。したがって、図7に示す構成では、複数の第一電極パッド43aが実装対象3の外周対角部に配置されることにより、接続端子41と第一電極パッド43aとの接合部付近に生ずる熱応力が低減される。これにより、被実装対象2と実装対象3との接続不良や接続端子41と第一電極パッド43aとの接合部付近におけるクラックの発生が抑制されて、BGA接続構造の信頼性が向上する利点がある。   In the processing step of the BGA connection structure, the largest thermal stress acts on the outer peripheral portion of the mounting target 3. Therefore, in the configuration shown in FIG. 7, the plurality of first electrode pads 43 a are arranged on the outer peripheral diagonal portion of the mounting target 3, thereby causing thermal stress generated in the vicinity of the joint portion between the connection terminal 41 and the first electrode pad 43 a. Is reduced. As a result, the connection failure between the mounted object 2 and the mounted object 3 and the occurrence of cracks in the vicinity of the joint between the connection terminal 41 and the first electrode pad 43a are suppressed, and the advantage of improving the reliability of the BGA connection structure is obtained. is there.

[電極パッドの変形例]
また、この半導体装置1では、第一電極パッド43aの本体部431が円形状(円盤状)を有しており、また、そのガイド部432が本体部431に対して所定間隔を隔てつつ本体部431の外周を囲んで配置される環状構造を有し、その一部にて連結部433を介して本体部431に連結されている(図4参照)。かかる構成では、ガイド部432が環状構造を有するので、ハンダ溶融ステップにて溶融した接続端子41の一部がガイド部432にガイドされたときに、このガイドされた接続端子41の一部がガイド部432の周方向に濡れ広がる(図3(e)参照)。したがって、溶融した接続端子41が第一電極パッド43a(ガイド部432)の外部にはみ出し難い。これにより、隣り合う接続端子41の絶縁状態が確保される利点がある。
[Modification of electrode pad]
In the semiconductor device 1, the main body portion 431 of the first electrode pad 43 a has a circular shape (disc shape), and the guide portion 432 is spaced from the main body portion 431 by a predetermined distance. It has the annular structure arrange | positioned surrounding the outer periphery of 431, and is connected with the main-body part 431 through the connection part 433 in the one part (refer FIG. 4). In such a configuration, since the guide portion 432 has an annular structure, when a part of the connection terminal 41 melted in the solder melting step is guided by the guide portion 432, a part of the guided connection terminal 41 is guided. It spreads wet in the circumferential direction of the portion 432 (see FIG. 3E). Therefore, it is difficult for the molten connection terminal 41 to protrude outside the first electrode pad 43a (guide portion 432). Thereby, there exists an advantage by which the insulation state of the adjacent connection terminal 41 is ensured.

しかし、これに限らず、この半導体装置1では、第一電極パッド43aのガイド部432が本体部431から突出した島状形状を有しても良い(図12および図13参照)。   However, the present invention is not limited thereto, and in this semiconductor device 1, the guide portion 432 of the first electrode pad 43a may have an island shape protruding from the main body portion 431 (see FIGS. 12 and 13).

例えば、図12に示す構成では、第一電極パッド43aのガイド部432が略円弧状(半円弧状)の島状形状を有し、本体部431に対して所定間隔を隔てつつ本体部431の外周に配置されている。また、ガイド部432が本体部431に対して連結部433を介して連結されている。また、図13に示す構成では、第一電極パッド43aのガイド部432が略四角形の島状形状を有し、本体部431に対して所定間隔を隔てつつ本体部431の外周に配置されている。また、ガイド部432が本体部431に対して連結部433を介して連結されている。   For example, in the configuration shown in FIG. 12, the guide portion 432 of the first electrode pad 43 a has a substantially arc-shaped (semi-arc-shaped) island shape, and the main body portion 431 is spaced apart from the main body portion 431 by a predetermined distance. It is arranged on the outer periphery. Further, the guide part 432 is connected to the main body part 431 via a connecting part 433. In the configuration shown in FIG. 13, the guide portion 432 of the first electrode pad 43 a has a substantially rectangular island shape, and is arranged on the outer periphery of the main body portion 431 with a predetermined interval from the main body portion 431. . Further, the guide part 432 is connected to the main body part 431 via a connecting part 433.

かかる構成では、ガイド部432が島状形状を有するので、ガイド部432が本体部431の全周を囲む環状構造を有する構成(図4参照)と比較して、第一電極パッド43aの全幅が小さい。これにより、配列された第一電極パッド43a群のピッチ寸法を狭くできる利点がある。なお、ガイド部432が所定の面積を有することにより、必要十分な量の接続端子41を本体部431の外部に流動させ得る。   In such a configuration, since the guide portion 432 has an island shape, the overall width of the first electrode pad 43a is smaller than the configuration in which the guide portion 432 has an annular structure surrounding the entire circumference of the main body portion 431 (see FIG. 4). small. Thereby, there exists an advantage which can narrow the pitch dimension of the arranged 1st electrode pad 43a group. In addition, since the guide part 432 has a predetermined area, a necessary and sufficient amount of the connection terminals 41 can flow outside the main body part 431.

なお、これらに限らず、第一電極パッド43aのガイド部432の形状は、接続端子41の溶融時にて接続端子41の一部を本体部431の外周にガイドする作用が確保されることを条件として、任意に選択され得る。   Note that the shape of the guide portion 432 of the first electrode pad 43a is not limited to these, provided that the operation of guiding a part of the connection terminal 41 to the outer periphery of the main body portion 431 is ensured when the connection terminal 41 is melted. Can be arbitrarily selected.

[電極パッドの径]
また、この半導体装置1では、被実装対象2と実装対象3とが相互に異なる靭性を有するときに、より低い靭性を有する側の電極パッドの径φDaと、より高い靭性を有する側の電極パッドの径φDbとがφDa>φDbの関係を有することが好ましい。なお、第一電極パッド43aの径は、電極パッド43aの本体部431の径である。
[Electrode pad diameter]
Further, in this semiconductor device 1, when the mounted object 2 and the mounted object 3 have different toughnesses, the electrode pad diameter φDa on the side having lower toughness and the electrode pad on the side having higher toughness. The diameter φDb preferably has a relationship of φDa> φDb. The diameter of the first electrode pad 43a is the diameter of the main body 431 of the electrode pad 43a.

例えば、この実施の形態では、被実装対象2がセラミックス製の基板から成り、実装対象3が樹脂材料製の基板から成ることにより、被実装対象2の靭性が実装対象3の靭性よりも低く設定されている(図14参照)。また、低い靭性を有する側(被実装対象2)の電極パッド42の径φDaが高い靭性を有する側(実装対象3)の電極パッド43の径φDbよりも大きく(φDa>φDb)設定されている。このため、低い靭性を有する側における電極パッド42と接続端子41との接合面積が、高い靭性を有する側における電極パッド43と接続端子41との接合面積よりも大きくなっている。なお、一般に、熱応力によるクラックは、より低い靭性を有する側における電極パッド42にて発生し易い。   For example, in this embodiment, the to-be-mounted object 2 is made of a ceramic substrate, and the to-be-mounted object 3 is made of a resin material substrate, so that the toughness of the to-be-mounted object 2 is set lower than the toughness of the mounted object 3. (See FIG. 14). Further, the diameter φDa of the electrode pad 42 on the side having low toughness (mounting target 2) is set larger than the diameter φDb of the electrode pad 43 on the side having high toughness (mounting target 3) (φDa> φDb). . For this reason, the bonding area between the electrode pad 42 and the connection terminal 41 on the side having low toughness is larger than the bonding area between the electrode pad 43 and the connection terminal 41 on the side having high toughness. In general, cracks due to thermal stress are likely to occur at the electrode pad 42 on the side having lower toughness.

かかる構成では、熱履歴により被実装対象2および実装対象3が熱変形したときに、低い靭性を有する側の電極パッド42が大きな径φDa(大きな接合面)を有するので、この電極パッド42に作用する熱応力が緩和される。これにより、接続端子41と被実装対象2との接合部におけるクラックの発生が抑制される利点がある。   In such a configuration, when the mounted object 2 and the mounted object 3 are thermally deformed due to the thermal history, the electrode pad 42 on the side having low toughness has a large diameter φDa (large bonding surface), and thus acts on the electrode pad 42. Thermal stress to be relieved. Thereby, there exists an advantage by which generation | occurrence | production of the crack in the junction part of the connecting terminal 41 and the to-be-mounted object 2 is suppressed.

なお、上記の構成では、さらに、第一電極パッド43aと第二電極パッド43bとの双方が被実装対象2および実装対象3間に配列されることが好ましい(図15参照)。かかる構成では、被実装対象2の実装工程にて、被実装対象2と実装対象3との間隔Hdが第二電極パッド43bの接続端子41により適正かつ安定的に維持されるので、第一電極パッド43aの接続端子41が溶融および凝固するときに、第一電極パッド43aの接続端子41が潰れにくい。これにより、接続端子41の成形が適正に行われて、接続端子41の好適な形状(鼓形状の中央部411およびフィレット形状の接合部412を有する形状)が確保される利点がある。   In the above configuration, it is preferable that both the first electrode pad 43a and the second electrode pad 43b are arranged between the mounted object 2 and the mounted object 3 (see FIG. 15). In such a configuration, since the distance Hd between the mounting target 2 and the mounting target 3 is properly and stably maintained by the connection terminal 41 of the second electrode pad 43b in the mounting process of the mounting target 2, the first electrode When the connection terminal 41 of the pad 43a is melted and solidified, the connection terminal 41 of the first electrode pad 43a is not easily crushed. Thereby, there exists an advantage by which shaping | molding of the connection terminal 41 is performed appropriately and the suitable shape (shape which has the center part 411 of a drum shape and the joint part 412 of a fillet shape) of the connection terminal 41 is ensured.

以上のように、この発明にかかる半導体装置およびその製造方法は、熱応力によるクラックの発生を抑制できる点で有用である。   As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful in that generation of cracks due to thermal stress can be suppressed.

1 半導体装置、2 被実装対象、21 半導体素子、22 回路基板、23 信号回路、24 キャップ、3 実装対象、31 信号回路部、4 BGA接続構造、41 接続端子、42 電極パッド、43a 第一電極パッド、43b 第二電極パッド、44 クリームハンダ、411 中央部、412 接合部、431 本体部、432 ガイド部
、433 連結部
DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Mounting object, 21 Semiconductor element, 22 Circuit board, 23 Signal circuit, 24 Cap, 3 Mounting object, 31 Signal circuit part, 4 BGA connection structure, 41 Connection terminal, 42 Electrode pad, 43a 1st electrode Pad, 43b second electrode pad, 44 cream solder, 411 center part, 412 joint part, 431 body part, 432 guide part, 433 connecting part

Claims (8)

アレイ状あるいはランダム状に配列された複数の接続端子を介して被実装対象が実装対象に実装される半導体装置であって、
前記実装対象側に複数の電極パッドを形成する手段と、前記接続端子を前記電極パッド上にて溶融および凝固させて前記実装対象に結合する手段とを備え、且つ、
一部の前記電極パッドが、前記接続端子の凝固形状を規定する本体部と、前記接続端子の溶融時にて前記接続端子の一部を前記本体部の外周にガイドするガイド部とを有することを特徴とする半導体装置。
A semiconductor device in which a mounting target is mounted on a mounting target via a plurality of connection terminals arranged in an array or randomly,
Means for forming a plurality of electrode pads on the mounting object side, and means for melting and solidifying the connection terminal on the electrode pad to couple to the mounting object; and
Some of the electrode pads include a main body part that defines a solidification shape of the connection terminal, and a guide part that guides a part of the connection terminal to the outer periphery of the main body part when the connection terminal is melted. A featured semiconductor device.
前記本体部および前記ガイド部を有する前記電極パッドと、前記本体部のみを有する前記電極パッドとの双方が単一の前記実装対象上に配列される請求項1に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein both the electrode pad having the main body part and the guide part and the electrode pad having only the main body part are arranged on a single mounting target. 前記本体部および前記ガイド部を有する前記電極パッドが前記実装対象の信号回路部に配置される請求項1または2に記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode pad having the main body portion and the guide portion is arranged in the signal circuit portion to be mounted. 前記本体部および前記ガイド部を有する前記電極パッドが前記実装対象の外周対角部に配置される請求項1〜3のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode pad having the main body portion and the guide portion is disposed on an outer peripheral diagonal portion to be mounted. 前記ガイド部が前記本体部に対して所定間隔を隔てつつ前記本体部の外周を囲んで配置される環状構造を有すると共に一部にて前記本体部に連結される請求項1〜4のいずれか一つに記載の半導体装置。   The said guide part has either the cyclic structure arrange | positioned surrounding the outer periphery of the said main-body part at predetermined intervals with respect to the said main-body part, and is connected with the said main-body part in part. The semiconductor device according to one. 前記ガイド部が前記本体部から突出した島状形状を有する請求項1〜5のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the guide portion has an island shape protruding from the main body portion. 前記被実装対象側に複数の電極パッドを形成する手段を備え、且つ、
前記被実装対象と前記実装対象とが相互に異なる靭性を有するときに、低い靭性を有する側の前記電極パッドの径φDaと高い靭性を有する側の前記電極パッドの径φDbとがφDa>φDbの関係を有する請求項1〜6のいずれか一つに記載の半導体装置。
Means for forming a plurality of electrode pads on the mounting target side; and
When the mounting target and the mounting target have different toughnesses, the diameter φDa of the electrode pad on the side having low toughness and the diameter φDb of the electrode pad on the side having high toughness satisfy φDa> φDb The semiconductor device according to claim 1, which has a relationship.
アレイ状あるいはランダム状に配列された複数の接続端子を介して被実装対象を実装対象に実装する半導体装置の製造方法であって、
前記実装対象側に複数の電極パッドが形成されるステップと、前記接続端子が前記電極パッド上にて溶融および凝固することにより前記実装対象に結合されるステップとを備え、且つ、
一部の前記電極パッドが、前記接続端子の凝固形状を規定する本体部と、前記接続端子の溶融時にて前記接続端子の一部を前記本体部の外周にガイドするガイド部とを有することを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device, wherein a mounting target is mounted on a mounting target via a plurality of connection terminals arranged in an array or at random,
A step of forming a plurality of electrode pads on the mounting target side, and a step of coupling the mounting terminal to the mounting target by melting and solidifying on the electrode pad, and
Some of the electrode pads include a main body part that defines a solidification shape of the connection terminal, and a guide part that guides a part of the connection terminal to the outer periphery of the main body part when the connection terminal is melted. A method of manufacturing a semiconductor device.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016100515A (en) * 2014-11-25 2016-05-30 アイシン精機株式会社 substrate
JP2020057725A (en) * 2018-10-03 2020-04-09 キヤノン株式会社 Printed circuit board and electronic apparatus
US11217545B2 (en) 2019-06-20 2022-01-04 Samsung Electronics Co., Ltd. Semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016100515A (en) * 2014-11-25 2016-05-30 アイシン精機株式会社 substrate
JP2020057725A (en) * 2018-10-03 2020-04-09 キヤノン株式会社 Printed circuit board and electronic apparatus
US11217545B2 (en) 2019-06-20 2022-01-04 Samsung Electronics Co., Ltd. Semiconductor package

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