JP2007243106A - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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Publication number
JP2007243106A
JP2007243106A JP2006067289A JP2006067289A JP2007243106A JP 2007243106 A JP2007243106 A JP 2007243106A JP 2006067289 A JP2006067289 A JP 2006067289A JP 2006067289 A JP2006067289 A JP 2006067289A JP 2007243106 A JP2007243106 A JP 2007243106A
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semiconductor chip
heat spreader
solder
semiconductor
package substrate
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Toshinao Sato
稔尚 佐藤
Hideaki Yoshimura
英明 吉村
Kenji Fukusono
健治 福園
Masateru Koide
正輝 小出
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To surely prevent failure generation in the case of the soldering operation of a heat spreader concerning a semiconductor package structure. <P>SOLUTION: The semiconductor package structure is provided with a semiconductor chip 2 mounted on a package substrate 1 and a heat spreader 3 soldered to an opposite face to the circuit face of the semiconductor 2. A frame-shaped solder dam 4 surrounding a region including the semiconductor chip 2 from a plane view is formed on a junction surface between the heat spreader 3 and the semiconductor chip 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体パッケージ構造に関するものである。   The present invention relates to a semiconductor package structure.

半導体チップのヒートシンク面にヒートスプレッダをはんだ付けした半導体パッケージ構造としては、特許文献１に記載されたものが知られている。この従来例において、放熱部材（ヒートスプレッダ）には基板（パッケージ基板）上に実装される半導体チップへの接合部が形成され、該接合部上に供給されたリフロー用はんだをリフローして半導体チップにはんだ付けされる。
特開平５-１８３０７６号公報 As a semiconductor package structure in which a heat spreader is soldered to a heat sink surface of a semiconductor chip, the one described in Patent Document 1 is known. In this conventional example, a joining portion to a semiconductor chip mounted on a substrate (package substrate) is formed on a heat radiating member (heat spreader), and reflow solder supplied onto the joining portion is reflowed to form a semiconductor chip. Soldered.
JP-A-5-183076

しかし、上述した従来例において、ヒートスプレッダと半導体チップとの接合境界における空隙の発生を防止し、伝熱抵抗を可及的に低くするために十分な量のはんだを供給しようとすると、リフロー時のパッケージ基板側へのはんだ流出が生じ、パッケージ基板上のパターンショート、パッケージ基板に実装されている他の電子部品の短絡等を引き起こす虞がある。   However, in the above-described conventional example, if an attempt is made to supply a sufficient amount of solder to prevent the generation of voids at the boundary between the heat spreader and the semiconductor chip and to reduce the heat transfer resistance as much as possible, Solder may flow out to the package substrate side, which may cause a pattern short on the package substrate, a short circuit of other electronic components mounted on the package substrate, or the like.

とりわけ、リフロー用はんだにはんだシートを使用する場合、リフロー工程時の加熱によるヒートスプレッダの膨張によってはんだシート内に発生した大きな内圧が溶融とともに一気に解放されるために、溶融はんだは急速に周囲に広がり、パッケージ基板側に流出して上述した問題を発生させる。   In particular, when using a solder sheet for the reflow solder, the large internal pressure generated in the solder sheet due to the expansion of the heat spreader due to heating during the reflow process is released at once with melting, so the molten solder spreads rapidly around the periphery, It flows out to the package substrate side and causes the above-mentioned problem.

本発明は、以上の欠点を解消すべくなされたものであって、ヒートスプレッダのはんだ付け作業時における不良発生を確実に防止することのできる半導体パッケージ構造の提供を目的とする。   The present invention has been made to solve the above-described drawbacks, and an object of the present invention is to provide a semiconductor package structure capable of reliably preventing the occurrence of defects during soldering work of a heat spreader.

半導体パッケージはパッケージ基板１上に実装される半導体チップ２と、半導体チップ２からの発熱を放熱して半導体チップ２を冷却するヒートスプレッダ３とを有する。半導体チップ２のパッケージ基板１への実装は、フリップ実装のみならず、ＡＢＧＡ（Advanced Ball Grid Array）等のキャビティダウン型のワイヤボンディング、あるいはＴＢＧＡ（Tape Ball Grid Array）等のテープボンディング実装等であってもよく、テープボンディング実装の場合には、パッケージ基板１としてＴＡＢテープが使用される。   The semiconductor package includes a semiconductor chip 2 mounted on the package substrate 1 and a heat spreader 3 that radiates heat generated from the semiconductor chip 2 and cools the semiconductor chip 2. The mounting of the semiconductor chip 2 on the package substrate 1 is not only flip mounting but also cavity down type wire bonding such as ABGA (Advanced Ball Grid Array) or tape bonding mounting such as TBGA (Tape Ball Grid Array). In the case of tape bonding mounting, a TAB tape is used as the package substrate 1.

ヒートスプレッダ３を半導体チップ２に接合する際に、半導体チップ２とヒートスプレッダ３との境界に十分な量のはんだを供給してリフローすると、溶融はんだは気相との間に適宜のフィレットを形成しながらヒートスプレッダ３と半導体チップ２との界面上を流動する。ヒートスプレッダ３上に形成されたはんだダム４は、ヒートスプレッダ３表面における溶融はんだの流動域を制限し、結果、パッケージ基板１上での流動域が規制される。   When joining the heat spreader 3 to the semiconductor chip 2 and supplying a sufficient amount of solder to the boundary between the semiconductor chip 2 and the heat spreader 3 and reflowing, the molten solder forms an appropriate fillet between the vapor phase It flows on the interface between the heat spreader 3 and the semiconductor chip 2. The solder dam 4 formed on the heat spreader 3 restricts the flow area of the molten solder on the surface of the heat spreader 3, and as a result, the flow area on the package substrate 1 is restricted.

このため、パッケージ基板１上での受動部品等の他の電子部品実装域、あるいは露出配線パターン域等の短絡危険領域へのはんだの流入を確実に防止することが可能になる。   For this reason, it becomes possible to reliably prevent the solder from flowing into other electronic component mounting areas such as passive components on the package substrate 1 or short circuit risk areas such as exposed wiring pattern areas.

本発明によれば、ヒートスプレッダのはんだ付け作業時における不良発生を確実に防止することができる。   According to the present invention, it is possible to reliably prevent the occurrence of defects during the soldering operation of the heat spreader.

図１にＦＣＢＧＡ（フリップチップボールグリッドアレイ）パッケージとして構成された本発明の実施の形態を示す。図１において１は有機基板材料、あるいはガラスセラミックにより形成されるパッケージ基板、２はこのパッケージ基板１の中央部に実装される半導体チップである。   FIG. 1 shows an embodiment of the present invention configured as an FCBGA (Flip Chip Ball Grid Array) package. In FIG. 1, reference numeral 1 is a package substrate formed of an organic substrate material or glass ceramic, and 2 is a semiconductor chip mounted at the center of the package substrate 1.

パッケージ基板１のチップ搭載面には図外の接続ランドと、パターン配線が形成されるとともに、裏面には、上記ランド、あるいはパターン配線と図外のビア、あるいは内層配線を介して接続される接続用バンプ１ａの多数がマトリクス状に配置される。このパッケージ基板１の表面は、必要に応じて、電気的接続部を除いて全面に渡り絶縁皮膜が施される。   Connection land and pattern wiring outside the figure are formed on the chip mounting surface of the package substrate 1, and connection connected to the back surface or the pattern wiring via vias or inner wiring outside the figure on the back surface. A large number of bumps 1a are arranged in a matrix. If necessary, the surface of the package substrate 1 is provided with an insulating film over the entire surface except for the electrical connection portion.

また、パッケージ基板１のチップ搭載面は、半導体チップ２に加えて、例えば当該半導体チップ２に構築された回路とのインタフェイス回路の一部を構成する抵抗、コンデンサ等の受動素子を中心とする電子部品５が実装される。   In addition to the semiconductor chip 2, the chip mounting surface of the package substrate 1 is centered on passive elements such as resistors and capacitors that form part of an interface circuit with a circuit constructed on the semiconductor chip 2, for example. An electronic component 5 is mounted.

さらに、パッケージ基板１のチップ搭載面には、半導体チップ２、および電子部品５の搭載エリアを囲むように枠形状のスティフナ６が固定される。スティフナ６はパッケージ基板１の反り等の有害な変形、あるいはパッケージへの外力負荷時の破断を防止するための補剛、補強体として使用され、パッケージ基板１と熱膨張率が近いＣｕ、あるいはステンレス鋼が使用される。   Further, a frame-shaped stiffener 6 is fixed to the chip mounting surface of the package substrate 1 so as to surround the mounting area of the semiconductor chip 2 and the electronic component 5. The stiffener 6 is used as a stiffening or reinforcing body to prevent harmful deformation such as warpage of the package substrate 1 or breakage when an external force is applied to the package. Cu or stainless steel having a thermal expansion coefficient close to that of the package substrate 1 is used. Steel is used.

半導体チップ２は、回路形成面に形成された電極２ａを利用してパッケージ基板１上の接続ランドに接続される。電極材料には、Ｓｎ-Ａｇ、あるいはＰｂ-Ｐｂはんだが使用される。   The semiconductor chip 2 is connected to a connection land on the package substrate 1 using an electrode 2a formed on the circuit formation surface. Sn-Ag or Pb-Pb solder is used as the electrode material.

パッケージ基板１への接合部の防食、塵埃等の付着による短絡を防止するために、電極２ａのパッケージ基板１への接合部には絶縁性を有するアンダーフィル樹脂７が充填される。アンダーフィル樹脂７には、エポキシを主成分とする熱膨張率１５００〜２０００ｐｐｍ／℃程度の合成樹脂が使用される。   In order to prevent corrosion at the joint portion to the package substrate 1 and to prevent a short circuit due to adhesion of dust or the like, the joint portion of the electrode 2a to the package substrate 1 is filled with insulating underfill resin 7. For the underfill resin 7, a synthetic resin having a thermal expansion coefficient of about 1500 to 2000 ppm / ° C. containing epoxy as a main component is used.

また、半導体チップ２の回路形成面の反対面には、はんだ濡れ性を高めて後述するヒートスプレッダ３とのはんだ接合状態を良好にするために、メタライズ処理を施して金属層が形成される。メタライズは、ウエハプロセス内でＣｕ、Ａｕ等を成膜することにより行うことができるが、この実施の形態においては、まず、ウエハ表面に密着金属として５０００（Å）程度の膜厚でＴｉ層を形成し、次いで、０．３（μｍ）程度の膜厚のＡｕ層を形成して構成される。   In addition, a metal layer is formed on the surface opposite to the circuit formation surface of the semiconductor chip 2 by performing a metallization process in order to improve solder wettability and improve a solder joint state with a heat spreader 3 described later. Metallization can be performed by depositing Cu, Au, or the like in the wafer process. In this embodiment, first, a Ti layer having a film thickness of about 5000 (Å) is formed on the wafer surface as an adhesion metal. Then, an Au layer having a thickness of about 0.3 (μm) is formed.

３はヒートスプレッダであり、熱伝導性能の良好な材料により形成される。ヒートスプレッダ３は、Ｃｕ、Ａｌ、あるいはこれをベースにした複合材料により形成することができるが、この実施の形態では無酸素銅が使用される。このヒートスプレッダ３には、後述するはんだリフロー処理工程における内部空間での容積変化によるパッケージ基板１、半導体チップ２への応力発生を防止するために、内部空間を外気に開放するための空気孔３ａが開設される。   Reference numeral 3 denotes a heat spreader, which is formed of a material having good heat conduction performance. The heat spreader 3 can be formed of Cu, Al, or a composite material based on this, but oxygen-free copper is used in this embodiment. The heat spreader 3 has an air hole 3a for opening the internal space to the outside air in order to prevent the generation of stress on the package substrate 1 and the semiconductor chip 2 due to a change in volume in the internal space in a solder reflow process described later. Established.

また、ヒートスプレッダ３を上記半導体チップ２のメタライズ処理面にはんだ付けするために、ヒートスプレッダ３のはんだ付け面にははんだ濡れ性の向上のためのメタライズ処理が施される。ヒートスプレッダ３の材料に無酸素銅が使用されるこの実施の形態において、メタライズ処理は、図２（ｂ）に示すように、表層に膜厚３μｍ程度のＮｉ層３ｂ、および０．３μｍ程度のＡｕ層３ｃを電解メッキにより成膜して行われる。   Further, in order to solder the heat spreader 3 to the metallized surface of the semiconductor chip 2, the soldered surface of the heat spreader 3 is subjected to metallization for improving solder wettability. In this embodiment in which oxygen-free copper is used as the material of the heat spreader 3, the metallization process is performed as follows. As shown in FIG. 2B, the Ni layer 3b having a thickness of about 3 μm and Au having a thickness of about 0.3 μm are formed on the surface layer. The layer 3c is formed by electrolytic plating.

さらに、上記ヒートスプレッダ３のメタライズ処理面にははんだダム４が形成される。はんだダム４は、はんだ濡れ性の悪い材料をメタライズ処理面の最表層に配置することによって溶融はんだの流動域を制限し、結果、パッケージ基板１上での流動域を制限する。図１に示すように、はんだダム４は、Ｎｉメッキ層によりヒートスプレッダ３を矩形に囲って形成されるが、図２（ｂ）に示すように、Ｎｉメッキ層３ｂとＡｕメッキ層３ｃによるメタライズ処理を行う場合には、Ａｕメッキ層３ｃをエッチングにより除去し、あるいはマスキングにより積層しないようにしてＮｉメッキ層３ｂを露出させることにより形成することもできる。   Further, a solder dam 4 is formed on the metallized surface of the heat spreader 3. The solder dam 4 restricts the flow region of the molten solder by disposing a material having poor solder wettability on the outermost layer of the metallized surface, and consequently restricts the flow region on the package substrate 1. As shown in FIG. 1, the solder dam 4 is formed by surrounding the heat spreader 3 in a rectangular shape with a Ni plating layer, but as shown in FIG. 2B, a metallization process with the Ni plating layer 3b and the Au plating layer 3c is performed. In the case of performing the above, the Au plating layer 3c may be removed by etching, or the Ni plating layer 3b may be exposed without being laminated by masking.

はんだダム４の形成領域は、はんだダム４により囲まれた領域内に充填されるはんだと、半導体チップ２、およびヒートスプレッダ３との接合面積が可及的に大きくなり、かつ、パッケージ基板１上の電子部品５がはんだの表面張力により決定されるフィレット形成域の外側に位置することとなるように設定される。したがって、はんだダム４は、図１に示すように、半導体チップ２の周囲をほぼ対称に囲む以外に、空気孔３ａ、電子部品５の配置により、図２（ａ）に示すように、非対称に半導体チップ２を囲むように形成することもできる。   The solder dam 4 is formed in a region where the solder filled in the region surrounded by the solder dam 4, the bonding area between the semiconductor chip 2 and the heat spreader 3 is as large as possible, and on the package substrate 1. The electronic component 5 is set so as to be located outside the fillet forming area determined by the surface tension of the solder. Accordingly, the solder dam 4 has an asymmetric shape as shown in FIG. 2A due to the arrangement of the air holes 3a and the electronic components 5, in addition to surrounding the periphery of the semiconductor chip 2 almost symmetrically as shown in FIG. It can also be formed so as to surround the semiconductor chip 2.

図３に以上のように構成される半導体パッケージの製造方法を示す。図３（ａ）に示すように、パッケージ製造に際して、まず、パッケージ基板１上にスティフナ６を固定する。スティフナ６の固定には、エポキシ系の接着シート材料が使用される。接着厚を均一化するため、接着材料にはガラス繊維や無機フィラーが含まれている。   FIG. 3 shows a method for manufacturing a semiconductor package configured as described above. As shown in FIG. 3A, when manufacturing a package, first, a stiffener 6 is fixed on the package substrate 1. An epoxy adhesive sheet material is used for fixing the stiffener 6. In order to make the bonding thickness uniform, the bonding material contains glass fibers and inorganic fillers.

次いで、図３（ｂ）に示すように、パッケージ基板１上に半導体チップ２と電子部品５を実装する。半導体チップ２のパッケージ基板１上へのフリップチップ実装は、半導体チップ２に形成される電極を２３０℃から２５０℃程度でリフローして行われる。   Next, as shown in FIG. 3B, the semiconductor chip 2 and the electronic component 5 are mounted on the package substrate 1. The flip chip mounting of the semiconductor chip 2 on the package substrate 1 is performed by reflowing the electrodes formed on the semiconductor chip 2 at about 230 ° C. to 250 ° C.

この後、図３（ｃ）に示すように、フリップチップ実装面にアンダーフィル樹脂７を充填し、硬化させる。アンダーフィル樹脂７は、硬化完了後、１５０℃程度の温度でキュアされる。   Thereafter, as shown in FIG. 3C, the flip chip mounting surface is filled with an underfill resin 7 and cured. The underfill resin 7 is cured at a temperature of about 150 ° C. after the completion of curing.

次いで、図３（ｄ）に示すように、メタライズ処理面間にはんだシートを介装させて半導体チップ２上にヒートスプレッダ３を載置し、はんだシート８’を２３５℃から２５５℃程度の温度でリフローする。必要に応じ、スティフナ６とヒートスプレッダ３との境界には接着シート等が介装される。   Next, as shown in FIG. 3D, a heat spreader 3 is placed on the semiconductor chip 2 with a solder sheet interposed between the metallized surfaces, and the solder sheet 8 ′ is placed at a temperature of about 235 ° C. to 255 ° C. Reflow. If necessary, an adhesive sheet or the like is interposed at the boundary between the stiffener 6 and the heat spreader 3.

リフロー炉内で溶融したはんだ８は、はんだダム４により囲まれた領域内で流動して半導体チップ２とヒートスプレッダ３を接合する。溶融はんだの流動域がはんだダム４により制限されているために、はんだは不用意にパッケージ基板１上の短絡危険域に侵入することがない。   The solder 8 melted in the reflow furnace flows in a region surrounded by the solder dam 4 and joins the semiconductor chip 2 and the heat spreader 3. Since the flow area of the molten solder is limited by the solder dam 4, the solder does not inadvertently enter the short circuit danger area on the package substrate 1.

この後、パッケージ基板１の裏面側に、上記ヒートスプレッダ３を接合しているはんだ８より低融点のはんだボールを供給した後、リフローして接続用バンプ１ａを形成して製造工程が終了する。   Thereafter, a solder ball having a melting point lower than that of the solder 8 to which the heat spreader 3 is bonded is supplied to the back surface side of the package substrate 1 and then reflowed to form the connection bump 1a, thereby completing the manufacturing process.

本発明による半導体パッケージを示す図で、（ａ）は断面図、（ｂ）は（ａ）の１Ｂ-１Ｂ線断面図である。1A and 1B are views showing a semiconductor package according to the present invention, in which FIG. 1A is a cross-sectional view and FIG. 1B is a cross-sectional view taken along line 1B-1B in FIG. 図１の変形例を示す図で、（ａ）ははんだダムの形成領域の変形例を示す断面図、（ｂ）ははんだダムの変形例を示す断面図である。2A and 2B are cross-sectional views illustrating a modification example of a solder dam formation region, and FIG. 2B is a cross-sectional view illustrating a modification example of the solder dam. 半導体パッケージの製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of a semiconductor package.

符号の説明Explanation of symbols

１ パッケージ基板
２ 半導体チップ
３ ヒートスプレッダ
４ はんだダム 1 Package Substrate 2 Semiconductor Chip 3 Heat Spreader 4 Solder Dam

Claims (4)

パッケージ基板に実装された半導体チップと、
半導体チップの回路面に対する反対面にはんだ付けされるヒートスプレッダとを有し、
前記ヒートスプレッダの半導体チップとの接合面には、平面視において半導体チップを含む領域を包囲する枠形状のはんだダムが形成される半導体パッケージ構造。 A semiconductor chip mounted on a package substrate;
A heat spreader that is soldered to the surface opposite to the circuit surface of the semiconductor chip;
A semiconductor package structure in which a frame-shaped solder dam surrounding a region including a semiconductor chip in a plan view is formed on a joint surface between the heat spreader and the semiconductor chip. 前記はんだダムは、ヒートスプレッダの半導体接合面に膜形成される請求項１記載の半導体パッケージ構造。   The semiconductor package structure according to claim 1, wherein the solder dam is formed on a semiconductor joint surface of a heat spreader. 請求項１または２記載の半導体パッケージ構造を備えた半導体装置を搭載した電子装置。   An electronic device on which a semiconductor device having the semiconductor package structure according to claim 1 is mounted. パッケージ基板上に実装された半導体チップにヒートスプレッダをはんだ付けする工程を有し、
該はんだ付け工程が、ヒートスプレッダの半導体チップへの接合面に形成され、周縁がはんだダムにより囲まれたはんだ供給領域に供給されるはんだをリフローして行われる半導体パッケージの製造方法。


A step of soldering a heat spreader to a semiconductor chip mounted on a package substrate;
A method of manufacturing a semiconductor package, wherein the soldering step is performed by reflowing solder supplied to a solder supply region formed on a bonding surface of a heat spreader to a semiconductor chip and surrounded by a solder dam.


JP2006067289A 2006-03-13 2006-03-13 Semiconductor package structure Withdrawn JP2007243106A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011086700A (en) * 2009-10-14 2011-04-28 Shinko Electric Ind Co Ltd Heat dissipating part
US20130134574A1 (en) * 2011-11-25 2013-05-30 Fujitsu Semiconductor Limited Semiconductor device and method for fabricating the same
WO2020162417A1 (en) * 2019-02-04 2020-08-13 株式会社ソニー・インタラクティブエンタテインメント Electronic apparatus, semiconductor device, insulating sheet, and method for manufacturing semiconductor device
TWI736072B (en) * 2018-12-21 2021-08-11 台灣積體電路製造股份有限公司 Package structure and methods for forming the same
CN115954274A (en) * 2021-10-06 2023-04-11 星科金朋私人有限公司 Package with windowed heat spreader
WO2023103470A1 (en) * 2021-12-10 2023-06-15 云南中宣液态金属科技有限公司 Liquid metal packaging structure for heat dissipation of chip

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011086700A (en) * 2009-10-14 2011-04-28 Shinko Electric Ind Co Ltd Heat dissipating part
US20130134574A1 (en) * 2011-11-25 2013-05-30 Fujitsu Semiconductor Limited Semiconductor device and method for fabricating the same
TWI736072B (en) * 2018-12-21 2021-08-11 台灣積體電路製造股份有限公司 Package structure and methods for forming the same
US11328936B2 (en) 2018-12-21 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of package structure with underfill
WO2020162417A1 (en) * 2019-02-04 2020-08-13 株式会社ソニー・インタラクティブエンタテインメント Electronic apparatus, semiconductor device, insulating sheet, and method for manufacturing semiconductor device
JPWO2020162417A1 (en) * 2019-02-04 2021-12-09 株式会社ソニー・インタラクティブエンタテインメント Manufacturing methods for electronic devices, semiconductor devices, insulating sheets, and semiconductor devices
JP7311540B2 (en) 2019-02-04 2023-07-19 株式会社ソニー・インタラクティブエンタテインメント Electronic device, semiconductor device, insulating sheet, and method for manufacturing semiconductor device
CN115954274A (en) * 2021-10-06 2023-04-11 星科金朋私人有限公司 Package with windowed heat spreader
US20230118190A1 (en) * 2021-10-06 2023-04-20 STATS ChipPAC Pte. Ltd. Package with Windowed Heat Spreader
US11830785B2 (en) * 2021-10-06 2023-11-28 STATS ChipPAC Pte. Ltd. Package with windowed heat spreader
WO2023103470A1 (en) * 2021-12-10 2023-06-15 云南中宣液态金属科技有限公司 Liquid metal packaging structure for heat dissipation of chip

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