JP2010205888A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2010205888A
JP2010205888A JP2009049130A JP2009049130A JP2010205888A JP 2010205888 A JP2010205888 A JP 2010205888A JP 2009049130 A JP2009049130 A JP 2009049130A JP 2009049130 A JP2009049130 A JP 2009049130A JP 2010205888 A JP2010205888 A JP 2010205888A
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Prior art keywords
wiring board
semiconductor device
semiconductor chip
resin
semiconductor
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Japanese (ja)
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Takashi Fujita
貴志 藤田
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Toppan Inc
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Toppan Printing Co Ltd
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Priority to JP2009049130A priority Critical patent/JP2010205888A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device attaining space saving of a packaging area by reducing warpage when packaging without using a warpage straightening tool. <P>SOLUTION: In the semiconductor device, a semiconductor chip 1 is connected with a pad of a wiring board 3 via a solder bump 2. A warpage straightening resin 5 is formed on a part other than a part onto which the semiconductor chip is mounted on a surface of the wiring board on which the semiconductor chip is mounted. The warpage straightening resin is formed such that at least one or more patterns of the warpage straightening resin are formed radially from an end of the semiconductor chip toward an end of the wiring board centering around the semiconductor chip. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、はんだバンプを介して多層配線基板上に半導体チップを実装する半導体装置に関する。   The present invention relates to a semiconductor device for mounting a semiconductor chip on a multilayer wiring board via solder bumps.

半導体チップを多層の配線基板上に実装する方法は、接点数の増大、または、信号遅延の問題により、ワイヤーボンディング接続から、はんだバンプを介するフリップチップ接続に移行してきている。従来のようなコア層を持ち、比較的総厚が厚い多層の配線基板上に半導体チップをフリップチップ接続で実装する場合は、配線基板はそれほど反らないが、総厚が薄い配線基板では、半導体チップ実装のリフロー時に配線基板の絶縁材と半導体チップの面方向の線膨張係数の相異から、リフローの後の冷却時に図２のように配線基板が反ってしまい、実装不良または実装信頼性の低下を引き起こす。   The method of mounting a semiconductor chip on a multilayer wiring board has shifted from wire bonding connection to flip chip connection via solder bumps due to an increase in the number of contacts or signal delay. When a semiconductor chip is mounted on a multilayer wiring board having a core layer as in the past and having a relatively large total thickness by flip chip connection, the wiring board is not so warped, but in a wiring board with a thin total thickness, Due to the difference in linear expansion coefficient between the insulating material of the wiring board and the surface direction of the semiconductor chip during reflow of the semiconductor chip mounting, the wiring board warps as shown in FIG. 2 during cooling after the reflow, resulting in poor mounting or mounting reliability. Cause a decline.

上記実装性、実装信頼性の問題を解決するため、従来、金属性反り矯正用冶具（スティフナ）を配線基板に貼り付け、金属製反り矯正用冶具により反りを低減する方法が提案されている（例えば、特許文献１参照）。   In order to solve the above problems of mounting property and mounting reliability, conventionally, a method has been proposed in which a metal warpage correction jig (stiffener) is attached to a wiring board and the warpage is reduced by a metal warpage correction jig ( For example, see Patent Document 1).

特開平１１−１８６４３８号公報Japanese Patent Laid-Open No. 11-186438

しかし、特許文献１に示すような方法は、配線基板表面における金属製反り矯正用冶具の占有面積が大きく、部品搭載数が限定されるため設計の自由度が大きく制限される。   However, the method shown in Patent Document 1 has a large area occupied by the metal warp correction jig on the surface of the wiring board, and the number of components mounted is limited, so that the degree of freedom in design is greatly limited.

本発明は、上記問題点に鑑み案出されたもので、半導体装置における配線基板の表面面積の省スペース化を図ると共に、半導体チップの配線基板上への実装時の配線基板の反りを小さくすることで、実装性、実装信頼性を向上させる半導体装置を提供することを課題とするものである。   The present invention has been devised in view of the above problems, and it is possible to reduce the surface area of the wiring board in the semiconductor device and to reduce the warping of the wiring board when the semiconductor chip is mounted on the wiring board. Thus, an object of the present invention is to provide a semiconductor device that improves mountability and mounting reliability.

本発明は、上記課題を解決するために、配線基板のパッドにはんだバンプを介して半導体チップを接続した半導体装置であり、前記配線基板の半導体チップが搭載されている側の面に、半導体チップの搭載箇所以外の部分に、反り矯正用樹脂が形成されていることを特徴とする半導体装置である。   In order to solve the above problems, the present invention is a semiconductor device in which a semiconductor chip is connected to a pad of a wiring board via a solder bump, and the semiconductor chip is mounted on the surface of the wiring board on which the semiconductor chip is mounted. The semiconductor device is characterized in that a warping correction resin is formed in a portion other than the mounting portion.

また、本発明は上記の半導体装置であって、上記反り矯正用樹脂が、上記半導体チップを中心とし、上記半導体チップ端部から上記配線基板端部に向けて少なくとも一本以上の上記反り矯正用樹脂のパターンが放射状に形成されていることを特徴とする半導体装置である。   Further, the present invention is the above semiconductor device, wherein the warp correction resin has at least one warp correction centered on the semiconductor chip from the end of the semiconductor chip toward the end of the wiring board. A semiconductor device is characterized in that a resin pattern is formed radially.

また、本発明は上記の半導体装置であって、上記配線基板の厚さが３５０μｍ以下であることを特徴とする半導体装置である。   In addition, the present invention is the semiconductor device described above, wherein the wiring board has a thickness of 350 μm or less.

また、本発明は上記の半導体装置であって、上記反り矯正用樹脂の線膨張係数（Ａ）が上記配線基板の線膨張係数（Ｂ）に対し、Ａ＞Ｂであることを特徴とする半導体装置であ
る。 According to another aspect of the present invention, there is provided the semiconductor device as described above, wherein a linear expansion coefficient (A) of the warpage correcting resin is A> B with respect to a linear expansion coefficient (B) of the wiring board. Device.

また、本発明は上記の半導体装置であって、上記半導体チップの少なくとも１つの角に、上記反り矯正用樹脂が上記半導体チップの角を中心として中心角２７０°の扇状に形成されていることを特徴とする半導体装置である。   Further, the present invention is the above semiconductor device, wherein the warping correction resin is formed in a fan shape with a central angle of 270 ° centered on the corner of the semiconductor chip at at least one corner of the semiconductor chip. This is a featured semiconductor device.

また、本発明は上記の半導体装置であって、上記配線基板の少なくとも一つの角部に、上記反り矯正用樹脂を矩形状に形成し、前記矩形状の反り矯正用樹脂と、上記放射状に形成されたパターンの反り矯正用樹脂とが繋がっていることを特徴とする半導体装置である。   The present invention is also the above semiconductor device, wherein the warp correction resin is formed in a rectangular shape at least at one corner of the wiring board, and the rectangular warp correction resin and the radial shape are formed. The semiconductor device is characterized in that it is connected to the warping correction resin of the pattern.

半導体チップを配線基板へ加熱して接続すると、その後の冷却の際に、配線基板の絶縁材と半導体チップの線膨張係数の違いから、半導体装置に反りを生じる。本発明は、その反りを打ち消すように、配線基板の絶縁材と線膨張係数の異なる反り矯正用樹脂を半導体チップによる配線基板の反りが凸となる表面に、加熱時に形成する。それにより、冷却の際に、反り矯正用樹脂が、配線基板の半導体チップによる反りを相殺する矯正が行われ、半導体装置の反りを低減できる効果がある。   When the semiconductor chip is heated and connected to the wiring substrate, the semiconductor device is warped during the subsequent cooling due to the difference in the coefficient of linear expansion between the insulating material of the wiring substrate and the semiconductor chip. In the present invention, a warping correction resin having a linear expansion coefficient different from that of the insulating material of the wiring board is formed on the surface where the warping of the wiring board by the semiconductor chip becomes convex so as to cancel the warping. Accordingly, during the cooling, the warping correction resin is corrected to offset the warp due to the semiconductor chip of the wiring board, and there is an effect that the warp of the semiconductor device can be reduced.

また、金属製反り矯正用冶具（スティフナ）貼り合せ装置等の設備が必要無いので製造工程が簡略でき、新たに必要になる反り矯正用樹脂を塗布する工程は、半導体チップ封止用のアンダーフィルを注入すべく塗布する装置を兼用して反り矯正用樹脂を塗布することができるので、製造工程が簡略化でき、製造コストを低減できる効果がある。   Also, since there is no need for equipment such as a metal warp correction jig (stiffener) bonding device, the manufacturing process can be simplified, and the newly applied process for applying a warp correction resin is an underfill for semiconductor chip sealing. Since the warping correction resin can be applied also as a device for applying the resin to inject, the manufacturing process can be simplified and the manufacturing cost can be reduced.

加えて、反り矯正用の金属製反り矯正用冶具（スティフナ）を配線基板に設置せず、従来スティフナを設置していた配線基板の表面のスペースを活用できるので、半導体チップの配線基板への設置面積を大幅に増やして半導体チップの実装密度を高くした半導体装置が得られる効果がある。   In addition, metal warp correction jigs (stiffeners) for warp correction are not installed on the wiring board, and the space on the surface of the wiring board on which the conventional stiffeners have been installed can be utilized. There is an effect that a semiconductor device in which the area is greatly increased and the mounting density of the semiconductor chip is increased can be obtained.

本発明の一実施例の、多層配線基板上に反り矯正用樹脂を放射状に形成した半導体装置の上面モデル図である。1 is a top model view of a semiconductor device in which a warp correction resin is radially formed on a multilayer wiring board according to an embodiment of the present invention. 封止用樹脂のみが塗布されている半導体装置の加熱後、熱膨張係数の相異により反りが大きくなった半導体装置の断面モデル図である。FIG. 3 is a cross-sectional model view of a semiconductor device in which warpage is increased due to a difference in thermal expansion coefficient after the semiconductor device to which only the sealing resin is applied is heated. 本発明の実施例の半導体装置の断面モデルである。It is a cross-sectional model of the semiconductor device of the Example of this invention. 本発明の一実施例の平面図（上面図）である。It is a top view (top view) of one example of the present invention. 本発明の一実施例の平面図（上面図）である。It is a top view (top view) of one example of the present invention. 本発明の一実施例の平面図（上面図）である。It is a top view (top view) of one example of the present invention. 本発明の一実施例の平面図（上面図）である。It is a top view (top view) of one example of the present invention.

図１は本発明の半導体装置の実施形態にかかる上面モデル図の一例であり、配線基板３を、多層の配線層と、絶縁樹脂層とソルダーレジストのいずれかで構成し、その配線基板３上に少なくとも１個以上の半導体チップ１を実装する。そして、配線基板３の、半導体チップ１を実装する側の面に、反り矯正用樹脂５を形成する。反り矯正用樹脂５は半導体チップ１を中心として放射状に形成されている。   FIG. 1 is an example of a top model diagram according to an embodiment of a semiconductor device of the present invention. A wiring board 3 is composed of any one of a multilayer wiring layer, an insulating resin layer, and a solder resist. At least one semiconductor chip 1 is mounted. Then, a warping correction resin 5 is formed on the surface of the wiring board 3 on the side where the semiconductor chip 1 is mounted. The warping correction resin 5 is formed radially around the semiconductor chip 1.

多層の配線基板３の厚さは特に限定されるわけではないが、厚さが薄いほど剛性が下がるため、配線基板３の反り低減を効果的に得るためには配線基板３の厚さが３５０μｍ以下であることが特に望ましい。   The thickness of the multilayer wiring board 3 is not particularly limited. However, since the rigidity decreases as the thickness decreases, the thickness of the wiring board 3 is 350 μm in order to effectively reduce the warpage of the wiring board 3. It is particularly desirable that

図２は、配線基板３の上面の電極パッドにはんだバンプ２で半導体チップ１のパッドを接合することで半導体チップ１を配線基板３に実装した半導体装置の図１のＸ−Ｘ’線にそった断面図である。半導体チップ１下の配線基板３との間の空間には封止用樹脂４を注入する。図２の半導体装置の断面図は、封止用樹脂４を硬化した後の状態を示し、反り矯正用樹脂５を形成する以前の状態を示す。この場合、半導体チップ１と配線基板３の線膨張係数差から、半導体装置は半導体チップ１側を凸とした反りを生じる。   FIG. 2 shows a semiconductor device in which the semiconductor chip 1 is mounted on the wiring board 3 by bonding the pads of the semiconductor chip 1 to the electrode pads on the upper surface of the wiring board 3 with solder bumps 2. FIG. A sealing resin 4 is injected into a space between the wiring substrate 3 below the semiconductor chip 1. The sectional view of the semiconductor device in FIG. 2 shows a state after the sealing resin 4 is cured, and shows a state before the warp correction resin 5 is formed. In this case, due to the difference in coefficient of linear expansion between the semiconductor chip 1 and the wiring substrate 3, the semiconductor device is warped with the semiconductor chip 1 side convex.

図３は、更に、反り矯正用樹脂５を半導体チップ１の封止用樹脂４に接して塗布した後に反り矯正用樹脂５を熱硬化させた半導体パッケージを、図１のＸ−Ｘ’線にそった断面で示す図である。本発明における反り矯正用樹脂５の線膨張係数（Ａ）は特に限定されるものではないが、反り矯正用樹脂５は、その線膨張係数（Ａ）と配線基板３の面内の方向への線膨張係数（Ｂ）がＡ＞Ｂの関係となる場合、反り矯正用樹脂５の弾性による反り低減効果に加え、配線基板３の温度が低下した際、線膨張係数差により配線基板３を図２の反りとは逆方向に引っ張る方向に力が働くことによる反り低減効果が加わるため、特に大きい低減効果が得られる。   FIG. 3 further shows a semiconductor package in which the warp correction resin 5 is thermally cured after being applied in contact with the sealing resin 4 of the semiconductor chip 1 as shown in FIG. FIG. The linear expansion coefficient (A) of the warp correction resin 5 in the present invention is not particularly limited. However, the warp correction resin 5 has a linear expansion coefficient (A) and a direction in the plane of the wiring board 3. When the linear expansion coefficient (B) satisfies the relationship of A> B, when the temperature of the wiring board 3 is lowered in addition to the warp reduction effect due to the elasticity of the warping correction resin 5, the wiring board 3 is shown by the difference in linear expansion coefficient Since a warp reduction effect due to a force acting in a direction pulling in a direction opposite to the warp of 2 is added, a particularly great reduction effect is obtained.

配線基板３表面に形成する反り矯正用樹脂５の形成パターンの例について、図１と図４から図７の半導体装置の上面図を用いて説明する。反り矯正用樹脂５が半導体チップ１を中心として、放射状に４方向に形成されているパターンの例を図１と図４に示す。図４では、放射状に形成されている反り矯正用樹脂５が配線基板３に対し水平方向、および垂直方向に形成されている。また、図５には、反り矯正用樹脂５が半導体チップ１を中心として、８方向に形成されている例を示す。すなわち、図４に加えて、反り矯正用樹脂５がさらに４本、配線基板３の対角線方向に形成されている。   An example of the formation pattern of the warp correction resin 5 formed on the surface of the wiring board 3 will be described with reference to the top views of the semiconductor device in FIGS. 1 and 4 to 7. Examples of patterns in which the warp correction resin 5 is formed radially in four directions around the semiconductor chip 1 are shown in FIGS. In FIG. 4, the radially correcting warp correcting resin 5 is formed in the horizontal direction and the vertical direction with respect to the wiring board 3. FIG. 5 shows an example in which the warp correction resin 5 is formed in eight directions around the semiconductor chip 1. That is, in addition to FIG. 4, four more warp correction resins 5 are formed in the diagonal direction of the wiring board 3.

さらに、図６、図７に、配線基板３表面に形成する反り矯正用樹脂５の形成パターンについて、放射状に形成された反り矯正用樹脂５の少なくともどちらか一端に、矩形状もしくは円形状の反り矯正用樹脂５を形成する場合を示す。そうすることで、より大きな反り低減効果が得られる。図６は、半導体チップの角に、反り矯正用樹脂５を半導体チップ１の角を中心として中心角２７０°の扇状に形成した例を示す。また、図７は、配線基板３の角に矩形状の反り矯正用樹脂５を形成し、その矩形状の反り矯正用樹脂５を、半導体チップ１から放射状に形成した反り矯正用樹脂５と繋げて形成するパターンの例を示す。   Further, in FIGS. 6 and 7, regarding the formation pattern of the warp correction resin 5 formed on the surface of the wiring board 3, a rectangular or circular warp is formed on at least one end of the warp correction resin 5 formed radially. The case where the resin 5 for correction is formed is shown. By doing so, a greater warp reduction effect can be obtained. FIG. 6 shows an example in which the warping correction resin 5 is formed in a fan shape with a central angle of 270 ° centered on the corner of the semiconductor chip 1 at the corner of the semiconductor chip. In FIG. 7, a rectangular warp correction resin 5 is formed at the corner of the wiring board 3, and the rectangular warp correction resin 5 is connected to the warp correction resin 5 formed radially from the semiconductor chip 1. An example of a pattern to be formed is shown.

＜第１の実施例＞
本発明の第１の実施例による半導体基板の製造方法を以下に説明する。
（工程１）
多層の配線基板３として、総厚２２０μｍ、絶縁樹脂が線膨張係数が２０ｐｐｍの樹脂を用いて構成した多層の配線基板３を用意した。
を配線基板へ加熱して接続する
（工程２）
次に、この配線基板３の上面の電極パッドに、加熱した半導体チップ１のパッド上のはんだバンプ２を接合する。
（工程３）
次に、封止用樹脂４を毛細管現象を利用し半導体チップ１と配線基板３間に充填し、さらに半導体チップ１の外周部を封止用樹脂４で封止する。
（工程４）
次に、図１に示すように、半導体チップ１の角から、配線基板３の角に向けて対角線方向に反り矯正用樹脂５を塗布し、加熱する。それにより、反り矯正用樹脂５を熱硬化させる。
なお、封止用樹脂４及び反り矯正用樹脂５は、エポキシ系で、線膨張係数が３０ｐｐｍの樹脂を使用した。 <First embodiment>
A method for manufacturing a semiconductor substrate according to the first embodiment of the present invention will be described below.
(Process 1)
As the multilayer wiring board 3, a multilayer wiring board 3 constituted by using a resin having a total thickness of 220 μm and an insulating resin having a linear expansion coefficient of 20 ppm was prepared.
Is connected to the wiring board by heating (step 2)
Next, the solder bump 2 on the pad of the heated semiconductor chip 1 is bonded to the electrode pad on the upper surface of the wiring board 3.
(Process 3)
Next, the sealing resin 4 is filled between the semiconductor chip 1 and the wiring substrate 3 by utilizing a capillary phenomenon, and the outer peripheral portion of the semiconductor chip 1 is sealed with the sealing resin 4.
(Process 4)
Next, as shown in FIG. 1, the warping correction resin 5 is applied diagonally from the corner of the semiconductor chip 1 toward the corner of the wiring substrate 3 and heated. Thereby, the warping correction resin 5 is thermoset.
The sealing resin 4 and the warp correction resin 5 are epoxy resins and have a linear expansion coefficient of 30 ppm.

＜比較例＞
以上の実施例の半導体装置が平面から反る高さは２００μｍあった。一方、比較例として、同じ配線基板３を用いて、反り矯正用樹脂５を形成せず半導体装置を作製した。その半導体装置は、図２のように反った。その配線基板３が平面から反る高さは約４００μｍになった。 <Comparative example>
The height at which the semiconductor device of the above example warps from the plane was 200 μm. On the other hand, as a comparative example, a semiconductor device was manufactured using the same wiring board 3 without forming the warp correction resin 5. The semiconductor device warped as shown in FIG. The height at which the wiring board 3 warps from the plane is about 400 μm.

以上の第１の実施例と比較例の反りの結果を比較すると、第１の実施例では、半導体装置が反る高さが比較例よりも大幅に低減され、半導体装置の平面度を向上できた。半導体チップ１を配線基板３へ加熱してはんだバンプ２を接続すると、その後の冷却の際に、配線基板３の絶縁材と半導体チップ１の線膨張係数の違いから、半導体装置に反りを生じる。第１の実施例は、その反りを打ち消すように、配線基板３の絶縁材と線膨張係数の異なる反り矯正用樹脂５を半導体チップ１による配線基板３の反りが凸となる表面に、加熱時に形成することにより、冷却の際に、反り矯正用樹脂５が、配線基板３の半導体チップ１による反りを相殺させることで半導体装置の反りを低減できた。   Comparing the results of warping of the first example and the comparative example described above, in the first example, the warp height of the semiconductor device is significantly reduced compared to the comparative example, and the flatness of the semiconductor device can be improved. It was. When the semiconductor chip 1 is heated to the wiring board 3 and the solder bumps 2 are connected, the semiconductor device is warped due to the difference in the coefficient of linear expansion between the insulating material of the wiring board 3 and the semiconductor chip 1 during subsequent cooling. In the first embodiment, a warping correction resin 5 having a coefficient of linear expansion different from that of the insulating material of the wiring board 3 is applied to the surface on which the warping of the wiring board 3 by the semiconductor chip 1 becomes convex so as to cancel the warping. By forming, the warp correction resin 5 can reduce the warp of the semiconductor device by offsetting the warp of the wiring substrate 3 by the semiconductor chip 1 during cooling.

本発明を薄型半導体パッケージ基板の樹脂封止に適用することで、半導体チップ１を配線基板３に実装した後の反りを小さくできる半導体パッケージを得ることができる。   By applying the present invention to resin sealing of a thin semiconductor package substrate, a semiconductor package capable of reducing warpage after the semiconductor chip 1 is mounted on the wiring substrate 3 can be obtained.

１・・・半導体チップ
２・・・はんだバンプ
３・・・配線基板
４・・・封止用樹脂
５・・・反り矯正用樹脂 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Solder bump 3 ... Wiring board 4 ... Resin for sealing 5 ... Resin for curvature correction

Claims (6)

配線基板のパッドにはんだバンプを介して半導体チップを接続した半導体装置であり、前記配線基板の半導体チップが搭載されている側の面に、半導体チップの搭載箇所以外の部分に、反り矯正用樹脂が形成されていることを特徴とする半導体装置。   A semiconductor device in which a semiconductor chip is connected to a pad of a wiring board via a solder bump, and a warp correction resin is provided on a surface of the wiring board on which the semiconductor chip is mounted on a portion other than the mounting position of the semiconductor chip. A semiconductor device characterized in that is formed. 請求項１記載の半導体装置であって、前記反り矯正用樹脂が、前記半導体チップを中心とし、前記半導体チップ端部から前記配線基板端部に向けて少なくとも一本以上の前記反り矯正用樹脂のパターンが放射状に形成されていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the warp correction resin includes at least one of the warp correction resins from the end of the semiconductor chip toward the end of the wiring board with the semiconductor chip as a center. A semiconductor device, wherein the pattern is formed in a radial pattern. 請求項１又は２に記載の半導体装置であって、前記配線基板の厚さが３５０μｍ以下であることを特徴とする半導体装置。   3. The semiconductor device according to claim 1, wherein the wiring board has a thickness of 350 [mu] m or less. 請求項１乃至３の何れか一項記載の半導体装置であって、前記反り矯正用樹脂の線膨張係数（Ａ）が前記配線基板の線膨張係数（Ｂ）に対し、Ａ＞Ｂであることを特徴とする半導体装置。   4. The semiconductor device according to claim 1, wherein a linear expansion coefficient (A) of the warping correction resin is A> B with respect to a linear expansion coefficient (B) of the wiring board. 5. A semiconductor device characterized by the above. 請求項１乃至４の何れか一項記載の半導体装置であって、前記半導体チップの少なくとも１つの角に、前記反り矯正用樹脂が前記半導体チップの角を中心として中心角２７０°の扇状に形成されていることを特徴とする半導体装置。   5. The semiconductor device according to claim 1, wherein the warp correction resin is formed in a fan shape with a central angle of 270 ° centering on the corner of the semiconductor chip at at least one corner of the semiconductor chip. 6. A semiconductor device which is characterized by being made. 請求項２記載の半導体装置であって、前記配線基板の少なくとも一つの角部に、前記反り矯正用樹脂を矩形状に形成し、前記矩形状の反り矯正用樹脂と、前記放射状に形成されたパターンの反り矯正用樹脂とが繋がっていることを特徴とする半導体装置。   3. The semiconductor device according to claim 2, wherein the warp correction resin is formed in a rectangular shape at least at one corner of the wiring board, and the rectangular warp correction resin and the radial shape are formed. A semiconductor device characterized by being connected to a resin for correcting pattern warpage.
JP2009049130A 2009-03-03 2009-03-03 Semiconductor device Pending JP2010205888A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013145348A1 (en) * 2012-03-30 2013-10-03 新東工業株式会社 Warp correction device and warp correction method for semiconductor element substrate
CN103430281A (en) * 2011-07-21 2013-12-04 新东工业株式会社 Processing method of substrate for semiconductor elements
US10916578B2 (en) 2018-02-14 2021-02-09 Canon Kabushiki Kaisha Semiconductor apparatus and camera

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103430281A (en) * 2011-07-21 2013-12-04 新东工业株式会社 Processing method of substrate for semiconductor elements
WO2013145348A1 (en) * 2012-03-30 2013-10-03 新東工業株式会社 Warp correction device and warp correction method for semiconductor element substrate
CN103503112A (en) * 2012-03-30 2014-01-08 新东工业株式会社 Warp correction device and warp correction method for semiconductor element substrate
US9136192B2 (en) 2012-03-30 2015-09-15 Sintokogio, Ltd. Warp correction device and warp correction method for semiconductor element substrate
JPWO2013145348A1 (en) * 2012-03-30 2015-12-10 新東工業株式会社 Warpage correction apparatus and warpage correction method for semiconductor element substrate
US9230868B2 (en) 2012-03-30 2016-01-05 Sintokogio, Ltd. Warp correction device and warp correction method for semiconductor element substrate
CN103503112B (en) * 2012-03-30 2016-08-17 新东工业株式会社 The crooked correction equipment of substrates for semiconductor elements and detorsion method
KR101830470B1 (en) 2012-03-30 2018-02-20 신토고교 가부시키가이샤 Warp correction device and warp correction method for semiconductor element substrate
US10916578B2 (en) 2018-02-14 2021-02-09 Canon Kabushiki Kaisha Semiconductor apparatus and camera

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