JP2007188930A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2007188930A
JP2007188930A JP2006003431A JP2006003431A JP2007188930A JP 2007188930 A JP2007188930 A JP 2007188930A JP 2006003431 A JP2006003431 A JP 2006003431A JP 2006003431 A JP2006003431 A JP 2006003431A JP 2007188930 A JP2007188930 A JP 2007188930A
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bga element
wiring board
heat sink
chip
semiconductor chip
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Toshitsune Iijima
利恒 飯嶋
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a semiconductor chip and a BGA element are mounted to a wiring board, and no positional controlling jig to prevent the dislocation of a heat slinger during solidification of an adhesive layer is needed, in a heat slinger mounting process. <P>SOLUTION: The semiconductor device is provided with: a wiring board 10 with external connection terminals 3; at least one BGA element 2 that is mounted to the wiring board; a semiconductor chip 1 connected to the wiring board by flip chip; and a heat sink 4 joined with the BGA element 2 and the semiconductor chip 1. A recess 41 is formed at a joint of the heat sink 4 and the BGA element 2, and the BGA element 2 is partly embedded in the recess 41. In the heat sink mounting process, the recess 41 is provided so that the heat sink 4 is hard to be dislocated during solidification of the adhesive layer, and no positional controlling jig to prevent dislocation during solidification is needed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体チップをフリップチップ接続により配線基板に搭載する半導体パッケージであって、複数のチップコンデンザやＢＧＡ素子が共に搭載されているパッケージオンパッケージ(Package on Package)形態の半導体パッケージに関するものであり、特に半導体チップとＢＧＡ素子を含む半導体パッケージにおいて放熱する必要がある半導体装置及び半導体装置の製造方法に関するものである。   The present invention relates to a semiconductor package in which a semiconductor chip is mounted on a wiring board by flip-chip connection, and relates to a package on package type semiconductor package in which a plurality of chip capacitors and BGA elements are mounted together. In particular, the present invention relates to a semiconductor device that needs to dissipate heat in a semiconductor package including a semiconductor chip and a BGA element, and a method for manufacturing the semiconductor device.

現在、一般的に活用されているマイクロプロセッサ等は膨大な情報を高速に処理する目的でキャッシュメモリなどを成膜工程で１チップ内に内蔵してしまう、いわゆるＳＯＣ（system on Chip）が採用されている。そのため、パッケージ形態としては最も特性を発揮できるシングルチップのフリップチップＢＧＡパッケージが採用されている。ＢＧＡ(Ball Grid Array) パッケージは、１つの半導体チップと１つの配線基板から構成され、配線基板は、裏面に外部接続端子を備えており、半導体チップはこの配線基板に搭載され、且つ樹脂封止されてなるものであり、外部接続端子は、格子状に配列された複数のボールからなる。フリップチップＢＧＡパッケージは、半導体チップが配線基板にフリップチップ接続された構成になっている。   Currently used microprocessors, etc., employ so-called SOC (system on chip), in which a cache memory or the like is built in one chip in the film formation process for the purpose of processing a large amount of information at high speed. ing. Therefore, a single-chip flip chip BGA package that can exhibit the most characteristics is adopted as a package form. The BGA (Ball Grid Array) package is composed of one semiconductor chip and one wiring board, and the wiring board has external connection terminals on the back surface, and the semiconductor chip is mounted on this wiring board and sealed with resin. The external connection terminal is composed of a plurality of balls arranged in a lattice pattern. The flip chip BGA package has a configuration in which a semiconductor chip is flip-chip connected to a wiring board.

しかし、更なる情報量の増大と高速化の要求から成膜工程の微細化が進み、ロジック(Logic) 回路とメモリ(Memory)回路の両立が厳しくなりつつある。またチップサイズも今後増大が見込まれ、チップの歩留まり確保が非常に厳しくなることが予想される。そこで近年ロジック部分とメモリ部分の分割がなされるようになってきた。通常キャッシュメモリなどは、ロジック部品とマザーボードを介してつながれるが、それでは配線長が長くなり過ぎるため高速処理に対応し辛い。そこで、チップからは分離するが、配線長が最短で可能なパッケージオンパッケージ形態の半導体パッケージが提案されている。具体的な形状はガラエポなどを絶縁材料とする配線基板の中央付近にロジックなどの半導体チップがフリップチップ接続で搭載され、その周辺にチップスケールパッケージなどの形態に単体パッケージ化されたメモリＢＧＡパッケージなどが搭載される。以下、この様なパッケージは、ＢＧＡ素子という。更に、配線間の容量の調整でチップコンデンサなどが配線基板の表面あるいは裏面に適宜搭載されている。ここで、中央付近に搭載されるロジックチップは発熱が数１０ワットに達するものがあり、放熱性を確保する目的でＣｕなどにＮｉメッキなどを施した放熱板が低熱抵抗樹脂などの接着剤を介して搭載される。   However, as the amount of information is further increased and the speed is increased, the film forming process is becoming finer, and the compatibility between the logic circuit and the memory circuit is becoming strict. In addition, the chip size is expected to increase in the future, and it is expected that securing the yield of chips will become very severe. Therefore, in recent years, the logic part and the memory part have been divided. Normally, a cache memory or the like is connected to a logic component and a motherboard, but this makes it difficult to handle high-speed processing because the wiring length becomes too long. In view of this, a semiconductor package in a package-on-package form has been proposed which can be separated from the chip but has the shortest wiring length. A specific shape is a memory BGA package in which a semiconductor chip such as logic is mounted by flip chip connection near the center of a wiring board made of insulating material such as glass epoxy, and a single package in the form of a chip scale package around the periphery. Is installed. Hereinafter, such a package is referred to as a BGA element. Furthermore, a chip capacitor or the like is appropriately mounted on the front surface or the back surface of the wiring board by adjusting the capacitance between the wirings. Here, some logic chips mounted near the center generate heat of several tens of watts, and a heat sink with Ni plating or the like applied to Cu or the like has an adhesive such as a low thermal resistance resin for the purpose of ensuring heat dissipation. Mounted through.

また、同一面に搭載されるメモリＢＧＡ素子についても発熱が１０ワット近いものがあり、同様に放熱する必要がある。これらを放熱する放熱構造としては、一般的には中央付近の半導体チップの取り付け高さに対してメモリＢＧＡ素子の方が高いので、半導体チップ上にダミーの板を搭載して半導体チップ裏面とＢＧＡ素子裏面を面一にさせた後に平板状の放熱板を搭載するか、あるいは突起平面のある放熱板を搭載している。半導体チップは、放熱板突起平面に接合される。ここでの問題は、前者の場合は、半導体チップ上に低熱抵抗樹脂層が２箇所あるので、１箇所のみの場合と比較すると放熱性が悪化する。また、後者の場合は、ズレが発生したり、チップサイズが大きくなったり、チップの搭載角度が変わった場合などに突起平面からチップが露出して必要な放熱性を確保できない。特許文献１には、ヒートシンクを取り付けた半導体パッケージが開示されており、ヒートシンクは、熱放散性の高い金属を用いる。ヒートシンクの一面には半導体チップ素子を埋め込むための凹部が設けられている。
特開平３−５８４５５号公報（図１０） Also, there are memory BGA elements mounted on the same surface that generate nearly 10 watts of heat, and it is necessary to dissipate similarly. As a heat dissipation structure for radiating these, the memory BGA element is generally higher than the mounting height of the semiconductor chip near the center. Therefore, a dummy plate is mounted on the semiconductor chip and the backside of the semiconductor chip and the BGA are mounted. A flat heat sink is mounted after the back surface of the element is flushed, or a heat sink with a projection plane is mounted. The semiconductor chip is bonded to the heat sink projection plane. The problem here is that in the former case, since there are two low thermal resistance resin layers on the semiconductor chip, the heat dissipation is deteriorated as compared with the case of only one location. Further, in the latter case, the chip is exposed from the projection plane when the deviation occurs, the chip size is increased, or the mounting angle of the chip is changed, so that necessary heat dissipation cannot be ensured. Patent Document 1 discloses a semiconductor package to which a heat sink is attached, and the heat sink uses a metal having a high heat dissipation property. A recess for embedding the semiconductor chip element is provided on one surface of the heat sink.
Japanese Patent Laid-Open No. 3-58455 (FIG. 10)

本発明は、放熱板搭載プロセスにおいて接着層の固化の際に放熱板がズレる心配が無いので固化中のズレを防止するための位置制御用治具を必要としない、半導体チップとＢＧＡ素子とを配線基板に搭載した半導体装置を提供する。   The present invention eliminates the risk of the heat sink shifting when the adhesive layer is solidified in the heat sink mounting process, and therefore does not require a position control jig for preventing misalignment during solidification. Provided is a semiconductor device mounted on a wiring board.

本発明の半導体装置の一態様は、外部接続端子を有する配線基板と、前記配線基板に搭載された少なくとも１つのＢＧＡ素子と、前記配線基板にフリップチップ接続された半導体チップと、前記ＢＧＡ素子及び前記半導体チップに接合された放熱板とを具備し、前記放熱板の前記ＢＧＡ素子との接合部には凹部が形成され、前記ＢＧＡ素子は、部分的に前記凹部に埋め込まれていることを特徴としている。
また、本発明の半導体装置の製造方法の一態様は、外部接続端子を有する配線基板上に半導体チップをフリップチップ接続する工程と、前記配線基板に少なくとも１つのＢＧＡ素子を前記半導体チップ周辺に搭載する工程と、前記ＢＧＡ素子及び前記半導体チップ上に接着剤を塗布する工程と、前記接着剤が塗布されたＢＧＡ素子を前記放熱板の前記凹部に嵌め込み、これらＢＧＡ素子と前記放熱板とを加圧しながら加熱して接着剤を硬化させる工程とを具備し、前記放熱板の凹部は、前記配線基板上の前記ＢＧＡ素子の位置を所定の位置に配置する位置決め機能を備えていることを特徴としている。 One aspect of the semiconductor device of the present invention includes a wiring board having an external connection terminal, at least one BGA element mounted on the wiring board, a semiconductor chip flip-chip connected to the wiring board, the BGA element, A heat sink that is bonded to the semiconductor chip, wherein a recess is formed at a joint between the heat sink and the BGA element, and the BGA element is partially embedded in the recess. It is said.
According to another aspect of the method for manufacturing a semiconductor device of the present invention, a step of flip-chip connecting a semiconductor chip onto a wiring board having external connection terminals, and mounting at least one BGA element on the wiring board around the semiconductor chip A step of applying an adhesive on the BGA element and the semiconductor chip, and fitting the BGA element coated with the adhesive into the recess of the heat sink, and adding the BGA element and the heat sink. And a step of curing the adhesive by heating while pressing, wherein the recess of the heat radiating plate has a positioning function for arranging the position of the BGA element on the wiring board at a predetermined position. Yes.

本発明は、半導体チップとＢＧＡ素子とを配線基板に搭載した半導体装置において、放熱板搭載プロセスにおいて接着層の固化の際に凹部の存在により放熱板がズレる心配が無いので固化中のズレを防止するための位置制御用治具を必要としない。   The present invention prevents a misalignment during solidification in a semiconductor device in which a semiconductor chip and a BGA element are mounted on a wiring board, since there is no fear that the heat sink is displaced due to the presence of recesses when the adhesive layer is solidified in the heat sink mounting process. This eliminates the need for a position control jig.

本発明の半導体装置は、半導体チップをフリップチップ接続したボールグリッドアレイ（ＢＧＡ）型パッケージで、その配線基板表面や配線基板裏面にチップコンデンザやメモリＢＧＡ素子などのパッケージ形態の部品を搭載しており、その中でもとくにロジックなどの半導体チップとメモリＢＧＡ素子などのパッケージ部品が配線基板の同一面に配置されるように構成されている。半導体チップの放熱と同様にメモリＢＧＡ素子などのパッケージに対しても放熱が必要な製品に対し、１枚の板状の放熱板を取り付けることで両方の放熱を合せ行う構造の場合に、半導体チップに対しては放熱板の平面部分で接着領域が設定され、メモリＢＧＡ素子などのパッケージに対しては放熱板に形成した凹部分にメモリＢＧＡ素子を嵌め込まれるように接着領域が設定されている。この時メモリＢＧＡ素子が嵌め込まれる放熱板の凹部の寸法がメモリＢＧＡ素子のパッケージの外形公差と搭載精度を考慮したうえで決定されているので、この凹部がそのまま放熱板の配線基板に対する位置決め構造になっている。したがって、放熱板搭載プロセスにおいて接着層の固化の際に放熱板がズレる心配が無いので、固化中のズレを防止するための位置制御用治具を必要としない。
以下、実施例を参照して発明の実施の形態を説明する。 The semiconductor device of the present invention is a ball grid array (BGA) type package in which semiconductor chips are flip-chip connected, and package-type components such as a chip condenser and a memory BGA element are mounted on the surface of the wiring substrate and the back surface of the wiring substrate. Among them, in particular, a semiconductor chip such as logic and a package component such as a memory BGA element are arranged on the same surface of the wiring board. In the case of a structure in which both heat dissipation is performed by attaching a single plate-like heat dissipation plate to a product that requires heat dissipation for a package such as a memory BGA element as well as heat dissipation of the semiconductor chip, In contrast, a bonding area is set in a flat portion of the heat sink, and a bonding area is set so that the memory BGA element is fitted into a recess formed in the heat sink for a package such as a memory BGA element. At this time, the size of the recess of the heat sink to which the memory BGA element is fitted is determined in consideration of the package tolerance of the memory BGA element and the mounting accuracy. It has become. Therefore, since there is no fear that the heat radiating plate is displaced when the adhesive layer is solidified in the heat radiating plate mounting process, a position control jig for preventing the displacement during solidification is not required.
Hereinafter, embodiments of the invention will be described with reference to examples.

図１乃至図４を参照して実施例１を説明する。
図１は、この実施例で用いる放熱板の断面図及び凹部が形成された面の平面図、図２は、放熱板を搭載したこの実施例の半導体装置の平面図、図３は、図２のＡ−Ａ′線及びＢ−Ｂ′線に沿う部分の断面図、図４は、この実施例で用いられるＢＧＡ素子の一例を示す断面図である。
図２及び図３に示すように、裏面に外部接続端子であるはんだボール３が格子（グリッド）状に取り付けられた、例えば、５．０ｍｍ角の配線基板１０には中央にＣＰＵなどのロジック回路などが形成されたシリコン半導体などからなるチップ（ロジックチップ）１が搭載され、四隅にはメモリ回路などが形成されたシリコンチップなどが組み込まれたＢＧＡ素子２が搭載され、また複数のチップコンデンサ６がＢＧＡ素子２間に搭載されている。チップコンデンサ６は、配線間容量を調整するために適宜搭載され、配線基板の主面に限らず裏面にも搭載することができる。 The first embodiment will be described with reference to FIGS.
1 is a cross-sectional view of a heat sink used in this embodiment and a plan view of a surface on which a recess is formed. FIG. 2 is a plan view of a semiconductor device of this embodiment on which a heat sink is mounted. FIG. FIG. 4 is a cross-sectional view showing an example of a BGA element used in this embodiment, and FIG. 4 is a cross-sectional view of a portion along the line AA ′ and BB ′.
As shown in FIGS. 2 and 3, a logic circuit such as a CPU is provided in the center of a 5.0 mm square wiring board 10 with solder balls 3 as external connection terminals attached to the back surface in a grid shape. A chip (logic chip) 1 made of a silicon semiconductor or the like on which a semiconductor circuit or the like is formed is mounted, a BGA element 2 in which a silicon chip or the like on which a memory circuit or the like is formed is mounted, and a plurality of chip capacitors 6 are mounted. Is mounted between the BGA elements 2. The chip capacitor 6 is appropriately mounted to adjust the inter-wiring capacitance, and can be mounted not only on the main surface of the wiring board but also on the back surface.

そして、配線基板１０上の半導体チップ１及びＢＧＡ素子２には、共通の放熱板４がエポキシ樹脂などの低熱抵抗樹脂からなる接着剤５により接合されている。この実施例では半導体チップは、１つに限らず複数個搭載することができる。放熱板４とＢＧＡ素子２とは放熱板４に形成された凹部４１において接着剤５を介して当接されている。半導体チップ１は、配線基板１０上の配線（図示しない）にフリップチップ接続されている。半導体チップ１は、外部接続端子１１を有し、外部接続端子１１が接合されている配線基板１０の主面と外部接続端子１１が取り付けられたチップ裏面との間にはエポキシ樹脂などからなるアンダーフィル樹脂１２が充填されている。同様に、ＢＧＡ素子２は、はんだボールなどからなる外部接続端子２５を有し、外部接続端子２５が接合されている配線基板１０の主面と外部接続端子２５が取り付けられた素子裏面との間にはエポキシ樹脂などからなるアンダーフィル樹脂２６が充填されている。更に、配線間の容量調整を行うためにチップコンデンサ６などが配線基板の表面あるいは裏面に適宜搭載されている。   A common heat sink 4 is bonded to the semiconductor chip 1 and the BGA element 2 on the wiring substrate 10 by an adhesive 5 made of a low thermal resistance resin such as an epoxy resin. In this embodiment, not only one semiconductor chip but also a plurality of semiconductor chips can be mounted. The heat sink 4 and the BGA element 2 are brought into contact with each other through an adhesive 5 in a recess 41 formed in the heat sink 4. The semiconductor chip 1 is flip-chip connected to wiring (not shown) on the wiring substrate 10. The semiconductor chip 1 has an external connection terminal 11, and an underlayer made of epoxy resin or the like is provided between the main surface of the wiring substrate 10 to which the external connection terminal 11 is bonded and the back surface of the chip to which the external connection terminal 11 is attached. Fill resin 12 is filled. Similarly, the BGA element 2 has an external connection terminal 25 made of a solder ball or the like. Between the main surface of the wiring board 10 to which the external connection terminal 25 is bonded and the element back surface to which the external connection terminal 25 is attached. Is filled with an underfill resin 26 made of an epoxy resin or the like. Further, a chip capacitor 6 or the like is appropriately mounted on the front surface or the back surface of the wiring board in order to adjust the capacitance between the wirings.

図１に示すように、放熱板１０には４つの凹部４１が設けられている。この凹部４１の底部に接着剤５を塗布してＢＧＡ素子２を固定している。凹部４１には素子上方が埋め込まれているので、機械的強度が向上し、接着剤５が固化した後は多少の外力が加わってもＢＧＡ素子２が配線基板１０から剥がれることは著しく減少する。放熱板１０は、銅やアルミニウム、Ｆｅ−４２Ｎｉ合金、銅の表面にニッケルメッキを施したものなど良熱伝導性材料が用いられる。
図４は、ＢＧＡ素子２の断面構造を示している。ＢＧＡ素子２は、シリコン半導体などの半導体チップ２２と外部接続端子２５を有する配線基板２１とを備えている。半導体チップ２２は、外部端子２３を有し、外部端子２３が接合されている配線基板２１の主面と外部端子２３が取り付けられたチップ裏面との間にはエポキシ樹脂などからなるアンダーフィル樹脂２４が充填されている。外部端子２３は、半導体チップ２２と配線基板２１とを電気的に接続しているが、この両者の間の電気的接続はボンディングワイヤを用いることも可能である。配線基板２１に搭載された半導体チップ２２は搭載後にエポキシ樹脂などの樹脂封止体２７により封止される。 As shown in FIG. 1, the heat sink 10 is provided with four recesses 41. The BGA element 2 is fixed by applying an adhesive 5 to the bottom of the recess 41. Since the upper part of the element is embedded in the recess 41, the mechanical strength is improved, and after the adhesive 5 is solidified, the BGA element 2 is remarkably reduced from being peeled off from the wiring board 10 even if some external force is applied. The heat radiating plate 10 is made of a heat conductive material such as copper, aluminum, Fe-42Ni alloy, or copper plated with nickel.
FIG. 4 shows a cross-sectional structure of the BGA element 2. The BGA element 2 includes a semiconductor chip 22 such as a silicon semiconductor and a wiring substrate 21 having external connection terminals 25. The semiconductor chip 22 has an external terminal 23, and an underfill resin 24 made of an epoxy resin or the like is provided between the main surface of the wiring board 21 to which the external terminal 23 is bonded and the chip back surface to which the external terminal 23 is attached. Is filled. The external terminal 23 electrically connects the semiconductor chip 22 and the wiring substrate 21, but a bonding wire can be used for electrical connection between the two. The semiconductor chip 22 mounted on the wiring substrate 21 is sealed with a resin sealing body 27 such as an epoxy resin after mounting.

次に、この実施例の半導体装置の製造方法を説明する。
まず、外部接続端子であるはんだボール３が裏面に格子状に取り付けられた配線基板１０上の中央部分の配線（図示しない）に半導体チップ１をフリップチップ接続する。次に、配線基板１０に少なくとも１つのＢＧＡ素子（この実施例では４個）２を半導体チップ１の周辺に搭載する。この実施例では、例えば、半導体チップ１には、ロジックチップが用いられる。中央付近に搭載されるロジックチップは発熱が数１０ワットに達するものがあり、放熱性を確保する目的でＣｕなどにＮｉメッキなどを施した放熱板４が低熱抵抗樹脂などの接着剤５を介して搭載される。また、同一配線基板１０の主面に搭載される、例えば、メモリなどに用いられるＢＧＡ素子２についても発熱が１０ワット近いものがあり、同じように放熱する必要がある。ＢＧＡ素子２は、配線基板１０の４つの角部に搭載される。次に、ＢＧＡ素子２及び半導体チップ１の上に接着剤５を塗布する。接着剤５が塗布されたＢＧＡ素子２を放熱板４の凹部４１に嵌め込み、これら半導体チップ１及びＢＧＡ素子２と放熱板４とを加圧しながら加熱して接着剤５を硬化させる。 Next, a method for manufacturing the semiconductor device of this embodiment will be described.
First, the semiconductor chip 1 is flip-chip connected to the wiring (not shown) in the central portion on the wiring substrate 10 in which the solder balls 3 as external connection terminals are attached to the back surface in a grid pattern. Next, at least one BGA element (four in this embodiment) 2 is mounted on the periphery of the semiconductor chip 1 on the wiring board 10. In this embodiment, for example, a logic chip is used as the semiconductor chip 1. Some logic chips mounted near the center generate heat of several tens of watts, and a heat sink 4 in which Ni plating or the like is applied to Cu or the like through an adhesive 5 such as a low thermal resistance resin for the purpose of ensuring heat dissipation. Mounted. Also, for example, the BGA element 2 mounted on the main surface of the same wiring board 10 and used for a memory or the like has a heat generation of nearly 10 watts, and it is necessary to dissipate heat in the same way. The BGA element 2 is mounted on four corners of the wiring board 10. Next, an adhesive 5 is applied on the BGA element 2 and the semiconductor chip 1. The BGA element 2 to which the adhesive 5 has been applied is fitted into the recess 41 of the heat radiating plate 4, and the semiconductor chip 1, the BGA element 2 and the heat radiating plate 4 are heated while being pressed to cure the adhesive 5.

放熱板４の凹部４１の形状寸法は、ＢＧＡ素子２の外形＋ＢＧＡ素子の外形公差＋ＢＧＡ素子の搭載位置精度の計算式を設定して置き、その計算により算出され決定される。そして、放熱板４の凹部４１は、配線基板１０上のＢＧＡ素子２の位置を所定の位置に配置する位置決め機能を備えている。
従来、低熱抵抗樹脂の硬化時に樹脂厚の制御用に錘あるいはそれに類する加圧を行うが、ＢＧＡ素子で位置ズレが防止されるために、この実施例では位置制御用の複雑な治工具を必要としない。また、半導体チップサイズの大型化、半導体チップの長方形化、配置方向の変更（４５度搭載など）があったとしても、ＢＧＡ素子のサイズ、位置が変わらない限り同一の放熱板を使用することが可能とな利、製造工程が簡略化される。 The shape dimension of the recess 41 of the heat sink 4 is determined by calculating and determining a formula for setting the outer shape of the BGA element 2 + the outer tolerance of the BGA element + the mounting accuracy of the BGA element. And the recessed part 41 of the heat sink 4 is equipped with the positioning function which arrange | positions the position of the BGA element 2 on the wiring board 10 in a predetermined position.
Conventionally, a weight or similar pressure is applied to control the resin thickness when curing a low thermal resistance resin, but in order to prevent misalignment of the BGA element, this embodiment requires a complicated jig for position control. And not. Even if the size of the semiconductor chip is increased, the semiconductor chip is made rectangular, the arrangement direction is changed (45 ° mounting, etc.), the same heat dissipation plate can be used as long as the size and position of the BGA element do not change. This makes it possible to simplify the manufacturing process.

次に、図５を参照して実施例２を説明する。
図５は、この実施例で用いる放熱板の断面図及び凹部が形成された面の平面図である。実施例１と同様に、図裏面に外部接続端子（はんだボール）が格子状に取り付けられた、例えば、５．０ｍｍ角の配線基板には中央にＣＰＵなどのロジック回路などが形成されたシリコン半導体などからなるチップ（ロジックチップ）がフリップチップ接続により搭載され、四隅にはメモリ回路などが形成されたシリコンチップが組み込まれたＢＧＡ素子がフリップチップ接続により搭載され、また、複数のチップコンデンサがＢＧＡ素子間に搭載されている。チップコンデンサは、配線間容量を調整するために適宜搭載され、配線基板の主面に限らず裏面にも搭載することができる。そして、配線基板上の半導体チップ及びＢＧＡ素子には、共通の放熱板２０がエポキシ樹脂などの低熱抵抗樹脂からなる接着剤により接合されている。放熱板２０とＢＧＡ素子とは放熱板２０に形成された凹部２８において接着剤を介して当接されている。半導体チップは、外部接続端子を有し、外部接続端子が接合されている配線基板の主面と外部接続端子が取り付けられたチップ裏面との間にはエポキシ樹脂などからなるアンダーフィル樹脂が充填されている。 Next, Example 2 will be described with reference to FIG.
FIG. 5 is a cross-sectional view of a heat sink used in this embodiment and a plan view of a surface on which a recess is formed. As in the first embodiment, external connection terminals (solder balls) are attached in a grid pattern on the back side of the figure. For example, a silicon semiconductor in which a 5.0 mm square wiring board is formed with a logic circuit such as a CPU in the center. A chip (logic chip) composed of, for example, is mounted by flip-chip connection, a BGA element incorporating a silicon chip on which memory circuits are formed is mounted at four corners by flip-chip connection, and a plurality of chip capacitors are mounted by BGA It is mounted between elements. The chip capacitor is appropriately mounted to adjust the capacitance between the wirings, and can be mounted not only on the main surface of the wiring board but also on the back surface. And the common heat sink 20 is joined to the semiconductor chip and BGA element on a wiring board by the adhesive agent which consists of low thermal resistance resins, such as an epoxy resin. The heat sink 20 and the BGA element are in contact with each other through an adhesive in a recess 28 formed in the heat sink 20. The semiconductor chip has external connection terminals, and an underfill resin made of epoxy resin or the like is filled between the main surface of the wiring board to which the external connection terminals are bonded and the chip back surface to which the external connection terminals are attached. ing.

同様に、ＢＧＡ素子は、はんだボールなどからなる外部接続端子を有し、外部接続端子が接合されている配線基板主面と外部接続端子が取り付けられた素子裏面との間にはエポキシ樹脂などからなるアンダーフィル樹脂が充填されている。
図５に示すように、放熱板２０には４つの凹部２８が設けられている。この凹部２８の底部に接着剤を塗布してＢＧＡ素子を固定している。凹部２８には素子上方が埋め込まれているので、機械的強度が向上し、接着剤が固化した後は多少の外力が加わってもＢＧＡ素子が配線基板から剥がれることは減少する。放熱板２０は、銅やアルミニウム、Ｆｅ−４２Ｎｉ合金、銅の表面にニッケルメッキを施したものなど良熱伝導性材料が用いられる。ＢＧＡ素子及び半導体チップの構造は、実施例１と同様である。
この実施例は、放熱板２０の凹部２８の形状に特徴がある。即ち、放熱板２０の４隅に形成されたほぼ正方形の凹部２８の全ての辺２９はテーパ状に形成されている。 Similarly, the BGA element has an external connection terminal made of a solder ball or the like, and an epoxy resin or the like is provided between the main surface of the wiring board to which the external connection terminal is bonded and the element back surface to which the external connection terminal is attached. Underfill resin is filled.
As shown in FIG. 5, the heat sink 20 is provided with four recesses 28. An adhesive is applied to the bottom of the recess 28 to fix the BGA element. Since the upper part of the element is embedded in the recess 28, the mechanical strength is improved, and after the adhesive is solidified, the BGA element is less likely to be peeled off from the wiring board even if some external force is applied. The heat radiating plate 20 is made of a heat-conductive material such as copper, aluminum, Fe-42Ni alloy, or a nickel-plated copper surface. The structures of the BGA element and the semiconductor chip are the same as those in the first embodiment.
This embodiment is characterized by the shape of the recess 28 of the heat sink 20. That is, all the sides 29 of the substantially square recesses 28 formed at the four corners of the heat sink 20 are formed in a tapered shape.

この実施例の半導体装置の製造方法は、基本的には実施例１と同じである。
まず、はんだボールが裏面に格子状に取り付けられた配線基板上の中央部分の配線に半導体チップをフリップチップ接続する。次に、配線基板に４個のＢＧＡ素子を半導体チップの周辺に搭載する。次に、ＢＧＡ素子上及び半導体チップ上に接着剤を塗布する。接着剤が塗布されたＢＧＡ素子を放熱板２０の凹部２８に嵌め込む。このとき、凹部２８のテーパ状の辺２９は、ＢＧＡ素子を凹部２８に嵌め込む際のガイドとして用いられる。その後、これら半導体チップ及びＢＧＡ素子と放熱板２０とを加圧しながら加熱して接着剤を硬化させる。
放熱板２０の凹部２８の形状寸法は、ＢＧＡ素子の外形＋ＢＧＡ素子の外形公差＋ＢＧＡ素子の搭載位置精度の計算式を設定して置き、その計算により算出され決定される。そして、放熱板２０の凹部２８は、配線基板上のＢＧＡ素子の位置を所定の位置に配置する位置決め機能を備えている。 The manufacturing method of the semiconductor device of this embodiment is basically the same as that of the first embodiment.
First, a semiconductor chip is flip-chip connected to a central portion of wiring on a wiring board having solder balls attached to the back surface in a grid pattern. Next, four BGA elements are mounted on the periphery of the semiconductor chip on the wiring board. Next, an adhesive is applied on the BGA element and the semiconductor chip. The BGA element to which the adhesive is applied is fitted into the recess 28 of the heat sink 20. At this time, the tapered side 29 of the recess 28 is used as a guide when the BGA element is fitted into the recess 28. Thereafter, the semiconductor chip and the BGA element and the heat sink 20 are heated while being pressed to cure the adhesive.
The shape and size of the recess 28 of the heat sink 20 is determined by calculating and determining a calculation formula for the outer shape of the BGA element + the outer tolerance of the BGA element + the mounting accuracy of the BGA element. And the recessed part 28 of the heat sink 20 is equipped with the positioning function which arrange | positions the position of the BGA element on a wiring board in a predetermined position.

従来、低熱抵抗樹脂の硬化時に樹脂厚の制御用に錘あるいはそれに類する加圧を行うが、ＢＧＡ素子で位置ズレが防止されるために、この実施例では位置制御用の複雑な治工具を必要としない。また、半導体チップサイズの大型化、半導体チップの長方形化、配置方向の変更（４５度搭載など）があったとしても、ＢＧＡ素子のサイズ、位置が変わらない限り同一の放熱板を使用することが可能とな利、製造工程が簡略化される。また、放熱板の凹部のテーパ状の辺は、凹部の各辺全てに形成してあるので、どの方向からもＢＧＡ素子を凹部に嵌め込むことが容易になる。   Conventionally, a weight or similar pressure is applied to control the resin thickness when curing a low thermal resistance resin, but in order to prevent misalignment of the BGA element, this embodiment requires a complicated jig for position control. And not. Even if the size of the semiconductor chip is increased, the semiconductor chip is made rectangular, the arrangement direction is changed (45 ° mounting, etc.), the same heat dissipation plate can be used as long as the size and position of the BGA element do not change. This makes it possible to simplify the manufacturing process. Further, since the tapered sides of the recesses of the heat sink are formed on all the sides of the recesses, it is easy to fit the BGA element into the recesses from any direction.

次に、図６を参照して実施例３を説明する。
図６は、この実施例で用いる放熱板の断面図及び凹部が形成された面の平面図である。実施例１と同様に、図裏面に外部接続端子（はんだボール）が格子状に取り付けられた、例えば、５．０ｍｍ角の配線基板には中央にＣＰＵなどのロジック回路などが形成されたシリコン半導体などからなるチップ（ロジックチップ）がフリップチップ接続により搭載され、四隅にはメモリ回路などが形成されたシリコンチップが組み込まれたＢＧＡ素子がフリップチップ接続により搭載され、また、複数のチップコンデンサがＢＧＡ素子間に搭載されている。チップコンデンサは、配線間容量を調整するために適宜搭載され、配線基板の主面に限らず裏面にも搭載することができる。そして、配線基板上の半導体チップ及びＢＧＡ素子には、共通の放熱板３０がエポキシ樹脂などの低熱抵抗樹脂からなる接着剤により接合されている。放熱板３０とＢＧＡ素子とは放熱板３０に形成された凹部３１において接着剤を介して当接されている。半導体チップは、外部接続端子を有し、外部接続端子が接合されている配線基板の主面と外部接続端子が取り付けられたチップ裏面との間にはエポキシ樹脂などからなるアンダーフィル樹脂が充填されている。 Next, Example 3 will be described with reference to FIG.
FIG. 6 is a cross-sectional view of the heat sink used in this embodiment and a plan view of the surface on which the recesses are formed. As in the first embodiment, external connection terminals (solder balls) are attached in a grid pattern on the back side of the figure. For example, a silicon semiconductor in which a 5.0 mm square wiring board is formed with a logic circuit such as a CPU in the center. A chip (logic chip) composed of, for example, is mounted by flip-chip connection, a BGA element incorporating a silicon chip on which memory circuits are formed is mounted at four corners by flip-chip connection, and a plurality of chip capacitors are mounted by BGA It is mounted between elements. The chip capacitor is appropriately mounted to adjust the capacitance between the wirings, and can be mounted not only on the main surface of the wiring board but also on the back surface. And the common heat sink 30 is joined to the semiconductor chip and BGA element on a wiring board by the adhesive agent which consists of low thermal resistance resins, such as an epoxy resin. The heat sink 30 and the BGA element are in contact with each other through an adhesive in a recess 31 formed in the heat sink 30. The semiconductor chip has external connection terminals, and an underfill resin made of epoxy resin or the like is filled between the main surface of the wiring board to which the external connection terminals are bonded and the chip back surface to which the external connection terminals are attached. ing.

同様に、ＢＧＡ素子は、はんだボールなどからなる外部接続端子を有し、外部接続端子が接合されている配線基板主面と外部接続端子が取り付けられた素子裏面との間にはエポキシ樹脂などからなるアンダーフィル樹脂が充填されている。
図６に示すように、放熱板３０には４つの凹部３１が設けられている。この凹部３１の底部に接着剤を塗布してＢＧＡ素子を固定している。凹部３１には素子上方が埋め込まれているので、機械的強度が向上し、接着剤が固化した後は多少の外力が加わってもＢＧＡ素子が配線基板から剥がれることは減少する。放熱板３０は、銅やアルミニウム、Ｆｅ−４２Ｎｉ合金、銅の表面にニッケルメッキを施したものなど良熱伝導性材料が用いられる。ＢＧＡ素子及び半導体チップの構造は、実施例１と同様である。 Similarly, the BGA element has an external connection terminal made of a solder ball or the like, and an epoxy resin or the like is provided between the main surface of the wiring board to which the external connection terminal is bonded and the element back surface to which the external connection terminal is attached. Underfill resin is filled.
As shown in FIG. 6, the heat sink 30 is provided with four recesses 31. An adhesive is applied to the bottom of the recess 31 to fix the BGA element. Since the upper part of the element is embedded in the recess 31, the mechanical strength is improved, and after the adhesive is solidified, the BGA element is less likely to be peeled off from the wiring board even if some external force is applied. The heat radiating plate 30 is made of a heat conductive material such as copper, aluminum, Fe-42Ni alloy, or a copper surface plated with nickel. The structures of the BGA element and the semiconductor chip are the same as those in the first embodiment.

この実施例は、放熱板３０の凹部３１の形状に特徴がある。即ち、放熱板３０の４隅に形成されたほぼ正方形の凹部３１の上側及び右側の辺３２がテーパ状に形成され、下側及び左側の辺はテーパ状になっておらず垂直である。
この実施例の半導体装置の製造方法は、基本的には実施例１と同じである。
まず、はんだボールが裏面に格子状に取り付けられた配線基板上の中央部分の配線に半導体チップをフリップチップ接続する。次に、配線基板に４個のＢＧＡ素子を半導体チップの周辺に搭載する。次に、ＢＧＡ素子上及び半導体チップ上に接着剤を塗布する。接着剤が塗布されたＢＧＡ素子を放熱板３０の凹部３１に嵌め込む。このとき、凹部３１のテーパ状の辺３２は、ＢＧＡ素子を凹部３１に嵌め込む際のガイドとして用いられる。その後、これら半導体チップ及びＢＧＡ素子と放熱板３０とを加圧しながら加熱して接着剤を硬化させる。
放熱板３０の凹部３１の形状寸法は、ＢＧＡ素子の外形＋ＢＧＡ素子の外形公差＋ＢＧＡ素子の搭載位置精度の計算式を設定して置き、その計算により算出され決定される。そして、放熱板３０の凹部３１は、配線基板上のＢＧＡ素子の位置を所定の位置に配置する位置決め機能を備えている。 This embodiment is characterized by the shape of the recess 31 of the heat sink 30. That is, the upper and right sides 32 of the substantially square recess 31 formed at the four corners of the heat sink 30 are formed in a taper shape, and the lower and left sides are not tapered and are vertical.
The manufacturing method of the semiconductor device of this embodiment is basically the same as that of the first embodiment.
First, a semiconductor chip is flip-chip connected to a central portion of wiring on a wiring board having solder balls attached to the back surface in a grid pattern. Next, four BGA elements are mounted on the periphery of the semiconductor chip on the wiring board. Next, an adhesive is applied on the BGA element and the semiconductor chip. The BGA element to which the adhesive is applied is fitted into the recess 31 of the heat sink 30. At this time, the tapered side 32 of the recess 31 is used as a guide when the BGA element is fitted into the recess 31. Thereafter, the semiconductor chip, the BGA element, and the heat sink 30 are heated while being pressed to cure the adhesive.
The shape and size of the recess 31 of the heat sink 30 is calculated and determined by setting a formula for calculating the outer shape of the BGA element + the outer tolerance of the BGA element + the mounting position accuracy of the BGA element. And the recessed part 31 of the heat sink 30 is equipped with the positioning function which arrange | positions the position of the BGA element on a wiring board in a predetermined position.

従来、低熱抵抗樹脂の硬化時に樹脂厚の制御用に錘あるいはそれに類する加圧を行うが、ＢＧＡ素子で位置ズレが防止されるために、この実施例では位置制御用の複雑な治工具を必要としない。また、半導体チップサイズの大型化、半導体チップの長方形化、配置方向の変更（４５度搭載など）があったとしても、ＢＧＡ素子のサイズ、位置が変わらない限り同一の放熱板を使用することが可能とな利、製造工程が簡略化される。また、放熱板の凹部は同じ部分の辺がテーパ状になっているので、所定の方向からガイドによりＢＧＡ素子を凹部に嵌め込むことができるので、この嵌め込みが容易になる。   Conventionally, a weight or similar pressure is applied to control the resin thickness when curing a low thermal resistance resin, but in order to prevent misalignment of the BGA element, this embodiment requires a complicated jig for position control. And not. Even if the size of the semiconductor chip is increased, the semiconductor chip is made rectangular, the arrangement direction is changed (45 ° mounting, etc.), the same heat dissipation plate can be used as long as the size and position of the BGA element do not change. This makes it possible to simplify the manufacturing process. In addition, since the side of the same portion of the recess of the heat sink is tapered, the BGA element can be fitted into the recess by a guide from a predetermined direction, so that the fitting is facilitated.

本発明の一実施例である実施例１で用いる放熱板の断面図及び凹部が形成された面の平面図。Sectional drawing of the heat sink used in Example 1 which is one Example of this invention, and the top view of the surface in which the recessed part was formed. 本発明の一実施例である実施例１で用いる放熱板を搭載した半導体装置の透視平面図。The perspective top view of the semiconductor device carrying the heat sink used in Example 1 which is one Example of this invention. 図２のＡ−Ａ′線及びＢ−Ｂ′線に沿う部分の断面図。Sectional drawing of the part which follows the AA 'line and BB' line of FIG. 本発明の一実施例である実施例１で用いられるＢＧＡ素子の一例を示す断面図。Sectional drawing which shows an example of the BGA element used in Example 1 which is one Example of this invention. 本発明の一実施例である実施例２で用いる放熱板の断面図及び凹部が形成された面の平面図。Sectional drawing of the heat sink used in Example 2 which is one Example of this invention, and the top view of the surface in which the recessed part was formed. 本発明の一実施例である実施例３で用いる放熱板の断面図及び凹部が形成された面の平面図。Sectional drawing of the heat sink used in Example 3 which is one Example of this invention, and the top view of the surface in which the recessed part was formed.

符号の説明Explanation of symbols

１、２２・・・半導体チップ
２・・・ＢＧＡ素子
３・・・外部接続端子（はんだボール）
４、２０、３０・・・放熱板
５・・・接着剤
６・・・チップコンデンサ
１０、２１・・・配線基板
１１、２５・・・外部接続端子
１２、２４、２６・・・アンダーフィル樹脂
２３・・・外部端子
２７・・・樹脂封止体
２８、３１、４１・・・放熱板の凹部
２９、３２・・・凹部のテーパ状の辺

1, 22 ... Semiconductor chip 2 ... BGA element 3 ... External connection terminal (solder ball)
4, 20, 30 ... radiator plate 5 ... adhesive 6 ... chip capacitor 10, 21 ... wiring board 11, 25 ... external connection terminal 12, 24, 26 ... underfill resin 23 ... External terminal 27 ... Resin sealing body 28, 31, 41 ... Recessed part of heat sink 29, 32 ... Tapered side of recessed part

Claims (5)

外部接続端子を有する配線基板と、
前記配線基板に搭載された少なくとも１つのＢＧＡ素子と、
前記配線基板にフリップチップ接続された半導体チップと、
前記ＢＧＡ素子及び前記半導体チップに接合された放熱板とを具備し、
前記放熱板の前記ＢＧＡ素子との接合部には凹部が形成され、前記ＢＧＡ素子は、部分的に前記凹部に埋め込まれていることを特徴とする半導体装置。 A wiring board having external connection terminals;
At least one BGA element mounted on the wiring board;
A semiconductor chip flip-chip connected to the wiring board;
A heat sink bonded to the BGA element and the semiconductor chip;
The semiconductor device is characterized in that a concave portion is formed in a joint portion between the heat radiating plate and the BGA element, and the BGA element is partially embedded in the concave portion. 前記配線基板上には複数の前記半導体チップが配置されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein a plurality of the semiconductor chips are arranged on the wiring board. 前記配線基板上には少なくとも１つの電子部品が搭載されていることを特徴とする請求項１又は請求項２に記載の半導体装置。 The semiconductor device according to claim 1, wherein at least one electronic component is mounted on the wiring board. 前記放熱板の前記凹部は、少なくとも１つの側面がテーパ状に形成されていることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein at least one side surface of the concave portion of the heat radiating plate is formed in a tapered shape. 5. 外部接続端子を有する配線基板上に半導体チップをフリップチップ接続する工程と、
前記配線基板に少なくとも１つのＢＧＡ素子を前記半導体チップ周辺に搭載する工程と、
前記ＢＧＡ素子及び前記半導体チップ上に接着剤を塗布する工程と、
前記接着剤が塗布されたＢＧＡ素子を前記放熱板の前記凹部に嵌め込み、これらＢＧＡ素子と前記放熱板とを加圧しながら加熱して接着剤を硬化させる工程とを具備し、
前記放熱板の凹部は、前記配線基板上の前記ＢＧＡ素子の位置を所定の位置に配置する位置決め機能を備えていることを特徴とする半導体装置の製造方法。

A step of flip-chip connecting a semiconductor chip on a wiring board having external connection terminals;
Mounting at least one BGA element on the wiring substrate around the semiconductor chip;
Applying an adhesive on the BGA element and the semiconductor chip;
Fitting the BGA element coated with the adhesive into the recess of the heat sink, heating the BGA element and the heat sink while applying pressure, and curing the adhesive;
The method of manufacturing a semiconductor device, wherein the recess of the heat radiating plate has a positioning function for arranging the position of the BGA element on the wiring board at a predetermined position.

JP2006003431A 2006-01-11 2006-01-11 Semiconductor device and method of manufacturing the same Pending JP2007188930A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011514594A (en) * 2008-02-28 2011-05-06 インターナショナル・ビジネス・マシーンズ・コーポレーション Data center, variable flow computer cooling system for data center, and method of operation
CN104332414A (en) * 2014-04-09 2015-02-04 珠海越亚封装基板技术股份有限公司 Embedded chip manufacture method
KR20170062100A (en) * 2015-11-27 2017-06-07 삼성전자주식회사 Method for manufacturing semiconductor package having heat slug and method for manufacturing heat slug

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011514594A (en) * 2008-02-28 2011-05-06 インターナショナル・ビジネス・マシーンズ・コーポレーション Data center, variable flow computer cooling system for data center, and method of operation
CN104332414A (en) * 2014-04-09 2015-02-04 珠海越亚封装基板技术股份有限公司 Embedded chip manufacture method
TWI625839B (en) * 2014-04-09 2018-06-01 Embedded chip manufacturing method
KR20170062100A (en) * 2015-11-27 2017-06-07 삼성전자주식회사 Method for manufacturing semiconductor package having heat slug and method for manufacturing heat slug
KR102437565B1 (en) * 2015-11-27 2022-08-29 삼성전자주식회사 Method for manufacturing semiconductor package having heat slug and method for manufacturing heat slug

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