US20090302414A1 - Trench isolation for reduced cross talk - Google Patents

Trench isolation for reduced cross talk Download PDF

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Publication number
US20090302414A1
US20090302414A1 US12/523,786 US52378608A US2009302414A1 US 20090302414 A1 US20090302414 A1 US 20090302414A1 US 52378608 A US52378608 A US 52378608A US 2009302414 A1 US2009302414 A1 US 2009302414A1
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Prior art keywords
trenches
wafer
trench
substrate
barriers
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US12/523,786
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Thorbjörn Ebefors
Tomas Bauer
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Silex Microsystems AB
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Silex Microsystems AB
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Assigned to SILEX MICROSYSTEMS AB reassignment SILEX MICROSYSTEMS AB ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAUER, TOMAS, EBEFORS, THORBJORN
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
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Definitions

  • the present invention relates to design of micro electronic devices where e.g. both analogue and digital units are to be located in close proximity on substrates such as micro chips.
  • it relates to means and methods for eliminating or at least reducing so called cross-talk between analogue/digital components on the same substrate.
  • Capactive crosstalk can e.g. occur when digital signals are run near analog signals, the capacitance between the lines can cause the lines to couple and the signals become blurred due to coupling through the substrate underneath.
  • the digital return currents return ground through a non-zero impedance, due to either resistive or inductive effects, which can cause the local “ground” to move up and down with the currrent. If this ground differs from the originator of the signal, this will cause voltage differences at the rate of the bits. This problem can be eliminated by improving grounding, or by understanding and controlling the paths that ground current flows in.
  • Some of the major problems induced by digital to analog and analog to analog cross talk are (1) high speed digital clocks cause severe interference with RF or IF front ends; (2) in digital portables, time-division-multiple-access (TDMA) may be used and power on/off cycles happen fairly frequently, causing additional transient noise on the power and ground planes; (3) in frequency division duplex systems, as well as in pixel based imaging devices, high-power transmit signals cause interference with weak receive signals since separation by filters is limited; (4) the leakage of the amplifier output to the input may cause the amplifier to oscillate.
  • TDMA time-division-multiple-access
  • a critical requirement for the development of low cost, wide-bandwidth telecommunications equipment is the close integration of both digital and analog microelectronic components.
  • the physical interface between an IC and its environment is the IC package, and its performance is severely tested by the high speed and high frequencies encountered in wide-bandwidth systems.
  • Single chip mixed signal ICs that combine directly both high frequency analog and high speed digital sub-sections will require proper electromagnetic understanding of capacitive, inductive, and radiative coupling between components, and their impact on high sensitivity analog sub-circuits.
  • Crosstalk and interference between devices in mixed signal ICs can be reduced when SOI wafers are used due to the isolation of devices from the substrate.
  • counter junction doping which entails reverse biased layers to prevent cross talk through the common substrate on which components are provided in combination with large physical separation between analogue and digital parts.
  • the latter is of course limiting on the possibilities to reduce component size, which is disadvantageous.
  • Another approach is to use SOI substrates to bring about dielectric isolation/insulation across the substrate.
  • a still further prior art solution is to combine use of SOI and non-wafer through trenches.
  • the usage of such trenches are well known in IC industry but then the normal approach is to make the trenches as a last step in the processing.
  • Starting substrates (trench first approach) with filled isolated trenches through a device layer on an SOI wafer with limited trench depth are commercially available from for example IceMOS (Northern Ireland, United Kingdom; www.icemostech.com).
  • IceMOS Northern Ireland, United Kingdom; www.icemostech.com
  • the general problem with this type of solution is that trenches must be narrow enough to be able to be filled.
  • the DeepReactive Ion Etching (DRIE) method often referred to as the Bosch process used to etch the trenches gives a practical maximum aspect ratio of about 1:40.
  • the present invention sets out to provide starting substrates for mixed analogue/digital designs, wherein the cross talk between components of such designs is eliminated or at least substantially reduced.
  • the invention provides a starting substrate for mixed analogue/digital designs, comprising isolated substrate parts wherein the isolated parts are separated by insulating trench structures, as defined in claim 1 .
  • an interposer substrate for e.g. wafer level flip-chip mounting of mixed analogue/digital devices such as ASICs, defined in claim 15 .
  • FIG. 1 is a schematic illustration of the inventive concept
  • FIG. 2 a schematically shows cutting pattern for obtaining a chip shown in FIG. 2 b;
  • FIG. 2 b illustrates a single chip
  • FIG. 3 schematically illustrates a mounted multi-chip component implementing the invention
  • FIG. 4 is a cross-section at B-B in FIG. 3 ;
  • FIG. 5 schematically illustrates an array of imaging devices interconnected with ASICs and/or other electronic components, using the invention
  • FIG. 6 illustrates an array of closed packed vias
  • FIG. 7 shows etch load compensation at corners
  • FIG. 8 shows a via/trench structure with redundancy
  • FIG. 9 schematically shows an implementation of the invention.
  • Capactive crosstalk when digital signals are run near analog signals, the capacitance between the lines can cause the lines to couple and the signals become blurred due to coupling through the substrate underneath. This problem can be eliminated by running the analog signals in a separate routing area than the digital, and by putting grounding shields between the analog and the digital.
  • the invention can be represented by the structure shown in FIG. 1 .
  • It comprises a wafer 1 of e.g. silicon, although a number of other semi-conductor materials are possible.
  • the wafer has two areas A 1 and A 2 , respectively, separated from each other by a barrier of insulating material 2 extending through the wafer and enclosing one area A 2 .
  • the wafer should be thicker than about 300 ⁇ m in order to provide enough rigidity to enable handling of the wafer during processing without risk of breaking it.
  • the thickness is >400 ⁇ m, most preferred >500 82 m.
  • This substrate could be used for making a device wherein there is provided electronics generating RF signals in partition A 2 , and digital electronics in partition A 1 , essentially without any interfering cross-talk between the partitions occurring.
  • the barriers can be made using the method for etching deep trenches disclosed in the above mentioned WO 2004/084300.
  • FIG. 2 a illustrates a part of a wafer 1 having such barriers L laid out in lines extending across the wafer. Cutting of the wafer along the broken lines C after suitable processing to provide some electronic structure thereon (not shown) would yield individual chips 3 with a lay-out of insulating barriers L as shown in FIG. 2 b, wherein the three separated areas B 1 , B 2 , B 3 are insulated form each other and will efficiently prevent cross-talk between the areas.
  • B 1 could e.g. be used for RF electronics, B 2 for digital logics and B 3 for analogue electronics.
  • FIG. 3 an interposer with mounted chips is schematically illustrated in a top view, wherein the invention has been implemented in the interposer chip 30 on which a mixed analouge-digital ASIC 31 has been mounted.
  • the ASIC is only shown schematically with a contour line.
  • any type of electronic component can be used, although below reference is made to ASICs.
  • an input device such as a pixel based image device 32 , e.g a camera chip, has been mounted.
  • This device is shown schematically with a broken contour line.
  • solder bumps SB are also shown in the figure. These solder bumps are each associated with an output pad related to a pixel element on the image device 32 (not shown in FIG. 3 ). Most of the output pads are uniformly distributed in a large array configuration.
  • the pixel elements are connected via the solder bumps and routing structures 35 to one via each (not shown), to couple the signal through the interposer such that the image device 32 and the ASIC 31 can be connected as described more in detail below.
  • the interposer 30 comprises a plurality of electrical through connections (vias), indicated with reference numeral 33 .
  • the vias are distributed over the entire surface of the interposer 30 , except in the digital “island” 39 . These vias are used for coupling signals to and from the ASIC 31 and the image device 32 through the wafer.
  • the metal routing on both sides of interposer 30 means that the position of output pads on imaging device 32 must not necessarily match those on the ASIC 31 (this is referred to as redistribution with “fan in/fan out” of routings).
  • connections between the vias 33 and the ASIC 31 is via contact bumps 34 on bottom surface of the ASIC and routing structures 35 suitably in the form of narrow metallizations on the interposer 30 .
  • the bumps 34 are shown to be elliptical only for the purpose of distinguishing them from the vias in the figure. Only a few of the routings 35 have been indicated for clarity.
  • DIGITAL and 39 In the part of the interposer labelled DIGITAL and 39 (separated from the part labelled ANALOGUE by means of the barriers 38 , see further below) there are arranged a plurality of “I/O” bumps 36 . These bumps are connected to external control devices (not shown) for digital control of the ASIC 31 . Routing metallizations 35 connect the bumps 36 to the contact bumps 34 on the ASIC 31 .
  • the digital signals have a high frequency and are represented by voltage pulses with a very steep rising flank, and will very easily couple into the analogue parts of the device (“cross-talk”), through the substrate, if there are no effective barriers against such cross-talk.
  • the interposer 30 also comprises a barrier 38 of insulating material extending all the way through the wafer and laid out in a pattern so as to separate two partitions on the wafer.
  • the barriers are 3-30 ⁇ m wide (in the plane of the wafer).
  • the barriers are 5-15 ⁇ m wide, and a common width is about 8 ⁇ m.
  • This barrier effectively shields the enclosed area (“digital ground”) 39 from cross-talk between components in two different areas.
  • the analogue I/O part ANALOGUE is effectively shielded against interfering signals from the digital I/O part DIGITAL, and the digital routing on the ASIC into the digital area on the ASIC overlaying with the digital isolated island 39 on the interposer.
  • interposer chips are created on wafer level, and on each interposer, an ASIC has been mounted by wafer level assembly using e.g. pick and-place flip-chip soldering before cutting.
  • FIG. 4 shows a cross-section through A-A in FIG. 3 .
  • the same reference numerals as in FIG. 3 will be used for like elements. It should be noted that only details of the structure are shown for clarity. Also, the figure is not to scale. Thus, there are numerous via structures in a device like this only three of which are shown. Also, there is a plurality of solder bumps on the image device, only three of which are shown.
  • the interposer 30 made from a silicon wafer comprises a plurality of electrical through connections (“vias”) 33 , only three of which are shown with broken lines.
  • vias can be made by a method disclosed in applicants own WO 04/084300 mentioned earlier. These vias are used to interconnect the ASIC 31 and the image device 32 .
  • the vias are made according to WO 04/084300 in a process comprising two general steps, namely provision of trenches and introducing insulating material into the grooves, and optionally filling the trenches, at least partially with oxide.
  • the starting material is a conducting or a semiconductor wafer, suitably a silicon wafer (although there are no specific limitations on the materials used), having a thickness of 500 ⁇ m, although the thickness can vary between 300 ⁇ m and 1000 ⁇ m.
  • Most commercially available silicon (or other semi-conductor) wafers are about 300-1000 ⁇ m thick, depending on size and intended application.
  • the invention is applicable to wafers exhibiting a thickness of 200-5000 ⁇ m, preferably 300-3000 ⁇ m, most preferably 400-1000 ⁇ m.
  • the first general step is the provision of a trench, i.e. a narrow recess encircling a portion of the wafer top surface.
  • the trench is made for example by etching or by laser based machining, or by EDM (electro-discharge machining).
  • Trench definition is achieved by providing a lithographic mask on the wafer.
  • trenches are made by any etching method yielding a high aspect ratio, e. g. DRIE (Dry Reactive Ion Etching), electrochemical HF etch.
  • DRIE Deposition Reactive Ion Etching
  • electrochemical HF etch electrochemical HF etch.
  • the trench should be less than 20 ⁇ m, preferably 4-15 ⁇ m, most suitably about 6-12 ⁇ m wide.
  • the layers of insulating material are 1-20 ⁇ m, typically 6-12 ⁇ m thick.
  • the insulating material should have certain electrical properties, such as a break down voltage of 1 kV or more; and a dielectric coefficient of 4-9.
  • the insulating material suitably extends over the substrate in a pattern adapted to a design of a selected electronic device.
  • the imaging device can be e.g. a photonic (X-ray, IR, visible etc) detection device, or a mirror array for light projection or a fingerprint detection device, and comprises a plurality of pixel elements 40 , only two of which are shown in FIG. 4 for clarity.
  • Each pixel 40 is provided with a solder bump SB and connected to a respective via 33 by routing structures 41 in the form of narrow metallizations.
  • the ASIC 31 comprises analogue and digital components provided in separated parts. These components are contacted with the vias 33 via solder bumps 34 .
  • barriers 38 provided extending through the wafer. In FIG. 4 these barriers are shown in “pairs”, i.e. two barriers 38 ′, 38 ′′ run in parallel. This design is made for the purpose of creating redundancy against short-circuiting, a phenomenon that will be discussed more in detail below.
  • the barriers 38 ′, 38 ′′ enclose a shielded area 39 used for digital ground and will effectively shield the analogue and digital areas from cross-talk between each other through the substrate.
  • an insulting layer 42 provided on the bottom surface of the interposer 30 , and thereon is a shield layer 43 of metal provided covering the ground area 39 .
  • a further insulating layer 44 is provided, covering the bottom surface of the interposer 30 .
  • wire bonding 45 For connection to external equipment there is provided wire bonding 45 . This is used for supplying power to both sides of the interposer.
  • the wire 45 is bonded to a pad and routed using metallization 35 to a via 33 .
  • a power supply PS that picks up power from the via and a solder bump SB.
  • a power supply PS in the ASIC 31 on the opposite side is connected via a solder bump 34 on the interposer, using the same routing 35 .
  • FIG. 5 there is shown a further application of the same principle as used in FIG. 4 .
  • the single mixed analogue/digital component is replaced by a plurality of separate analogue and digital components.
  • It illustrates an array of imaging devices, such as a full 35 mm camera sensor, wherein the sensor array has been split up e.g. into smaller and less expensive chips.
  • the chips are mounted on an interposer 50 similar to the one disclosed in FIGS. 3 and 4 .
  • the chips are connected to ASICs and/or other electronic components (#1, #2, #3 . . . ”N) on the opposite side of the interposer using vias, as discussed above in connection with FIGS. 3 and 4 .
  • imaging devices can be used for detection of X-rays, IR light, visible light etc. with low signal levels.
  • ASIC imaging chip with ASIC (and other components) are separated by barriers 54 similar to the ones disclosed in FIGS. 3 and 4 .
  • the imaging device is a micromirror array
  • normally hundreds of volts are applied.
  • the trench insulation should therefore withstand such high voltages, and a break-down voltage of at leas 1 kV is required.
  • the isolated island should protect from capacitive cross-talk.
  • a problem that can occur with very long trenches, such as those forming the barriers 38 in FIGS. 3 and 4 used for preventing cross-talk, as discussed above, is that in view of the trenches in a standard situation being about only 8 ⁇ m wide, it will suffice if one single particle with conductive properties gets “caught” in the trench and forms a bridge between the via and the surrounding wafer material in order that the area enclosed by the trench will be short-circuited. The probability of this happening becomes increasingly larger as the length of the trench increases, and will inevitably cause high rejection rates and thus low manufacturing yields.
  • two or more trenches 81 ′, 81 ′′, 81 ′′′ are made as concentric circles or squares or rectangles or any other geometric shape on a wafer 80 , enclosing an area 82 , and each circle is connected to the next by radially extending trenches 83 ′, 83 ′′ wherein three concentric trenches are connected by the radial trenches.
  • This principle can be used for the purpose of the present invention, namely to isolate parts on a substrate wafer from each other, so as to eliminate or reduce cross talk between components on the substrate.
  • FIG. 9 intends to show schematically a chip 90 on which there are provided both analogue A and digital D components, that would cause unwanted cross talk unless they are separated.
  • a trench structure 91 as described above. This will efficiently shield the wafer (substrate) portions from currents leaking between the dedicated analogue and digital portions, A and D, respectively respectively. To further improve redundancy and to lower the capacitance between Analogue and Digital areas, several parallel trench chains would suitably be provided.
  • FIG. 6 An example of such vias 62 is schematically shown in FIG. 6 as a top view of a portion of a wafer 60 having the novel trench structures provided therein (see also FIG. 9 ).
  • the filled trenches are designated 64 .
  • the idea is to let neighbouring vias share a common insulated trench as at 66 in FIG. 1 .
  • a typical centre-to-centre distance for these vias is about 50 ⁇ m, if trenches are 10-15 ⁇ m wide and the side dimension of vias is, typically 35-40 ⁇ m.
  • the “plugs” (vias) 92 between the trenches are made of wafer native material. In the case of silicon this entails high dielectric coefficient. By allowing a floating potential on these “plugs” 92 , the capacitance between A and D is considerably decreased compared with the case if only one single trench should be provided.
  • etch load compensation in accordance with an aspect of the invention there will always be made a redundant via 94 at each end of the trench structure built up from the array.
  • the corners are given a special geometry schematically shown in FIG. 7 , which corresponds to the encircled part shown at 68 in FIG. 6 .
  • the optimal shape can be determined based on etching parameters used for each specific case. Narrowing the trenches like this, as shown at 70 , will ideally result in trenches having essentially the same depth, or at least will the etch not be too deep in the corners of the trench structure.

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EP2106617A4 (fr) 2015-04-15
WO2008091221A3 (fr) 2008-09-18
US20120292736A1 (en) 2012-11-22
EP2121511B1 (fr) 2017-08-16
TW200848359A (en) 2008-12-16
WO2008091220A1 (fr) 2008-07-31
TWI461348B (zh) 2014-11-21
EP2106617A1 (fr) 2009-10-07
EP2106617B1 (fr) 2021-06-02
EP2121511A4 (fr) 2014-07-02
SE0700172L (sv) 2008-07-26
US8598676B2 (en) 2013-12-03
US20100053922A1 (en) 2010-03-04
WO2008091221A2 (fr) 2008-07-31
EP2121511A2 (fr) 2009-11-25
SE533579C2 (sv) 2010-10-26

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