US20080023699A1 - A test structure and method for detecting charge effects during semiconductor processing - Google Patents

A test structure and method for detecting charge effects during semiconductor processing Download PDF

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Publication number
US20080023699A1
US20080023699A1 US11/460,209 US46020906A US2008023699A1 US 20080023699 A1 US20080023699 A1 US 20080023699A1 US 46020906 A US46020906 A US 46020906A US 2008023699 A1 US2008023699 A1 US 2008023699A1
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test structure
gate electrode
diffusion region
charge
substrate
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US11/460,209
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English (en)
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Ming-Hsiu Lee
Chao-I Wu
Ming-Chang Kuo
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Macronix International Co Ltd
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Macronix International Co Ltd
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Priority to US11/460,209 priority Critical patent/US20080023699A1/en
Assigned to MACRONIX INTERNATIONAL CO., LTD. reassignment MACRONIX INTERNATIONAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, MING-HSIU, KUO, MING-CHANG, WU, CHAO-I
Priority to TW095132795A priority patent/TWI335657B/zh
Priority to CN200710136485.7A priority patent/CN101114634B/zh
Publication of US20080023699A1 publication Critical patent/US20080023699A1/en
Priority to US12/777,858 priority patent/US8241928B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • This invention relates generally to testing and diagnostics of line processes used for the manufacture of integrated circuit devices, and more particularly to the measurement and monitoring of the charging status in a gate dielectric layer or floating gate layer of a test structure during semiconductor processing steps.
  • the manufacture of large-scale integrated circuits involves hundreds of discrete processing steps. These steps are typically divided into two sub-processes.
  • the first of these sub-processes is often referred to as the front-end of line (FEOL) sub-process during which the semiconductor devices are formed within a silicon wafer.
  • the second of the sub-processes is often termed the back-end of line (BEOL) sub-process during which various metal interconnecting layers and contacts are formed on top of the semiconductor devices formed during the FEOL sub-process.
  • FEOL front-end of line
  • BEOL back-end of line
  • FEOL and BEOL sub-processes involve depositing layers of material, patterning the layers by photolithographic techniques, and then etching away unwanted portions of the deposited material.
  • the deposited materials primarily consist of insulators and metal alloys.
  • the pattern layer serves as temporary protective mass, while on others they are functional components of the integrated circuit chips being formed.
  • Radio frequency (RF) plasmas are often used in many of the processing steps, especially in the processing steps comprising the BEOL sub-process.
  • RF plasmas are used in Reactive Ion Etching (RIE), which is used to etch the layers of material as described above.
  • RIE Reactive Ion Etching
  • gaseous chemical etching is assisted by unidirectional ion bombardment provided by an RF plasma.
  • Photo-resist layers, used in the photolithographic patterning described above, are also frequently removed using plasma ashing.
  • the surfaces of the patterned semiconductor wafer present multiple areas of conductors and insulators to the RF plasmas.
  • the multiple areas of conductors and insulators produce local non-uniformities in the plasma currents, which can result in charge build up on the electrically floating conductor surfaces. This charge build up can produce the damaging current flows and can affect the threshold voltages for semiconductor structures formed on the silicon wafer.
  • the semiconductor devices often comprise some form of field effect transistor comprising a gate, drain, and source regions.
  • the gate often comprises a polysilicon electrode separated from the substrate by a gate dielectric. Charge can penetrated through the gate dielectric to the gate electrode.
  • the mechanism of current flow through the gate oxide is primarily the result of Fowler-Nordheim (FN) tunneling. FN tunneling occurs at fields in excess of 10 MV/cm. Charge build up on the gate electrode resulting in a gate electrode potential of only 10 volts is therefore sufficient to induce FN tunneling through an oxide layer of 100 A.
  • FN tunneling occurs at fields in excess of 10 MV/cm. Charge build up on the gate electrode resulting in a gate electrode potential of only 10 volts is therefore sufficient to induce FN tunneling through an oxide layer of 100 A.
  • Such potentials are easily achieved in conventional plasma reactors used to generate RF plasmas and semiconductor processing. Excessive FN tunneling currents eventually lead to positively charged interface traps in the oxide layer forming the gate,
  • test wafers or test chips comprising structures designed to measure, or allow measurement of, the damage produced by various processing steps.
  • Test structures are typically formed within a specifically designated test site on a semiconductor wafer being processed. Alternatively, entire wafers can be devoted to providing a plurality of test structures for process monitoring. Thus, the test structures are run through the process which results in charge build up that can be then measured.
  • a common method for measuring the charging status is to use Capacitance-Voltage (CV) techniques or floating gate testers. Such techniques, however, are often unsatisfactory for the semiconductor industry because of their low sensitivity, high test chip cost, or long delay time associated with the production of data related to the testing.
  • CV Capacitance-Voltage
  • the CV method can only be used for processes with uniform charging effect.
  • CV methods will suffer from insufficient capacitance change produced by the trapped charges.
  • the insufficient capacitance change will render conventional CV methods insufficient for monitoring the charging status.
  • a semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region.
  • the test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps.
  • Gate-Induced Drain Leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
  • charge-trapping layers comprising dielectrics with different charging states near the diffusion region will result in different GIDL currents.
  • the charge-trapping layer can be an oxide-nitrite-oxide or oxide-Si-oxide structure.
  • FIGS. 1A-1C are diagrams illustrating various views of a test structure configured in accordance with one embodiment
  • FIG. 2 is a diagram illustrating a metalized version of the test structure of FIG. 1 with test leads;
  • FIG. 3 is a diagram illustrating bias voltages that can be applied to the test structure of FIG. 1 in order to generate GIDL currents for measurement of charge status in accordance with one embodiment
  • FIG. 4 is a diagram illustrating current measurements obtained using the bias voltages of FIG. 3 before and after a process step being evaluated;
  • FIG. 5 is a diagram illustrating a plurality of different gate electrode shapes that can be used for the test structure of FIG. 1 ;
  • FIG. 6 is a diagram illustrating another example test structure in accordance with another embodiment
  • FIG. 7 is a diagram illustrating another example test structure in accordance with another embodiment
  • FIG. 8 is a diagram illustrating another example test structure comprising a plurality of diffusion areas in accordance with another embodiment
  • FIG. 9 is a diagram illustrating another example test structure comprising a plurality of diffusion areas in accordance with another embodiment
  • FIG. 10 is a diagram illustrating another example test structure comprising a plurality of diffusion areas in accordance with another embodiment
  • FIG. 11 is a diagram illustrating another example test structure comprising a plurality of diffusion areas in accordance with another embodiment
  • FIG. 12 is a diagram illustrating bias voltages that can be applied to the test structure of FIG. 11 in order to generate GIDL currents for measurement of charge status in accordance with one embodiment
  • FIG. 13 is a diagram illustrating a pattern comprising a plurality if the test structures of FIG. 11 ;
  • FIG. 14 is a diagram illustrating another example test structure comprising a plurality of diffusion areas in accordance with another embodiment.
  • FIG. 15 is a diagram illustrating another example test structure comprising a plurality of diffusion areas in accordance with another embodiment.
  • the systems and methods described herein are directed to simple capacitor-like test structures that can be used to reduce test wafer costs and shorten the delay time for producing test data that can be used to modify the semiconductor processes at issue in order to reduce damage resulting from charge accumulation during processing steps.
  • GIDL currents in the capacitor-like test structures are used to determine a charging status for the test structure.
  • the GIDL currents produced and the test structures described herein are sensitive to charges in the dielectric charge-trapping layers near a diffusion region. As a result, GIDL current measurement techniques are capable of producing useful test data for both uniform and edge-charging devices.
  • the charging effect will result in a wide initial threshold voltage distribution, which can impact the device's operation window.
  • the charging effect can result from various electric fields, plasmas, or radiation, such as UV light, to which a semiconductor wafer is exposed during semiconductor processing.
  • FIGS. 1A-1C are diagrams illustrating various views of an example semiconductor test structure 100 configured in accordance with one embodiment of the systems and methods described herein.
  • FIG. 1A is a diagram illustrating a top view of test structure 100 .
  • test structure 100 comprises a gate electrode 102 and a diffusion region 104 .
  • FIG. 1B is a perspective view of test structure 100 illustrating that diffusion region 104 sits atop a substrate 108 .
  • substrate 108 can be a bulk Si substrate.
  • FIG. 1C is a diagram illustrating a cross section of test structure 100 along line A-A′. In the cross-sectional view of FIG. 1C , charge-trapping layer 104 can be seen. Charge-trapping layer can reside under electrode 102 and over diffusion region 106 .
  • Charge-trapping layer 104 is a dielectric layer designed to trap charges within structure 100 .
  • charge-trapping layer 104 comprises an oxide-nitride-oxide structure.
  • charge-trapping layer 104 comprises an oxide-Si-oxide structure, such as a SiO2-Si—SiO2 structure.
  • charge-trapping layer 104 comprises a structure with high dielectric constant materials, such as nitride, aluminum oxide, or hafnium oxide. It will be apparent, however, that any dielectric layer or structure that can be used to trap charge in accordance with the systems and methods described below can be used for charge-trapping layer 104 .
  • Gate electrode 102 can comprise a polysilicon layer depending on the embodiment.
  • substrate 108 is a P-type substrate, while diffusion region 106 comprises an N-type region.
  • substrate 108 can be a N-type substrate, while diffusion region 106 is a P-type region.
  • diffusion region 106 and gate electrode 102 can be metallized with metal layers 202 and 204 respectively.
  • metal layers 202 and 204 can be metal silicide layers.
  • Metallizing diffusion region 106 and gate electrode 102 can reduce the resistance associated with diffusion region 106 and gate electrode 102 .
  • Testing of structure 100 can be accomplished by directly probing on diffusion region 106 and gate electrode 102 .
  • interconnection leads such as interconnection lead 206
  • metal layers 202 and/or 204 can then be probed in order test the charging status of structure 100 .
  • test structure 100 can be subjected to the process steps being monitored. This will result in charge being imparted to charge-trapping layer 104 during the various process steps.
  • the charge can be imparted, as explained above, by an electric field, plasma, charge particles, radiation (UV) or other sources.
  • the amount of charge or charge status in charge-trapping layer 104 can then be determined by probing gate electrode 102 and diffusion region 106 or interconnection leads attached thereto.
  • diffusion region 106 can be formed before or after the process steps being tested are performed depending on the embodiment.
  • FIG. 3 is a diagram illustrating example voltages that can be applied to structure 100 in order to produce and measure GIDL currents within structure 100 . It will be clear that the voltages applied are for a P-type substrate 108 and N-type diffusion region 106 . Thus, a negative bias voltage ( ⁇ Vg) 304 can be applied to gate electrode 102 , while a positive bias voltage (+Vd) 306 is applied to diffusion region 106 . Substrate 108 can then be grounded. For an N-type substrate 108 , the polarity of the bias voltages 304 and 306 should be reversed.
  • FIG. 4 is a diagram illustrating such a shift.
  • FIG. 4 illustrates the current measured for various gate bias voltages ( ⁇ Vg) 304 .
  • Curve 402 illustrates the current measured prior to test structure 100 undergoing a particular process step
  • curve 404 illustrates the current measured for test structure 100 after it has undergone the particular process step.
  • curve 404 has been shifted relative to curve 402 as a result of the charge imparted during the process step being tested. This information can then be used to modify the process and improve yields. As mentioned above, the test results can be achieved quickly and at little cost.
  • the GIDL currents can be measured for processes that result in uniform charging or processes that result in edge charging.
  • test structures comprising different test patterns can be designed for different process-monitoring purposes.
  • FIG. 5 illustrates several example shapes that can be used for gate electrode 102 depending on the embodiment.
  • test structure 100 can comprise a circular gate electrode 502 , a square gate electrode 504 , a star-shaped gate electrode 506 , etc.
  • a more complex shape can be used for gate electrode 102 depending on the process being monitored.
  • a gate electrode 508 with a plurality of fingers 508 a can be used in certain embodiments of test structure 100 .
  • Other embodiments of test structure 100 can use a gate electrode 512 that includes a plurality of long lines 512 a.
  • Gate electrodes can be configured with a different axis of orientation as well.
  • gate electrode 508 can be oriented along a horizontal axis of orientation or a vertical axis of orientation as illustrated in FIG. 5 .
  • gate electrode 512 can be oriented along a horizontal axis or a vertical axis as required by a specific embodiment.
  • the charging effect that occurs during the various processing steps is a result of various conductive layers and areas acting like an antenna that attract charge produced during the various processing steps.
  • Configuring gate electrodes with, e.g., long fingers 508 a or long lines 512 a can increase or decrease this antenna effect, which can be used to produce more relevant or accurate test data.
  • FIG. 6 is a diagram illustrating a gate electrode 508 and a gate electrode 512 combined with a partial oxide region 602 to form a test structure 600 .
  • Test structure 600 can, for example, be used to test for the antenna effect referred to above.
  • partial oxide region 602 can be combined with a gate electrode 508 alone or a gate electrode 512 alone.
  • other gate electrodes of various shapes and orientations can be combined with oxide region 602 .
  • FIG. 7 is a diagram illustrating a test structure 700 comprising a circular gate electrode 502 surrounded by an oxide region 702 .
  • Test structure 700 can be used to isolate a leakage path within test structure 700 .
  • other gate electrodes comprising other shapes and/or orientations can be combined with oxide region 702 depending on the embodiment.
  • the diffusion region can be separated into two or more regions, e.g., by the gate electrode structure.
  • the diffusion region can be separated into source and drain regions as would be found in a MOSFET structure.
  • FIG. 8 is a diagram illustrating an example test structure 800 comprising a gate electrode 802 separating a drain region 804 and source region 806 . Drain and source region can be formed in substrate 808 .
  • FIG. 9 is a diagram illustrating another test structure 900 comprising a drain region 904 and source region 906 separated by a gate electrode 902 .
  • FIG. 10 is a diagram illustrating a test structure 1000 comprising four diffusion regions, 1004 , 1006 , 1008 , and 1010 , separated by gate electrode 1002 .
  • any number of diffusion regions required to achieve the test data being sought can be included within the test structure configured in accordance with the systems and methods described herein.
  • the shape of the gate electrode can be varied as required to achieve the test data being sought and to separate the various diffusion regions.
  • FIG. 11 illustrates a test structure 1100 comprising a gate electrode 1102 separating a drain diffusion region 1106 and the source diffusion region 1110 formed on substrate 1108 .
  • the charge effect on drain 1106 can be determined by applying certain bias voltages to gate electrode 1102 , drain 1106 , and source 1110 and then measuring the resulting GIDL current.
  • the charge effect on source 1110 can be measured by applying certain bias voltages to gate electrode 1102 , drain 1106 , and source 1110 and then measuring the resulting GIDL current.
  • FIG. 12 is a diagram illustrating example bias voltages that can be applied to gate electrode 1102 , drain 1106 , and source 1110 in order to measure the charging effect for drain 1106 and for source 1110 .
  • substrate 1108 is a P-type substrate while drain and source regions 1106 and 1110 are N-type diffusion regions.
  • a negative gate bias voltage ( ⁇ Vg) 1116 can be applied to gate electrode 1102 and a positive bias voltage (+Vd) 1118 can be applied to drain diffusion region 1106 , while source diffusion region 1110 is allowed to float and substrate 1108 is tied to ground, in order to measure the GIDL current for drain region 1106 .
  • drain region 1106 can be allowed to float, while a positive bias voltage (+Vs) 1114 is applied to source diffusion region 1110 .
  • test structures can be laid out with different orientations, e.g., in order to provide information related to an isotropic charging effect.
  • a plurality of test structures 1100 are laid out in a pattern 1300 .
  • test structure 1100 and pattern 1300 can have vertical, horizontal, or diagonal orientations.
  • a pattern of test structures, such as pattern 1300 with varying orientations can be useful in providing an isotropic charging effect information.
  • other test structure patterns can comprise more or less test structures along with more or less orientations.
  • a test pattern can comprise test structures with different shapes and dimensions as well as different orientations.
  • FIGS. 14 and 15 illustrate two example embodiments of test structures 1400 and 1500 respectively that are slightly more complex than the previous structures illustrated above. It will be clear, however, that the embodiments described herein are by way of example only and that the particular test structures described should not be seen as limiting the systems and methods described herein to any particular test structures, shapes, orientations, or levels of complexity.
  • FIG. 15 is a diagram illustrating a test structure 1500 in accordance with one embodiment of the systems and methods described herein.
  • Test structure 15 comprises a gate electrode 1504 separating a plurality of diffusion regions 1506 - 1522 , formed on a substrate 1502 .
  • FIG. 14 is a diagram illustrating a test structure 1400 configured in accordance with another embodiment of the systems and methods described herein.
  • Test structure 14 comprises a circular gate electrode 1404 separating diffusion regions 1406 - 1420 formed on substrate 1402 .
  • test structures such as those described above, can be arranged on a single wafer, either in the scribe line or in the chip area, for process monitoring. As mentioned, multiple test structures can be arranged comprising different shapes and orientations. Further, one or more of the test structures can be packaged into a discreet device as a sensing element for plasma or radiation detecting.

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TW095132795A TWI335657B (en) 2006-07-26 2006-09-05 A test structure and method for detecting charge effects during semiconductor processing
CN200710136485.7A CN101114634B (zh) 2006-07-26 2007-07-13 用于在半导体工艺中检测电荷效应的测试结构与方法
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US9070652B2 (en) 2012-04-13 2015-06-30 United Microelectronics Corp. Test structure for semiconductor process and method for monitoring semiconductor process
US20190115217A1 (en) * 2016-07-04 2019-04-18 Mitsubishi Electric Corporation Manufacturing method for semiconductor device
CN114545180A (zh) * 2022-01-07 2022-05-27 西安电子科技大学 一种基于MOSFETs弱反型区噪声的栅氧化层陷阱表征方法

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US8450792B2 (en) * 2011-04-08 2013-05-28 International Business Machines Corporation Structure and fabrication method of tunnel field effect transistor with increased drive current and reduced gate induced drain leakage (GIDL)
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CN111856236B (zh) * 2020-07-28 2022-07-12 哈尔滨工业大学 提取电子器件氧化层中负电荷的方法

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CN101114634B (zh) 2012-07-04
US8241928B2 (en) 2012-08-14
TWI335657B (en) 2011-01-01
US20100221851A1 (en) 2010-09-02
CN101114634A (zh) 2008-01-30

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