200814278 九、發明說明： 【發明所屬之技術領域] 本發明-般係有關於用以 測試與檢測，並尤其有關於在 你$電路元件之製程的 控在一測試結構之閘極介帝 ¥體製程步驟中測量並監 '層或洋動開極中的充電狀態。 【先前技術】 大型積體電路的製造會牽淨 驟。這些步驟典型地分為二群百個分離的製程步 個係通常指稱為前段製程。這些子步驟的第一 晶圓中。第二個子步驟係通常 =，元件係形成於一石夕 金屬連接層以及接觸係形成於二段製程，其間各種 的半導體元件之上。 則又β程子步驟中所形成 前段和後段製程中包括有許多 制 材料的沈積、以微影蝕刻技術程步驟，會牽涉到 積材料中不需要的部分I虫刻。戶斤、$ 土α層、並接著將所沈 體以及金屬合金所構成。在某此=積的材料主要係由絕緣 暫時保護體，而在其他時候則二二丄此圖案層係做為 元件。 為所形成積體電路的功能 無線射頻（RF)電漿係通常用於夕制 在包括後段製程子步驟的製程步衣^^驟中，尤其是 係使用於反應性離子蝕刻（RIE τ牛例而言，RF電漿 上述各材料層。反應性離子蝕^徂程則係用以蝕刻 定義圖案時、以及精確控制尺^寸日了達成高精準度 刻。在RIE中，氣相化學蝕^ 1斤而要的非等向性蝕 向離子轟炸而達成。用於上^科、里二電漿所提供的單 阻層，亦通常利用電漿灰化而蝕刻圖案化步驟中的光 不幸地厂人恭露至灯電聚以及其他類型的離子射線 5 200814278 ί導致輻射傷害以及在外露導電元件中累積電荷，後 將以成知吾電流以及電荷被捕捉，進而影響半導體元件 =及if成的積體電路晶片。圖案化後的半導體晶圓表 多個導體與絕緣體部分受到RF電漿的照射。這 二ίΐ體部分在電漿電流中產生了局部不均勻，其 ^把=1包荷累積於電荷流動的導體表面。此電荷累積會 構流’並可能影響石夕晶圓上所形成之半導體結 括導、體元件通常包括某種形式的場效應電晶體’其包 托二二输f極、以及源極區域。電流流經氧化物生成之閘 对/^6 έ士制’係主要為富勒諾德漢(F〇lwer-N〇rdheim)穿隧 ;r'f二丨。FN穿隨效應係發生在大於1〇MV/cm的電場 足以’在二;的電壓，會使得僅要10伏特的閘極電壓就 電位在1〇()埃的氧化層中誘發FN穿隧效應。此 二rf電聚以及半導體製程的電讓反 的氧化層中形成^^的rf穿隨電流最終將在形成閘極 潰。甲办成电何介面捕捉層，其可進一步引起電性崩 傷暴露至連續的製程步驟後，傷害或潛在 程步驟中所形成的傷；多主於評估在各半導體製 程度的方法，係制1、1卜+舉例而§，一經常用以測試傷害 地設計而可量測C式晶圓或測試晶片’其中包括有特 害的結構。 '(或允許量測）由各製程步驟所造成之傷 測試Ί ^中則。fn形成於半導體晶片内一特別設計的 試結構，以龄护制如正片晶圓可被用來專門提供複數個測 而導致可胸㈣係㈣完整製程， 態之方法，係使用知。一種經常用以量測充電狀 竹便用-电各-電壓（cv)技術或浮動閘極測試。然 6 200814278 而此等習知技術通常在半導體業中無法獲得令人滿意的結 果，因為敏感度低、測試晶片成本高昂、或與測試相關之 資料產生時延遲時間長。 舉例而言，習知的cv方法僅可用在具有均勻充電效應 的製程。易言之，對於該些電荷會在閘極結構邊緣累積的 ^程，習知的CV方法將受到由被捕捉電荷所致的電容改 變不足所苦。此不足的電容改變將使習知CV方法不能用 以監控充電狀態。 【發明内容】 一種半導體製程測試結構，其包括一閘極、一電何裯從 I兮一擴散區域。此測試結構係為一類電容結構，其 1電荷捕捉層將在不同製程步驟中捕捉電荷。可接著j吏 (GIDL) 分之一面向中，電荷捕捉層係包括不同的介電質i 不同的閑不同的充電狀態’因此會造成 “目1結構與方法。本發明内容說明 所定義舉發明。本發明係由申請專利範圍 透過下列施例、特徵、目的及優點等將可 月申’專利乾圍及所附圖式獲得充分瞭解。 【實施方式】 可用本關於簡易類電容測試結構，其 的守間延遲，此職資料係用以修改該半導體製 7 200814278 以減少在製程步驟中之電荷累積所造成的損害。 +、在^類電容測試結構中的閘極誘發汲極漏電流係用以決 定j試結構之一充電狀態。本發明所述的此閘極誘發汲極 Ϊ電Ϊ以及測試結構，係對於為在靠近一擴散區域處之介 ，，荷捕捉層中的電荷非常敏感。因此，閘極誘發汲極漏 電流測量技術係可以對於均一以及邊緣電荷之元件，產生 有用的測試資料。 如上所述’有許多半導體製程步驟可以在一半導體結構 的2極介電層誘發一電荷效應，造成臨界電壓偏移及/或閘 • ^介電質的劣化。對於包括有浮動閘極元件之記憶元件如 電性可程式化可抹消唯讀記憶體(EEPROMS)與快閃元件、 以及士 SONOS元件等電荷捕捉元件而言，此充電效應會導 致一寬廣的初始臨界電壓分佈，其會衝擊此元件之操作區 ，。此充電效應的成因包括不同電場、電漿、或如紫外光 等射線’而使得半導體晶圓在半導體製程中受到這些射線 的照射。一、 第1A-1C圖係繪示一依據本發明系統與方法之一實施 例所組態之例示半導體測試結構1〇〇的各種視圖。第1Α 圖係繪示測試結構1〇〇之上視圖。如圖所示，測試結構1〇〇 _ 匕括閘極1 以及擴散區域1 〇6。第1Β圖係測試結構1 〇〇 之立體圖’其說明擴散區域位於一基板1〇8之上。舉 例而言，基板108可為一大片矽基板。第lc:圖係繪示測試 結構100沿著AA，線之剖面圖。在第1(：圖所示的剖面圖 中可以看到電荷捕捉層1〇4。電荷捕捉層可位於電極1〇2 之下、擴散區域106之上。 捕捉層104係一介電層其係設計以在結構1〇〇中捕 捉電荷。在一實施例中，電荷捕捉層1〇4包括一氧化物-氮 化物:氧化物結構。在另一實施態樣中，電荷捕捉層1〇4包 括一氧化物-矽-氧化物結構，例如二氧化;5夕_矽_二氧化矽結 200814278 構。在一實施例中， 數材料所構成的結構，何捕捉層104係包括一由高介電常 然而，顯而易見的是j例如氮化物、氧化鋁、或氧化铪。 法中之介電層或結構，任何可以用在下述本發明系統與方 閘極102可包括〜夕均曰可用做為電荷捕捉層1〇4。 例中，基板108係為^晶矽層，視實施例而定。在一實施 一 N型區域。在並他:P型基板，而擴散區域1〇6則包栝 板，而擴散區域/ι〇6 3ί態樣中，基板108可為一 N型基 如第2圖所示，擴化/型區域。 金屬層202與204進j 1(>6 以及閘極102可以分別以 中，i屬層‘與20了=:舉例而言，在-實施態檬 域106以及閘極1〇2 ^可為盃屬矽化物層。金屬化擴散暖 相關之電阻。 可以降低與擴散區域106與閘極102 之Γί行If而^Γ藉由直接於擴散區域106與閘極⑽ 探測，以測試結構1G()之充電\態。b内連接線可接著旅 二此’測試：構100可進入欲監控之製程步驟。此將造 何在不同衣程步驟時’被給予到電荷捕捉層刚中。 解釋’此電荷可被—電場、電漿、帶電粒子、射線 他來,所給予。接著則可藉由偵測閘極102 政區域106、或者連接此二者之内連接線，而監控 電荷捕捉層104中的電荷量或充電狀態。 工 j注意的是，擴散區域106可在所測試之製程步驟進 之W或之後形成，視不同實施例而定。 、，第3圖係繪示可以施加到結構1〇〇的例示電壓，以 亚測量在結構100之中的閘極誘發汲極漏電流。可以^ =是，電壓係施加到一 P型基板108以及N型擴散區域 1〇6。因此，一負偏壓（一Vg) 304可施加到閘極1〇2，而1 9 200814278 正偏壓（+Vd) 306則施加到擴散區 著接地。對於N型基板1G8 μ =二了接 應該逆轉。 偏堡綱與贏的極性 偏壓304,306的施加會使得一閘極誘 法 並流動於測試結構100之中，其可被測▲以決/定：：、則 製程中的充，效應所引起的臨界電壓偏移。第4圖二㈡ 此種偏移。第4圖繪不了不同閘極偏壓（_Vg) 3〇4之;200814278 IX. INSTRUCTIONS: [Technical field to which the invention pertains] The present invention generally relates to the use of a gate for testing and testing, and particularly for controlling the process of your circuit components in a test structure. During the process step, the state of charge in the 'layer or oceanic opening is measured and monitored. [Prior Art] The manufacture of large integrated circuits will lead to cleanliness. These steps are typically divided into two groups of hundreds of separate process steps. The system is often referred to as the front stage process. These substeps are in the first wafer. The second sub-step is usually =, the component is formed on a stone metal connection layer and the contact system is formed in a two-stage process with various semiconductor components in between. Then, the formation of the β-step sub-step includes the deposition of a plurality of materials in the process of the lithography process, and the lithography process step involves the unnecessary part I in the material. The jin, the earth alpha layer, and then the body and the metal alloy. In some cases, the material is mainly made of an insulating temporary protective body, and at other times, the pattern layer is used as a component. The function of the formed integrated circuit radio frequency (RF) plasma system is usually used in the process steps including the back-end process sub-steps, especially for reactive ion etching (RIE τ 牛例) In the RIE, the gas phase chemical etching ^ is used to etch the defined pattern and precisely control the ruler to achieve high precision. 1 jin of non-isotropic etching is achieved by ion bombardment. The single-resist layer provided by Shangke and Li 2 plasma is also usually etched by plasma ashing to unfortunately etch the light in the patterning step. The factory is obsessed with the lamp and other types of ionizing radiation. 200814278 ί causes radiation damage and accumulates electric charge in the exposed conductive elements, which will then capture the current and charge, which will affect the semiconductor components = and if Integral circuit wafer. The patterned semiconductor wafer shows that a plurality of conductors and insulator portions are irradiated by RF plasma. The two parts of the semiconductor body generate local unevenness in the plasma current, which accumulates 1 load. Charge flow Body surface. This charge buildup will flow' and may affect the semiconductor junction formed on the Shixi wafer. The body component usually includes some form of field effect transistor, which encloses the two poles, and the source. Polar region. Current flows through the oxide generating gate pair /^6 The gentleman's system is mainly for the F〇lwer-N〇rdheim tunneling; r'f 丨. FN wear-through effect system An electric field occurring at more than 1 〇 MV/cm is sufficient to 'at two's voltage, such that a gate voltage of only 10 volts induces a FN tunneling effect in an oxide layer of 1 Å () angstroms. The electricity of the poly-and semiconductor process allows the rf-following current in the opposite oxide layer to eventually form a gate-crush. A device can be electrically exposed to a continuous capture process, which can further cause electrical collapse to be exposed to a continuous process. After the step, the injury formed in the injury or potential step; more than the method of evaluating the degree of each semiconductor system, system 1, 1 Bu + example and §, one often used to test the damage design and can measure C Wafer or test wafer 'which includes a special structure. ' (or allow measurement) by each system The damage test caused by the step Ί ^ is. fn is formed in a specially designed test structure in the semiconductor wafer, and the age of the wafer, such as the positive wafer can be used to provide a plurality of measurements to lead to the chest (four) system (four) complete process The method of state is used. It is often used to measure the charge-like bamboo-electrical-voltage (cv) technology or floating gate test. However, these conventional technologies are usually not available in the semiconductor industry. Satisfactory results are obtained because of low sensitivity, high test wafer cost, or long delays in the production of test-related data. For example, the conventional cv method can only be used in processes with uniform charging effects. Thus, the conventional CV method will suffer from insufficient capacitance change due to trapped charges for the accumulation of these charges at the edge of the gate structure. This insufficient capacitance change will prevent the conventional CV method from being used to monitor the state of charge. SUMMARY OF THE INVENTION A semiconductor process test structure includes a gate and a drain region. This test structure is a type of capacitor structure whose charge trapping layer will capture charge in different process steps. It can be followed by a part of jGI (GIDL), and the charge trapping layer includes different dielectric states of different dielectric states. Therefore, the structure and method of the object can be caused. The present invention defines the invention. The invention is fully understood by the following examples, features, objects and advantages, etc. through the following examples, features, objects and advantages, etc. [Embodiment] The present invention relates to a simple capacitance test structure. The defensive delay, this job data is used to modify the semiconductor system 7 200814278 to reduce the damage caused by the charge accumulation in the process steps. +, the gate induced buckle leakage current in the ^ class capacitance test structure In order to determine the state of charge of one of the j-test structures, the gate-induced 汲-electrode and the test structure of the present invention are very sensitive to charge in the charge trapping layer for the interface near a diffusion region. Therefore, the gate-induced drain leakage current measurement technique can produce useful test data for uniform and edge-charged components. As mentioned above, there are many semiconductor manufacturing steps. A charge effect can be induced in a 2-pole dielectric layer of a semiconductor structure, causing a threshold voltage shift and/or a deterioration of the gate dielectric. For memory elements including floating gate elements, such as electrical stylization This charge effect can result in a broad initial threshold voltage distribution that can impact the operating region of the component, such as EEPROMs and flash components, as well as charge trapping components such as the SONOS component. The cause of the effect includes different electric fields, plasmas, or rays such as ultraviolet light, so that the semiconductor wafer is exposed to these rays in the semiconductor process. 1. The 1A-1C diagram shows a system and method according to the present invention. Various views of an exemplary semiconductor test structure configured in an embodiment. Figure 1 shows a top view of the test structure. As shown, the test structure 1 〇〇 闸 includes the gate 1 and Diffusion region 1 〇 6. The first diagram is a perspective view of the test structure 1 其 which indicates that the diffusion region is located above a substrate 1 。 8. For example, the substrate 108 can be a large 矽 substrate. A cross-sectional view of the test structure 100 along AA is shown. The charge trapping layer 1〇4 can be seen in the cross-sectional view shown in Fig. 1. The charge trapping layer can be located under the electrode 1〇2 and the diffusion region. Above the 106. The capture layer 104 is a dielectric layer designed to capture charge in the structure. In one embodiment, the charge trap layer 1〇4 includes an oxide-nitride: oxide structure. In another embodiment, the charge trapping layer 1 〇 4 comprises an oxide-germanium-oxide structure, such as a dioxide; 5 矽 矽 二 二 二 2008 2008 200814278 structure. In one embodiment, the number of materials constitutes The structure of the capture layer 104 includes a high dielectric constant. However, it is obvious that such as nitride, aluminum oxide, or hafnium oxide. The dielectric layer or structure in the process can be used in the system of the present invention described below. The square gate 102 can include a uniform current as the charge trapping layer 1〇4. In the example, the substrate 108 is a germanium layer, depending on the embodiment. In an implementation of an N-type area. In the case of the P-type substrate, the diffusion region 1〇6 is the cladding plate, and in the diffusion region/ι〇6 3ί state, the substrate 108 can be an N-type substrate as shown in FIG. 2, the expansion/type region. The metal layers 202 and 204 enter j 1 (> 6 and the gate 102 can be respectively in the middle, the i-type layer 'and 20 ==, for example, the --implemented state of the field 106 and the gate 1〇2 ^ can be The cup is a telluride layer. The metallization diffuses the heat-related resistance. It can be lowered and the diffusion region 106 and the gate 102 can be detected by directly detecting the structure 1G() by directly detecting the diffusion region 106 and the gate (10). The charging state of the b. The inner cable of the b can be followed by the second test of the test: the structure 100 can enter the process step to be monitored. This will be applied to the charge trapping layer just in the different process steps. Explain 'this charge It can be given by an electric field, a plasma, a charged particle, or a ray, and then the charge trapping layer 104 can be monitored by detecting the gate 102 political region 106, or connecting the inner connecting lines. The amount of charge or state of charge. Note that the diffusion region 106 can be formed during or after the process steps being tested, depending on the embodiment. Figure 3 illustrates the application to the structure. An exemplary voltage of 〇, which is sub-measured in the gate of the structure 100 to induce a drain leakage The voltage can be applied to a P-type substrate 108 and the N-type diffusion region 1〇6. Therefore, a negative bias (a Vg) 304 can be applied to the gate 1〇2, and 1 9 200814278 is The bias voltage (+Vd) 306 is applied to the diffusion region to ground. For the N-type substrate 1G8 μ = the second connection should be reversed. The application of the bias and the bias polarity bias 304, 306 will cause a gate to induce and flow. In the test structure 100, it can be measured ▲ to determine /::, the process is charged, the threshold voltage shift caused by the effect. Figure 4 (2) This offset. Figure 4 can not draw different gates Extreme bias (_Vg) 3〇4;
測，電流。曲線402係繪示了測試結構1〇〇進入特定製程 之前所測量的電流，而曲線404則繪示了測試結構1〇(^經 歷了特疋製程之後所測量的電流。如圖所示，曲線4〇4 應到曲線402係已發生偏移，原因即為在待測製程步驟中 所產生的電荷。此等資料可接著被用以修改製程並增加產 率。如上所述，此測试結果可以快速獲得並且成本很低。 此外’閘極誘發没極漏電流可以被用以測量該些產生均 一充電效應或產生邊緣充電敢應的製程。 如第5-1〇圖所示，可以設計包括有不同測試圖案的測試 結構’以用在不同的製程監控目的之中。舉例而言，第5 圖繪示了數個可以被用於閘極102的例示形狀，隨著實施 例而定。因此，隨著實施例的不同，測試結構1〇〇可以包 括一環形閘極502、一方形閘極504、一星形閘極506等。 隨著所監控製程的不同，可使用一更複雜的結構於閘極1〇2 中。舉例而言，一具有多個指狀結構508a之閘極508可被 使用於測試結構100的特定實施態樣中。測試結構1〇〇的 其他實施態樣，可使用一包括有複數個長條線512a之閘極 512。 閘極可組態為具有不同方向的轴。舉例而言，如第5圖 所示，閘極508可朝向一水平軸或朝向一垂直軸。相同地， 隨著特定實施態樣的不同，閘極512可朝向一水平軸或一 垂直軸。 10 200814278 禕疋’在不同製程步驟中所發生的充電效應， tu:同製程步驟中各導電層以及做為天線般吸引電荷 真Li :形成的結果。•閘極的組態設定為長錄5〇8a或 可以增加或減少此天線效應，進而產生更相 關或更準確的測試數據。 又祁 他實施例中，各種不同形狀的閘極組態，可盥 合，結合後的組態可達成不同製程以及監;空目的 結果。舉例而言，“圖係繪示-閘極508 乂及閘極512與一部分氧化物區域6〇2結合， =r;r:言，測試結構600可用以測== 實施财，科氧化物區域⑼2可與僅與 每或僅與一閉極512結合。甚者，在其他 =結ί他不同形狀以及不同方向之問極可與氧化物 诚示—測試結構700，其包括一被一氧化物區 上=所裱繞之環狀閘極5〇2。測試結構70 結構700内部之一漏電流路徑。相同地，顯： 易見的疋其他不同形狀及/或不同方向的閘極，亦可隨著實 施例的不同而與氧化物區域702結合。 、 在，他實施例中，此擴散區域可被閘極結構分為二個以 ^的區域。舉，而言，此擴散區域可被分為源極與汲極區 域’如同一金氧半場效應電晶體(MOSFET)結構中可見。第 8圖係繪示一例示測試結構8〇〇，其包括一用以分隔開一汲 極區域804與一源極區域806的閘極8〇2。汲極與源極區 域可形成於基板808之中。第9圖係繪示另一測試結構9〇〇 其包括被一閘極902所分隔之一汲極區域904以及源極區 域 906。 顯而易見的是，複數個擴散區域亦可被包括於一如本發 明所述之測試結構組態中。舉例而言，第1〇圖係繪示一測 11 200814278 π 试結構1000，其包括被閘極l〇〇2所分隔的四個擴散區域 1004，1006，1008，1010。一般而言，用以獲得此測試數據所 需要的擴散區域數目，應被包括於根據本發明系統與方法 所組態之測試結構中。此外，為了獲得測試數據並用以分 隔不同的擴散區域’閘極的形狀可視需求而改變。 當擴散區域係被分隔為兩個以上的區域時，例如第8_1〇 圖中所示，母一擴散區域之充電效應的量測則可各自獨立 進行。請參照第11圖所示的測試結構。第u圖係繪示一 測試結構1100,其包括一閘極1102,其係分隔形成於基板 _ I108上之一〉及極擴散區域以及源極擴散區域111()。 藉由施加特定偏壓至閘極1102、汲極11〇6、與源極111〇 並測量所生成的閘極誘發汲極漏電流，而可決定在汲極 1106上的充電效應。相似的，藉由施加特定偏壓至閘極 1102、汲極1106、與源極1110並測量所生成的閘極誘發汲 極漏電流’而可決定在源極111 〇上的充電效應。 第12圖係繪示可以施加至閘極1102、汲極1106與源極 1110的例示偏壓以測量在汲極1106與源極11丨〇上的充電 效應。在此實施中，基板1108係為一 P型基板，而汲極與 源極區域1106,1110係為N型擴散區域。因此，可施加二 響 負閘極偏壓（-Vg ) 1116至閘極11 〇2 ’並施加一正偏壓（+ vd ) 1118至汲極擴散區域1106，同時將源極擴散區域ul〇浮 接並將基板1108接地，以測I〉及極區域1106的閘極誘發 >及極漏電流。為了測量源極區域111 〇的間極誘發沒極漏電 流，係將汲極區域1106浮接，同時施加一正偏壓（+Vs) 1114到源極擴散區域1110。 多個测試結構可排列於不同的方向，例如用以提供關於 一等向性充電效應之資訊時。舉例而言，在第13圖中，複 數個測試結構1100係設ί於一圖案13〇〇中。如圖所示， 測試結構1100以及圖案13〇〇可為垂直、水平、或對角之 12 200814278 方向。一個如具有各種方向性的圖案1300之測試結構圖 案’在提供一非等向性充電效應資訊時相當有用。顯而易 見的是’其他圖案之測試結構可包括更多或更少的測試結 構，以及更多或更少的方向性。此外，一測試圖案可以包 括不同形狀、不同尺寸、以及不同方向的測試結構。 如上所述，一測试結構'閘極、及/或擴散區域的尺寸、 形狀、與方向性，可為了獲得理想的測試數據而做變更。 第14與15圖係繪示了二個測試結構ι4〇〇，15〇〇之例示實 施例，其係比先前所述之結構稍微複雜。然而可以清楚理 φ 解的是，本發明所述之實施例係僅為舉例之用，因此特定 之測试結構不應被視為將本發明之系統與方法限制於任何 特定的結構、形狀、方向性、或者複雜度。 第15圖係根據本發明系統與方法之一實施例，而繪示 一測試結構1500。測試結構15〇〇係包括一閘極1504，其 分隔了複數個形成於基板15〇2之上的擴散區域 1506-1522。第14圖係根據本發明系統與方法之另一實施 例，而繪示一測試結構1400。測試結構14〇〇係包括一環 狀閘極1404，其分隔了複數個形成於基板1402上之擴散 區域 1406-1420。 ⑩ 複數個如上所述之測試結構可安排於單一晶圓上的切 割道内或晶片區域内’以監控製程。如前戶斤述，複數個測 試結構可以包括不同的形狀與方向性。此外，一個以上的 測試結構可以被封裝入一分離式元件中，做為一用以偵測 電漿或射線之感測元件。 雖然本發明係已參照較佳實施例來加以描述，將為吾人 所瞭解的是，本發明創作並未受限於其詳細描述内容。替 換方式及修改樣式係已於先前描述中所建議，並且其他替 換方式及修改樣式將為熟習此項技藝之人士所思及。特別 是，根據本發明之結構與方法，所有具有實質上相同於本 13 200814278 發明之構件結合而達成與本發明實質上相同結果者皆不脫 離本發明之精神範疇。因此，所有此等替換方式及修改樣 式係意欲落在本發明於隨附申請專利範圍及其均等物所界 定的範疇之中。任何在前文中提及之專利申請案以及印刷 文本，均係列為本案之參考。 【圖式簡單說明】 第1A-1C圖係繪示根據本發明一實施例所組態之一測 試結構的各視圖。 第2圖係繪示第1圖之測試結構的金屬化後之結果，因 此具有測試導線。 第3圖係根據本發明一實施例，繪示可以施加至第1圖 之測試結構的偏壓，以產生閘極誘發汲極漏電流，進而測 量充電狀態。 .第4圖係繪示利用第3圖冬偏壓而在一製程步驟的前後 所測量得到的電流值。 第5圖係繪示複數個可用於第1圖之測試結構中的不同 閘極形狀。 第6圖係繪示本發明另一實施例之另一例示測試結構。 第7圖係繪示本發明另一實施例之另一例示測試結構。 第8圖係繪示本發明另一實施例之另一例示測試結 構，其包括有複數個擴散區域。 第9圖係繪示本發明另一實施例之另一例示測試結 構，其包括有複數個擴散區域。 第10圖係繪示本發明另一實施例之另一例示測試結 構，其包括有複數個擴散區域。 第11圖係繪示本發明另一實施例之另一例示測試結 構，其包括有複數個擴散區域。 第12圖係根據本發明一實施例，繪示可以施加至第11 14 200814278 圖之測試結構的偏壓，以產生閘極誘發汲極漏電流，進而 測量充電狀態。 第13圖係繪示一圖案其包括有複數個第11圖之測試結 構。 第14圖係繪示本發明另一實施例之另一例示測試結 構，其包括有複數個擴散區域。 第15圖係繪示本發明另一實施例之另一例示測試結 構，其包括有複數個擴散區域。Measure, current. Curve 402 shows the current measured before the test structure 1 〇〇 enters a specific process, and curve 404 shows the current measured after the test structure 1 〇 (^ has undergone the special process. As shown, the curve 4〇4 The offset to the curve 402 has occurred, which is the charge generated in the process step to be tested. This data can then be used to modify the process and increase the yield. As mentioned above, this test result It can be obtained quickly and at a very low cost. In addition, the gate-induced immersed leakage current can be used to measure the processes that produce uniform charging effects or generate edge charging. As shown in Figure 5-1, it can be designed to include Test structures having different test patterns are used for different process monitoring purposes. For example, Figure 5 illustrates several exemplary shapes that can be used for gate 102, as an example. Depending on the embodiment, the test structure 1A may include a ring gate 502, a square gate 504, a star gate 506, etc. A more complicated structure may be used depending on the process being monitored. At the gate 1〇 For example, a gate 508 having a plurality of finger structures 508a can be used in a particular embodiment of the test structure 100. Other embodiments of the test structure 1 can use a complex number The gate 512a has a gate 512. The gate can be configured as an axis having different directions. For example, as shown in Fig. 5, the gate 508 can face a horizontal axis or face a vertical axis. Depending on the particular implementation, the gate 512 can be oriented toward a horizontal axis or a vertical axis. 10 200814278 充电 'Charging effects occurring in different process steps, tu: the same conductive layer in the process step and as The antenna attracts the charge true Li: the result of the formation. • The configuration of the gate is set to long record 5〇8a or this antenna effect can be increased or decreased to produce more relevant or accurate test data. Different kinds of gate configurations can be combined, and the combined configuration can achieve different process and monitoring results. For example, "the diagram shows - gate 508 乂 and gate 512 and part Oxide region 6〇2 combination =r;r: In other words, the test structure 600 can be used to measure == implementation, the oxide region (9) 2 can be combined with only one or only one closed pole 512. Moreover, in other = different shapes and different The direction of polarity can be determined with the oxide-test structure 700, which includes a ring-shaped gate 5〇2 that is surrounded by an oxide region. Test structure 70 One of the leakage current paths inside the structure 700. The same Ground, visible: other different shapes and / or different directions of the gate, may also be combined with the oxide region 702 according to the embodiment. In his embodiment, the diffusion region can be braked The pole structure is divided into two regions of ^. For example, the diffusion region can be divided into source and drain regions as seen in the same metal oxide half field effect transistor (MOSFET) structure. Figure 8 is a diagram showing an exemplary test structure 8A including a gate 8〇2 for separating a drain region 804 and a source region 806. The drain and source regions may be formed in the substrate 808. Figure 9 illustrates another test structure 9A including a drain region 904 and a source region 906 separated by a gate 902. It will be apparent that a plurality of diffusion regions can also be included in a test structure configuration as described herein. For example, the first diagram shows a test 11 200814278 π test structure 1000, which includes four diffusion regions 1004, 1006, 1008, 1010 separated by a gate l〇〇2. In general, the number of diffusion regions required to obtain this test data should be included in the test structure configured in accordance with the systems and methods of the present invention. In addition, in order to obtain test data and to separate the different diffusion regions, the shape of the gate can be changed as needed. When the diffusion region is divided into two or more regions, for example, as shown in Fig. 8_1, the measurement of the charging effect of the mother-diffusion region can be performed independently. Please refer to the test structure shown in Figure 11. Fig. u shows a test structure 1100 comprising a gate 1102 which is formed on one of the substrate _I108 and the polar diffusion region and the source diffusion region 111 (). The charging effect on the drain 1106 can be determined by applying a specific bias voltage to the gate 1102, the drain 11〇6, and the source 111〇 and measuring the generated gate induced drain leakage current. Similarly, the charging effect on the source 111 可 can be determined by applying a specific bias voltage to the gate 1102, the drain 1106, and the source 1110 and measuring the generated gate induced drain leakage current'. Figure 12 illustrates an exemplary bias voltage that can be applied to gate 1102, drain 1106, and source 1110 to measure the charging effect on drain 1106 and source 11 。. In this implementation, the substrate 1108 is a P-type substrate, and the drain and source regions 1106, 1110 are N-type diffusion regions. Therefore, a negative negative gate bias (-Vg) 1116 can be applied to the gate 11 〇 2 ' and a positive bias (+ vd ) 1118 can be applied to the drain diffusion region 1106 while the source diffusion region ul is floated. The substrate 1108 is grounded to measure the gate induced > and the extreme leakage current of I> and the pole region 1106. In order to measure the interpole induced immersion current of the source region 111 ,, the drain region 1106 is floated while a positive bias (+Vs) 1114 is applied to the source diffusion region 1110. Multiple test structures can be arranged in different directions, for example to provide information about an isotropic charging effect. For example, in Fig. 13, a plurality of test structures 1100 are provided in a pattern 13A. As shown, test structure 1100 and pattern 13A can be vertical, horizontal, or diagonal 12 200814278 directions. A test structure pattern such as pattern 1300 having various directionalities is quite useful in providing an information on anisotropic charging effect. It is obvious that the test structure of other patterns may include more or less test structures, and more or less directionality. In addition, a test pattern can include test structures of different shapes, different sizes, and different orientations. As noted above, the size, shape, and directionality of a test structure 'gate, and/or diffusion region can be varied to achieve the desired test data. Figures 14 and 15 illustrate two exemplary embodiments of test structures ι4 〇〇, 15 , which are somewhat more complicated than previously described. However, it can be clearly understood that the embodiments of the present invention are for illustrative purposes only, and thus the particular test structure should not be construed as limiting the system and method of the present invention to any particular structure or shape. Directionality, or complexity. Figure 15 illustrates a test structure 1500 in accordance with one embodiment of the system and method of the present invention. The test structure 15 includes a gate 1504 that separates a plurality of diffusion regions 1506-1522 formed over the substrate 15A2. Figure 14 is a diagram showing a test structure 1400 in accordance with another embodiment of the system and method of the present invention. The test structure 14 includes a ring gate 1404 that separates a plurality of diffusion regions 1406-1420 formed on the substrate 1402. 10 A plurality of test structures as described above may be arranged in or within the dicing streets on a single wafer to monitor the process. As mentioned in the previous section, a plurality of test structures may include different shapes and directionalities. In addition, more than one test structure can be packaged into a separate component as a sensing component for detecting plasma or radiation. Although the present invention has been described with reference to the preferred embodiments, it is understood that the invention is not limited by the detailed description. Alternatives and modifications are suggested in the previous description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, the structures and methods of the present invention, all of which are substantially identical to the components of the present invention, are substantially the same as those of the present invention, without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents. Any patent application and printed text mentioned in the foregoing are a series of references for this case. BRIEF DESCRIPTION OF THE DRAWINGS The 1A-1C drawings illustrate various views of a test structure configured in accordance with an embodiment of the present invention. Figure 2 is a graph showing the results of the metallization of the test structure of Figure 1, and thus has test leads. Figure 3 is a diagram showing the bias voltage that can be applied to the test structure of Figure 1 to generate a gate induced drain leakage current, thereby measuring the state of charge, in accordance with an embodiment of the present invention. Figure 4 is a graph showing the current values measured before and after a process step using the winter bias of Figure 3. Figure 5 is a diagram showing the different gate shapes that can be used in the test structure of Figure 1. Figure 6 is a diagram showing another exemplary test structure of another embodiment of the present invention. Figure 7 is a diagram showing another exemplary test structure of another embodiment of the present invention. Figure 8 is a diagram showing another exemplary test structure of another embodiment of the present invention including a plurality of diffusion regions. Figure 9 is a diagram showing another exemplary test structure of another embodiment of the present invention including a plurality of diffusion regions. Figure 10 is a diagram showing another exemplary test structure of another embodiment of the present invention including a plurality of diffusion regions. Figure 11 is a diagram showing another exemplary test structure of another embodiment of the present invention including a plurality of diffusion regions. Figure 12 is a diagram showing the bias voltage that can be applied to the test structure of Figure 11 14 200814278 to generate a gate induced drain leakage current, thereby measuring the state of charge, in accordance with an embodiment of the present invention. Figure 13 is a diagram showing a pattern including a plurality of test structures of Figure 11. Figure 14 is a diagram showing another exemplary test structure of another embodiment of the present invention including a plurality of diffusion regions. Figure 15 is a diagram showing another exemplary test structure of another embodiment of the present invention including a plurality of diffusion regions.
【主要元件符號說明】 100 半導體測試結構 102 閘極 104 電荷捕捉層 106 擴散區域 108 基板 202,204 金屬層 304,306 偏壓 502 環形閘極 504 方形閘極 506 星形閘極 508 閘極 508a 指狀結構 512 閘極 512a 長條線 600 測試結構 602 氧化物區域 700 測試結構 702 氧化物區域 800 测試結構 15 200814278 802 804 806 900 902 904 906 1000 1002 閘極 没極 源極 測試結構 閘極 汲極 源極 測試結構 閘極 1004,1006,1008,1010 擴散區域 1100 測試結構 1102 1106 1108 1110 1114 1116 1118 1300 1400,1500 1402,1502 1404,1504 閘極 汲極擴散區域 基板 源極擴散區域. 正偏壓 負閘極偏壓 正偏壓 圖案 測試結構 基板 閘極 1406-1420,1506-1522 擴散區域 16[Main component symbol description] 100 semiconductor test structure 102 gate 104 charge trapping layer 106 diffusion region 108 substrate 202, 204 metal layer 304, 306 bias 502 ring gate 504 square gate 506 star gate 508 gate 508a finger structure 512 gate Pole 512a long line 600 test structure 602 oxide region 700 test structure 702 oxide region 800 test structure 15 200814278 802 804 806 900 902 904 906 1000 1002 gate electrodeless source test structure gate drain source test structure Gate 1004, 1006, 1008, 1010 Diffusion region 1100 Test structure 1102 1106 1108 1110 1114 1116 1118 1300 1400, 1500 1402, 1502 1404, 1504 Gate drain diffusion region substrate source diffusion region. Positive bias negative gate bias Positive bias pattern test structure substrate gate 1406-1420, 1506-1522 diffusion region 16