US20080003744A1 - Method of manufacturing nand flash memory device - Google Patents

Method of manufacturing nand flash memory device Download PDF

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Publication number
US20080003744A1
US20080003744A1 US11/618,714 US61871406A US2008003744A1 US 20080003744 A1 US20080003744 A1 US 20080003744A1 US 61871406 A US61871406 A US 61871406A US 2008003744 A1 US2008003744 A1 US 2008003744A1
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United States
Prior art keywords
layer
isolation structures
isolation
conductive layer
polysilicon
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Abandoned
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US11/618,714
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English (en)
Inventor
Byoung ki Lee
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, BYOUNG KI
Publication of US20080003744A1 publication Critical patent/US20080003744A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a NAND flash memory device and, more particularly, to a method of manufacturing a NAND flash memory device, in which the threshold voltage (Vt) shift due to cell interference can be reduced and the programmed threshold voltage Vt can be increased.
  • Vt threshold voltage
  • FIG. 1 is a perspective view illustrating a general method of manufacturing a NAND flash memory device by employing a Self-Aligned Shallow Trench Isolation (SASTI).
  • SASTI Self-Aligned Shallow Trench Isolation
  • a tunnel oxide layer 11 and a first polysilicon layer 12 are formed over a semiconductor substrate 10 .
  • the first polysilicon layer 12 and the tunnel oxide layer 11 are selectively etched by an etch process employing an isolation mask.
  • the semiconductor substrate 10 is etched by using the selectively etched first polysilicon layer 12 as a mask, forming trenches.
  • An insulating layer such as a High Density Plasma (HDP) oxide layer, is formed on the resulting structure so that the trenches are gap-filled.
  • the insulating layer is polished by means of a Chemical Mechanical Polishing (CMP) so that the top surface of the first polysilicon layer 12 is exposed, thus forming an isolation layer 13 in each of the trenches.
  • CMP Chemical Mechanical Polishing
  • a second polysilicon layer 14 is formed on the resulting structure.
  • the second polysilicon layer 14 is etched by using a mask, thus forming a floating gate including the first polysilicon layer 12 and the second polysilicon layer 14 .
  • a dielectric layer 15 and a conductive layer 16 for a control gate are formed on the resulting structure.
  • the width of the isolation trench decreases as the level of integration increases, and therefore the distance between neighboring floating gates also decreases. This leads to the occurrence of an interference phenomenon due to neighboring cells.
  • the interference phenomenon can occur between cells in a word line direction and a string cell direction.
  • the interference phenomenon occurring between cells in the string cell direction is generated since the HDP oxide layer existing between the first polysilicon layers serves as a dielectric material.
  • the interference phenomenon occurring between the cells in the word line direction is generated since the HDP oxide layer existing between the gates serves as a dielectric material.
  • FIG. 2 is a graph illustrating the relationship between the programmed threshold voltage Vt and the threshold voltage (Vt) shift due to interference as the size of a device is decreased.
  • curve “a” is a plot indicating the threshold voltage (Vt) shift due to interference of a cell verses device size
  • curve “b” is a plot indicating the programmed threshold voltage (Vt) verses device size.
  • the present invention is directed towards a method of manufacturing a NAND flash memory device, which can decrease the threshold voltage (Vt) shift due to interference of a cell by decreasing the footprint of the floating gate, and can increase the program threshold voltage Vt by increasing the contact area between the floating gate and the control gate.
  • Vt threshold voltage
  • a method of manufacturing a NAND flash memory device includes the steps of; etching a tunnel oxide layer, a first polysilicon layer, a buffer oxide layer, a nitride layer and a portion of a semiconductor substrate, all of which are laminated over a semiconductor substrate, thus forming trenches; forming an insulating layer within each of the trenches to form an isolation layer; sequentially removing the exposed nitride layer and the exposed buffer oxide layer; forming spacers on sidewalls of the isolation layer and partially removing a top surface of the isolation layer to control an EFH of the isolation layer; and forming a dielectric layer, a second polysilicon layer and a conductive layer on the entire surface of the resulting structure.
  • a method of manufacturing a flash memory device includes etching a tunnel dielectric layer, a first polysilicon layer, a buffer oxide layer, a nitride layer and a portion of a semiconductor substrate to form first and second isolation trenches.
  • An insulating layer is formed within the first and second isolation trenches to form first and second isolation structures, respectively, wherein the nitride layer, buffer oxide layer, the first polysilicon layer, and the tunnel dielectric layer being defined between the first and second isolation structures.
  • the nitride layer and the buffer oxide layer defined between the first and second isolation structures are removed to define a first gate trench.
  • First and second vertical extensions are formed within the first gate trench, the first vertical extension provided proximate to a sidewall of the first isolation structure, the second vertical extension provided proximate to a sidewall of the second isolation structure, the first and second vertical extensions contacting the first polysilicon layer. Upper portions of the first and second isolation structures are removed to define second gate trenches, so that each vertical extension has first and second sides exposed. A dielectric layer and a second polysilicon layer are formed within the first gate trench and the second gate trenches.
  • a method of manufacturing a non-volatile memory device includes forming first and second isolation structures in a substrate.
  • a tunnel dielectric layer, a first conductive layer, a first insulating layer, and a second insulating layer are provided between the first and second isolation structures.
  • the first and second insulating layers are removed to expose the first conductive layer.
  • First and second vertical extensions are formed on the first conductive layer to form a U-shape structure. Upper portions of the first and second isolation structures are removed to define second gate trenches, so that each vertical extension has first and second sides exposed.
  • a dielectric layer and a second conductive layer are formed to form a gate structure comprising the first conductive layer, the dielectric layer, and the second conductive layer.
  • the first and second isolation structures are formed after the tunnel dielectric layer and the first conductive layer.
  • the first conductive layer includes polysilicon.
  • the first insulating layer is provided as an etch stop layer, so that the second insulating layer can be removed without damaging the first conductive layer.
  • the first insulating layer is oxide-based, and the second insulating layer is nitride-based.
  • FIG. 1 is a perspective view illustrating a method of manufacturing a conventional NAND flash memory device.
  • FIG. 2 is a graph illustrating the relationship between the programmed threshold voltage Vt and the threshold voltage (Vt) shift due to interference as the size of the device is decreased.
  • FIGS. 3A to 3F are cross-sectional views illustrating a method of manufacturing a NAND flash memory device by employing a STI according to an embodiment of the present invention.
  • a tunnel oxide layer (or tunnel dielectric layer) 102 , a first polysilicon layer 104 for a floating gate, a buffer oxide layer 106 and a nitride layer 108 are formed over a semiconductor substrate 100 .
  • the layers 102 , 104 , and 106 are formed sequentially in the present implementation.
  • the nitride layer 108 , the buffer oxide layer 106 , the first polysilicon layer 104 , the tunnel oxide layer 102 and a portion of the semiconductor substrate 100 are etched to form trenches.
  • the nitride layer 108 is formed to a thickness of 500 to 900 angstroms.
  • a sidewall oxide layer is formed within each of the trenches (not shown).
  • An insulating layer is formed on the resulting structure so that the trenches are gap-filled.
  • the insulating layer can be formed from a HDP oxide layer.
  • the insulating layer is polished so that a top surface of the nitride layer 108 is exposed, thus forming an isolation structure 110 within each trench.
  • the nitride layer 108 is removed to expose the buffer oxide layer 106 .
  • a wet etch process is performed to remove the nitride layer 108 in the present implementation.
  • a trench 109 is defined between two adjacent isolation structures.
  • an etch target depth can be set to 150 to 170% of a total deposition thickness to ensure that the nitride layer is substantially removed from the buffer oxide layer.
  • the nitride etch step performed is provided with high selectivity to the oxide, so that only the buffer oxide layer 106 is only partially removed at the top.
  • the buffer oxide layer 106 remains to a thickness of 20 to 40 angstroms.
  • the buffer oxide layer 106 protects the first polysilicon layer 104 from the nitride etch process.
  • the remaining buffer oxide layer 106 is removed, e.g., by a wet etch process employing BOE or HF. At this time, the buffer oxide layer 106 is over-etched to a thickness of 40 to 80 angstroms. Due to the etch selectivity of the buffer oxide layer 106 and the first polysilicon layer 104 , only a small amount of the polysilicon layer 104 is removed. A significant amount of the sidewalls of the isolation layer 110 is etched away.
  • a silicon layer is formed on the resulting structure.
  • the silicon layer can be formed to a thickness of 100 to 300 angstroms.
  • the silicon layer is doped amorphous silicon.
  • the silicon layer is blanket etched to form vertical extensions (or spacers) 112 on the sidewalls of the isolation layer 110 .
  • the vertical extensions 112 and the first polysilicon layer 104 together resemble a U-shape structure.
  • the silicon layer is over-etched to a thickness of 200 to 450 angstroms, so that the top portion of the top first polysilicon layer 104 is also etched.
  • the top surface of the isolation layer 110 is partially etched by a wet etch process using BOE or HF in order to control the EFH of the isolation layer 110 .
  • a trench 119 is from above each isolation structure 110 . This increases the exposed surfaces of the vertical extensions 112 .
  • Each vertical extension 112 has a first side 120 that is facing the trench 109 and a second side 122 on the opposing side of the first side 120 .
  • a dielectric layer 114 , a second polysilicon layer 116 for a control gate and a conductive layer 118 are formed on the resulting structure. These layers 114 , 116 , and 118 are formed sequentially in the present implementation.
  • the contact area of the floating gate and the control gate can be increased. Accordingly, the coupling ratio and the programmed threshold voltage Vt can be increased. Furthermore, since this allows the footprint of the polysilicon layer for the floating gate to be reduced, the threshold voltage (Vt) shift due to interference of a cell can be decreased.
  • the present embodiment may be implemented with various non-volatile memory devices including multi-level cell flash memory devices. The present embodiment may be used to scale down to flash memory devices of 50 nm or less.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
US11/618,714 2006-06-28 2006-12-29 Method of manufacturing nand flash memory device Abandoned US20080003744A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060058548A KR100799030B1 (ko) 2006-06-28 2006-06-28 낸드 플래시 메모리 소자의 제조방법
KR10-2006-58548 2006-06-28

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US (1) US20080003744A1 (ja)
JP (1) JP2008010817A (ja)
KR (1) KR100799030B1 (ja)
CN (1) CN100477169C (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090256189A1 (en) * 2008-04-10 2009-10-15 Wei-Ming Liao Two bit u-shaped memory structure and method of making the same
US20110156125A1 (en) * 2007-04-30 2011-06-30 Samsung Electronics Co., Ltd. Nonvolatile semiconductor device including a floating gate and associated systems
CN104658979A (zh) * 2013-11-19 2015-05-27 中芯国际集成电路制造(上海)有限公司 快闪存储器及其形成方法
US20160371674A1 (en) * 2015-06-17 2016-12-22 Lg Electronics Inc. Mobile terminal for authorizing payment at scheduled time and method for controlling the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252153B1 (en) * 2014-09-22 2016-02-02 Macronix International Co., Ltd. Method of word-line formation by semi-damascene process with thin protective conductor layer

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US6248631B1 (en) * 1999-10-08 2001-06-19 Macronix International Co., Ltd. Method for forming a v-shaped floating gate
US6326263B1 (en) * 2000-08-11 2001-12-04 United Microelectronics Corp. Method of fabricating a flash memory cell
US20020160571A1 (en) * 2001-04-30 2002-10-31 Horng-Huei Tseng High coupling ratio stacked-gate flash memory and the method of making the same
US6627947B1 (en) * 2000-08-22 2003-09-30 Lattice Semiconductor Corporation Compact single-poly two transistor EEPROM cell
US20040000694A1 (en) * 1997-11-20 2004-01-01 Johnson Frank S. Bipolar transistor with high breakdown voltage collector
US6680506B2 (en) * 1999-10-08 2004-01-20 Macronix International Co., Ltd. Method for forming a flash memory cell having contoured floating gate surface
US6808989B2 (en) * 2001-03-14 2004-10-26 Micron Technology, Inc. Self-aligned floating gate flash cell system and method
US6903405B2 (en) * 2002-03-20 2005-06-07 Fujitsu Limited Semiconductor memory device with a pair of floating gates
US20060008997A1 (en) * 2002-09-12 2006-01-12 Chuck Jang Atomic layer deposition of interpoly oxides in a non-volatile memory device
US20060068535A1 (en) * 2004-09-04 2006-03-30 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US20060166438A1 (en) * 2004-12-22 2006-07-27 Stmicroelectronics S.R.L. Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling and device thus obtained
US20070257305A1 (en) * 2006-05-01 2007-11-08 Yoshitaka Sasago Nonvolatile semiconductor memory device and manufacturing method thereof
US20070269947A1 (en) * 2006-05-16 2007-11-22 Kuei-Yun Chen Method for manufacturing NAND flash memory
US20080064164A1 (en) * 2006-09-13 2008-03-13 Hynix Semiconductor Inc. Method of manufacturing nonvolatile memory device

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KR20010003086A (ko) * 1999-06-21 2001-01-15 윤종용 플로팅 게이트 형성 방법
KR20020091984A (ko) * 2001-06-01 2002-12-11 삼성전자 주식회사 자기 정렬형 플래시 메모리 장치 및 그 형성 방법
KR20030094443A (ko) * 2002-06-04 2003-12-12 주식회사 하이닉스반도체 플래시 메모리 셀의 플로팅 게이트 형성 방법

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040000694A1 (en) * 1997-11-20 2004-01-01 Johnson Frank S. Bipolar transistor with high breakdown voltage collector
US6680506B2 (en) * 1999-10-08 2004-01-20 Macronix International Co., Ltd. Method for forming a flash memory cell having contoured floating gate surface
US6248631B1 (en) * 1999-10-08 2001-06-19 Macronix International Co., Ltd. Method for forming a v-shaped floating gate
US6326263B1 (en) * 2000-08-11 2001-12-04 United Microelectronics Corp. Method of fabricating a flash memory cell
US6627947B1 (en) * 2000-08-22 2003-09-30 Lattice Semiconductor Corporation Compact single-poly two transistor EEPROM cell
US6808989B2 (en) * 2001-03-14 2004-10-26 Micron Technology, Inc. Self-aligned floating gate flash cell system and method
US20020160571A1 (en) * 2001-04-30 2002-10-31 Horng-Huei Tseng High coupling ratio stacked-gate flash memory and the method of making the same
US6903405B2 (en) * 2002-03-20 2005-06-07 Fujitsu Limited Semiconductor memory device with a pair of floating gates
US20060008997A1 (en) * 2002-09-12 2006-01-12 Chuck Jang Atomic layer deposition of interpoly oxides in a non-volatile memory device
US20060068535A1 (en) * 2004-09-04 2006-03-30 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US20060166438A1 (en) * 2004-12-22 2006-07-27 Stmicroelectronics S.R.L. Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling and device thus obtained
US20070257305A1 (en) * 2006-05-01 2007-11-08 Yoshitaka Sasago Nonvolatile semiconductor memory device and manufacturing method thereof
US20070269947A1 (en) * 2006-05-16 2007-11-22 Kuei-Yun Chen Method for manufacturing NAND flash memory
US20080064164A1 (en) * 2006-09-13 2008-03-13 Hynix Semiconductor Inc. Method of manufacturing nonvolatile memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110156125A1 (en) * 2007-04-30 2011-06-30 Samsung Electronics Co., Ltd. Nonvolatile semiconductor device including a floating gate and associated systems
US8330205B2 (en) * 2007-04-30 2012-12-11 Samsung Electronics Co., Ltd. Nonvolatile semiconductor device including a floating gate and associated systems
US20090256189A1 (en) * 2008-04-10 2009-10-15 Wei-Ming Liao Two bit u-shaped memory structure and method of making the same
US7667262B2 (en) * 2008-04-10 2010-02-23 Nanya Technology Corp. Two bit U-shaped memory structure and method of making the same
CN104658979A (zh) * 2013-11-19 2015-05-27 中芯国际集成电路制造(上海)有限公司 快闪存储器及其形成方法
US20160371674A1 (en) * 2015-06-17 2016-12-22 Lg Electronics Inc. Mobile terminal for authorizing payment at scheduled time and method for controlling the same

Also Published As

Publication number Publication date
CN101097894A (zh) 2008-01-02
JP2008010817A (ja) 2008-01-17
KR100799030B1 (ko) 2008-01-28
CN100477169C (zh) 2009-04-08
KR20080000771A (ko) 2008-01-03

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