US20080001224A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
US20080001224A1
US20080001224A1 US11/812,609 US81260907A US2008001224A1 US 20080001224 A1 US20080001224 A1 US 20080001224A1 US 81260907 A US81260907 A US 81260907A US 2008001224 A1 US2008001224 A1 US 2008001224A1
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insulating film
semiconductor
side wall
semiconductor region
gate
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Atsuhiro Kinoshita
Junji Koga
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KINOSHITA, ATSUHIRO, KOGA, JUNJI
Publication of US20080001224A1 publication Critical patent/US20080001224A1/en
Priority to US12/585,034 priority Critical patent/US8343870B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a MIS field effect transistor the source and drain portions of which are improved and a method of manufacturing the same.
  • the device using a conventional Schottky source-drain has a merit for short channel effect and suppression of junction leakage.
  • the merit of the Schottky source-drain which can inject high-speed carriers into a channel is not always maximally utilized. More specifically, in order to improve the device performance by using an increase in rate of injection by the Schottky source-drain, a device structure must be optimized. However, up to now, it cannot be said that the device structure is optimized.
  • the present invention has been made in consideration of the above circumstances. It is an object of the present invention to provide a semiconductor device having a field effect transistor with a device structure which can achieve improvement of performance by increasing an injection rate of carriers while effectively suppressing a short channel effect and junction leakage, and a method of manufacturing the semiconductor device.
  • a semiconductor device comprises a field effect transistor including: a first semiconductor region of a first conductivity type having a surface portion on which a channel region is formed; a gate electrode formed on the channel region, a gate insulating film in between the gate electrode and the channel region; a source electrode and a drain electrode formed on both the sides of the channel region; second semiconductor regions of a second conductivity type formed between the source electrode and the channel region and between the drain electrode and the channel region to serve as extension regions of a source and a drain; third semiconductor regions of the second conductivity type formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions and having an impurity concentration higher than that of the second semiconductor region; and side wall insulating films formed on both the side surfaces of the gate electrode, the side wall insulating films being separated from the source electrode and the drain electrode.
  • a method for producing the field effect transistor according to another embodiment of the present invention comprises: forming a gate electrode on a first semiconductor region of a first conductivity type, a gate insulating film in between, and side wall insulating films on both side surfaces of the gate electrode; ion-implanting an impurity in the first semiconductor region by using the gate electrode and the side wall insulating film as masks to form second semiconductor regions of a second conductivity type serving as extension regions of a source and a drain; forming second side wall insulating films on both side surfaces of the side wall insulating film; and siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.
  • a method for producing the field effect transistor comprises: forming a gate electrode on a first semiconductor region of a first conductivity type, a gate insulating film in between; forming side wall insulating films each having a footing-bottom shape at a lower surface side thereof on both side surfaces of the gate electrode; ion-implanting an impurity in the first semiconductor region by using the gate electrode and the side wall insulating film as masks to form second semiconductor regions of a second conductivity type serving as extension regions of a source and a drain; and siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.
  • a method for producing the field effect transistor comprises: forming a gate electrode on a part of a first semiconductor region of a first conductivity type, a gate insulating film in between; depositing an insulating film serving as a side wall insulating film of the gate electrode; maximally etching the insulating film serving as the side wall insulating film by anisotropic etching not to expose an underlying layer; ion-implanting an impurity in the first semiconductor region from above the insulating film serving as the side wall insulating film to form second semiconductor regions of a second conductivity type serving as extension regions of a source and a drain; etching the insulating film serving as the side wall insulating film which is maximally etched not to expose the underlying layer to form side wall insulating films each having a footing-bottom shape at a lower surface side thereof on both side surfaces of the gate electrode, siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second
  • a semiconductor device having a field effect transistor with a device structure which can achieve improvement of performance by increasing an injection rate of carriers while effectively suppressing a short channel effect and junction leakage, and a method of manufacturing the semiconductor device.
  • FIG. 1 is across-sectional view showing an device structure of a MIS field effect transistor according to a first embodiment
  • FIGS. 2A and 2B are band diagram for explaining operation and effect of the first embodiment
  • FIG. 3 is a diagram showing a dependence of a drain current on a separation distance
  • FIG. 4 is a diagram showing a dependence of an increasing rate of the drain current in a gate length
  • FIG. 5 is a diagram showing a dependence of an increasing rate of the drain current on EOT
  • FIG. 6 is a diagram showing a dependence of the drain current on a side wall thickness
  • FIGS. 7 to 13 are cross-sectional views showing a first manufacturing step for the MIS field effect transistor according to the first embodiment
  • FIG. 14 is a diagram showing a dependence of an increasing rate of the drain current on a substrate etching amount
  • FIGS. 15 to 20 are cross-sectional views showing the second manufacturing step for the MIS field effect transistor according to the first embodiment
  • FIGS. 21 to 23 are cross-sectional views showing a third manufacturing step for the MIS field effect transistor according to the first embodiment
  • FIG. 24 is a cross-sectional view showing an device structure of a MIS field effect transistor according to a second embodiment
  • FIG. 25 is a cross-sectional view showing an device structure of a MIS field effect transistor according to a third embodiment.
  • FIGS. 26 to 34 are cross-sectional views showing an device structure of a MIS field effect transistor according to a fourth embodiment.
  • FIG. 1 is a sectional view showing an device structure of a MIS field effect transistor according to a first embodiment.
  • a polysilicon gate electrode 102 is formed on a p-type silicon substrate (first semiconductor region) 100 a gate insulating film 101 in between.
  • a gate silicide 103 is formed on the polysilicon gate electrode 102 .
  • the gate electrode 102 is made of polysilicon.
  • a metal gate structure in which the polysilicon gate electrode 102 and the gate silicide 103 are replaced by a single metal layer may be employed.
  • a gate side wall insulating film 104 constituted by a silicon nitride film is formed on both the side surfaces of the gate electrodes 102 and 103 .
  • Source and drain regions are formed in the silicon substrate 100 to interpose a channel region under the polysilicon gate electrode 102 .
  • the source and drain regions are constituted by, an n-type extension diffusion layer (second semiconductor region) 105 using, for example, As as an impurity, source and drain suicides (source electrode and drain electrode) 107 made of, for example, nickel silicide (NiSi), and an n + -type high-concentration impurity layer (third semiconductor region) 106 using, for example, As as an impurity.
  • the n + -type high-concentration impurity layer 106 is formed between the source and drain electrodes 107 and the silicon substrate 100 and the n-type extension diffusion layer 105 .
  • the n + -type high-concentration impurity layer 106 has an impurity concentration higher than that of the n-type extension diffusion layer 105 .
  • the impurity of the n + -type high-concentration impurity layer 106 is formed by segregating the impurity of the n-type extension diffusion layer 105 in manufacturing of the source and drain electrodes 107 .
  • a characteristic feature of the embodiment is to have a structure in which, as shown in FIG. 1 , an interface of the source and drain suicides 107 is separated (offset) from the gate side wall insulating film 104 (L 1 >0).
  • FIG. 2A includes a sectional view and a band diagram of a field effect transistor according to the embodiment in which a gate side wall insulating film is separated from a source-drain silicide interface (L 1 >0).
  • FIG. 2B includes a sectional view and a band diagram of a field effect transistor using a conventional Schottky source and drain in which a gate side wall insulating film is overlapped on a source-drain silicide (L 1 ⁇ 0).
  • an energy difference ( ⁇ E) is given between a Fermi level of the source and a potential top of the channel to increase an injection rate of carriers.
  • ⁇ E energy difference
  • FIG. 2B when a source metal or a source silicide is excessively close to a gate electrode as in a conventional field effect transistor, a Schottky barrier of the source moderates a gate electric field to make it impossible to increase the injection rate of carriers.
  • an electric flux line of the gate electric field which goes around the gate electrode from the gate electrode side surface is terminated.
  • the structure of the embodiment in which the interface of the source-drain silicide 107 is separated (offset) (L 1 >0) from the gate side wall insulating film 104 is employed to make it possible to obtain the operation and effect that suppress a decrease in injection rate of carriers from the source.
  • the operation and effect of the embodiment are especially effective when the material constituting the gate side wall insulating film has a dielectric constant higher than that of the upper layer film of the gate side wall insulating film, for example, when the gate side wall insulating film and the upper layer film are a silicon nitride film and a silicon oxide film, respectively.
  • This is because convergence of an electric line of force on the interface of the gate electric field which goes around the gate electrode from the gate electrode side surface becomes conspicuous.
  • the dielectric constants are equal to each other, for example, even though both the gate side wall insulating film and the upper layer film are silicon nitride films, the electric line of force of the gate electric field is terminated due to the influence of an interface level existing on the interface. For this reason, the operation and effect as those described above are obtained as well.
  • Parameters to which conditions are not assigned are calculated to be fixed to the reference values.
  • the side wall thickness and the separation distance (L 1 ) are calculated such that the side wall thickness and the separation distance are symmetrically changed with respect to a gate in both the side directions.
  • a field effect transistor using a diffusion layer as a source-drain having an equivalent standby current characteristic is used as an object to be compared.
  • FIG. 3 shows dependence of a drain current on a separation distance (L 1 ) between the gate side wall insulating film and the source-drain silicide interface.
  • the gate side wall thickness is calculated from three conditions (10 nm, 12 nm, and 14 nm). As is apparent from FIG. 3 , it is observed that, regardless of the side wall thickness, the drain current sharply increases from a region in which the separation distance L 1 exceeds 0. Furthermore, when the separation distance increases, the drain current begins to decrease. This is because a diffusion layer resistance increases when the length of separation portion increases.
  • the separation distance L 1 is desirably larger than 0 and 30 nm or less. This is because in the region a drain current becomes larger than that of a conventional field effect transistor in which a source-drain silicide interface and a side wall insulating film overlap. Furthermore, the separation distance L 1 is desirably 4 nm or more and 20 nm or less. This is because a drain current has a maximal value in this region.
  • FIG. 4 shows a dependence of an increasing rate of a drain current on a gate length (L).
  • the gate length (L) is desirably 80 nm or less which is equal to or more than that of a conventional field effect transistor. Furthermore, the gate length (L) is desirably less than 30 nm where an increasing rate of the drain current is 10% or more (1.1 times the drain current).
  • FIG. 5 shows a dependence of an increasing rate of a drain current on a gate insulating film EOT.
  • EOT decreases in thickness
  • a drain current characteristic is improved in comparison with a conventional field effect transistor in which a diffusion layer is used as a source-drain region. This is because the EOT decreases in thickness to make it possible to more effectively modulate a potential of the segregation layer 106 ( FIG. 1 ) through the n-type extension diffusion layer 105 ( FIG. 1 ). Therefore, the injection rate of carriers can be improved without increasing a parasitic resistance.
  • the gate insulating film EOT is desirably set at 4 nm or more which is equal to or larger than the characteristic of the conventional field effect transistor such that an increasing rate of the drain current is 0% or more. Furthermore, the gate insulating EOT is desirably 1.3 nm or less at which the drain current further increases.
  • FIG. 6 shows a dependence of a drain current of the gate side wall insulating film thickness.
  • a drain current characteristic is deteriorated as the side wall thickness increases. This is because, when the side wall thickness increases, influence of a parasitic resistance of an extension diffusion layer under the side wall increases.
  • the side wall thickness is desirably 10 nm or less at which deterioration of a drain current characteristic is not conspicuous, and is more desirably 8 nm or less at which the deterioration of the drain current characteristic is not observed.
  • an impurity concentration of the n + -type high-concentration impurity layer 106 in interfaces between the impurity layer and the source and the drain electrode is desirably 8 ⁇ 10 19 to 5 ⁇ 10 20 atoms/cm 3
  • an impurity concentration at a depth of 20 nm from the interfaces between the impurity layer and the source and drain electrode is desirably 1/10 or less the impurity concentration in the interfaces between the impurity layer and the source and drain electrode. More specifically, a depth of a point at which an impurity concentration decreases to 1/10 from the interface is desirably 20 nm or less.
  • the n-type extension diffusion layer 105 desirably has a maximum impurity concentration in a gate insulating film interface, the maximum impurity concentration is desirably 1 ⁇ 2 or less the impurity concentration of the n + -type high-concentration impurity layer 106 in the interfaces between the impurity layer 106 and the source and the drain electrode, and an impurity concentration at a depth of 30 nm from the gate insulating film interface is desirably 1/10 or less the concentration in the gate insulating film interface. More specifically, the depth of the point at which the impurity concentration decreases to 1/10 from the interface is desirably 30 nm or less. This is because, when the concentration and the depth are equal to or larger than the given concentration and the given depth, respectively, an off current increases due to the influence of a short channel effect.
  • a first manufacturing method for the field effect transistor according to the embodiment will be described below with reference to FIGS. 7 to 12 .
  • a device isolation region (not shown) is formed on the p-type silicon substrate (first semiconductor region) 100 having a (100) orientation plane.
  • the gate insulating film 101 is formed to have an EOT of about 1.2 nm.
  • a polysilicon film serving as the gate electrode 102 is deposited by a low-pressure chemical vapor deposition (to be also referred to as LP-CVD hereinafter) method to have a thickness of about 100 to 150 nm.
  • LP-CVD low-pressure chemical vapor deposition
  • RIE reactive ion etching
  • a silicon nitride film is deposited by the LP-CVD method to have a thickness of about 8 nm. Thereafter, the silicon nitride film is etched back by the RIE method to cause the silicon nitride film to be left on only a side surface portion of the gate electrode 102 . In this manner, the gate side wall insulating film 104 is formed. In this case, only the single silicon nitride film is used as the side wall.
  • n-type extension layer (second semiconductor region) 105 As shown in FIG. 9 , As having a dose of 2 ⁇ 10 15 cm ⁇ 2 or more is ion-implanted as an impurity at 2 KeV or less (more desirably, 1 KeV or less) to form the n-type extension layer (second semiconductor region) 105 .
  • spike annealing at 1030 to 1050° C. is performed to activate the impurity.
  • a TEOS oxide film is deposited by the LP-CVD method to have a thickness of about 10 nm and etched back by the RIE method to form a second side wall insulating film 112 .
  • Ni is sputtered in a thickness of 7 to 11 nm (more desirably, 9 nm or less) and heat-treated at 350° C. for 30 seconds, as shown in FIG. 11 .
  • silicon of source, drain, and gate electrodes is silicided.
  • silicide is performed up to a position deeper than the n-type extension layer 105 .
  • unreacted Ni is removed with a mixed solution of a sulfuric acid and a hydrogen peroxide solution or the like.
  • heat treatment is performed at 500° C. for about 30 seconds to form the source-drain silicide 107 and the silicon substrate 100 and the gate silicide 103 .
  • an As impurity in the n-type extension layer 105 is segregated by siliciding.
  • the n + -type high-concentration impurity layer 106 having a concentration higher than that of the n-type extension layer 105 is formed in the interface between the source-drain silicide 107 and the n-type extension layer 105 .
  • the second side wall insulating film 112 formed by the TEOS oxide film is peeled with a diluted hydrofluoric acid or the like to make it possible to obtain the structure shown in FIG. 1 .
  • the deposited film thickness of the TEOS oxide film forming the second side wall insulating film 112 is changed, so that the separation distance (L 1 ) of the interface between the gate side wall insulating film 104 and the source-drain silicide 107 can be set to a desired value.
  • control of an amount of substrate etching is important when the TEOS oxide film is etched back by the RIE method to form the second side wall insulating film 112 .
  • the silicon substrate 100 is etched by overetching.
  • the amount of substrate etching means a thickness at which the silicon is etched from the silicon substrate surface by overetching in a direction of depth in the etch-back operation.
  • FIG. 14 shows a relationship between the amount of substrate etching at this time and an increasing rate of a drain current.
  • simulation is performed such that parameters other than the amount of substrate etching are fixed to the reference values described above.
  • a drain current characteristic is degraded. This is because the separation distance L 1 is substantially shortened or the side wall insulating film and the source-drain silicide overlap since formation of the source-drain silicide 107 extends toward the gate insulating film by etching the substrate.
  • etching conditions and etching time are desirably controlled such that the amount of substrate etching is set to 8 nm or less which obtain a drain current having an increasing rate of 0% or more, i.e., equal to or larger than that of conventional field effect transistor characteristics, more preferably, 6 nm or less at which the drain current further increases.
  • the amount of substrate etching is desirably controlled at the minimum.
  • the gate insulating film 101 and the gate electrode 102 are formed as in the first manufacturing method. If necessary, post oxidation is performed in a thickness of 1 to 2 nm.
  • a silicon nitride film is deposited by the LP-CVD method to have a thickness of about 8 nm and etched back to form the gate side wall insulating film 104 .
  • the gate side wall insulating film 104 is processed to have a footing-bottom shape (or tailed shape) at a lower side surface as shown in FIG. 16 .
  • This process can be performed, for example, by the RIE method with a footing-bottom condition selected.
  • the degree of footing bottom is controlled by etching conditions to control a final separation distance L 1 .
  • the n-type extension layer 105 is formed and activated by the same method as the first manufacturing method.
  • the source-drain silicide 107 and the gate silicide 103 are formed as in the same method as the first manufacturing method.
  • the n + -type high-concentration impurity layer (third semiconductor region) 106 is formed in the interface between the source-drain silicide 107 and the silicon substrate 100 .
  • the interface of the source-drain silicide 107 is located near the foot of the gate side wall insulating film 104 .
  • the foot of the gate side wall insulating film 104 is removed to obtain the structure shown in FIG. 1 .
  • the removal of the foot may be performed by a wet etching process after the formation of the source-drain silicide 107 or may be performed by an RIE method having strong isotropy.
  • the step of forming a second sidewall insulating film is unnecessary. For this reason, the manufacturing steps of the second manufacturing method can be simplified in comparison with the first manufacturing method.
  • etching conditions and etching time are desirably controlled such that the amount of substrate etching is set to 8 nm or less at which a drain current has an increasing rate of 0% or more, and more preferably, 6 nm or less at which the drain current further increases.
  • the n-type extension layer 105 is formed after the etch-back process in the RIE in the second manufacturing method. For this reason, a problem of removal of the n-type extension layer 105 is not occurred.
  • the following third manufacturing method can also be used. More specifically, as in the first and second manufacturing methods, the gate insulating film 101 and the gate electrode 102 are formed by patterning. Thereafter, as shown in FIG. 21 , a silicon nitride film is deposited by the LP-CVD method to have a thickness of about 8 nm. The silicon nitride film is etched back by anisotropic etching such as an RIE method. At this time, a silicon nitride film having a thickness of about 1 nm is left on the surface of the silicon substrate 100 . More specifically, the silicon nitride film is maximally etched not to expose the p-type silicon substrate 100 .
  • As (Arsenic) having a dose of 2 ⁇ 10 15 cm ⁇ 2 or more is ion-implanted as an impurity at 2 KeV or less, more desirably 1 KeV or less, to form the n-type extension layer 105 .
  • spike annealing at 1030 to 1050° C. is performed to activate the impurity.
  • the silicon nitride film on the surface of the p-type silicon substrate 100 is removed to form the gate side wall insulating film 104 .
  • the gate side wall insulating film 104 is processed to have a footing-bottom shape on the surface of the silicon substrate 100 .
  • This process can be performed, for example, by isotropic wet etching such as diluted hydrofluoric acid treatment, high-temperature phosphoric acid treatment, or hydrofluoric glycerol treatment.
  • the subsequent steps are the same as those in the second manufacturing method.
  • the amount of etching of the substrate 100 can be minimized by using wet etching which can have selectivity to the silicon substrate 100 higher than that in the RIE method.
  • the field effect transistor according to the embodiment described above has a self-aligned silicide structure.
  • An interface between the silicide of the source-drain portion and the silicon substrate is separated from the gate side wall insulating film.
  • the interface is covered with an impurity layer having a steep impurity concentration profile at a desired concentration or more. Therefore, improvement of performance by increasing an injection rate of carriers and improvement of element reliability can be achieved while suppressing punch through and leakage current.
  • FIG. 24 is a cross-sectional view showing an device structure of a MIS field effect transistor according to a second embodiment of the present invention. Since the MIS field effect transistor is the same as that in the first embodiment except that an HALO diffusion layer (fourth semiconductor region) 201 is formed, a description thereof will be omitted.
  • the HALO diffusion layer 201 is a p-type region the impurity type of which is the same as that of a silicon substrate 100 , and has an impurity concentration higher than that of the silicon substrate 100 as a characteristic feature.
  • the field effect transistor according to the embodiment includes the HALO diffusion layer 201 to obtain the operation and effect of the first embodiment and to achieve improvement of a roll-off characteristic.
  • FIG. 25 is a cross-sectional view showing an device structure of a MIS field effect transistor according to a third embodiment of the present invention. Since the MIS field effect transistor according to the third embodiment is the same as that of the first embodiment except that an n + -type deep diffusion layer (fifth semiconductor region) 301 is formed, a description thereof will be omitted.
  • the n + -type deep diffusion layer 301 is formed between an n + -type high-concentration impurity layer 106 and the silicon substrate 100 , and has a thickness of, for example, about 50 nm.
  • the field effect transistor according to the embodiment includes the n + -type deep diffusion layer 301 to obtain the operation and effect of the first embodiment and to achieve a considerable reduction in junction leakage from the source-drain bottom portion.
  • the n + -type deep diffusion layer 301 can be made shallower or can have a concentration lower than a deep diffusion layer applied to a MOSFET using a normal diffusion layer as a source-drain region. Therefore, it is also a characteristic feature of the embodiment that a punch through current can be suppressed.
  • FIG. 26 is a cross-sectional view showing an element structure of a MIS field effect transistor according to a fourth embodiment of the present invention. Since the MIS field effect transistor according to the fourth embodiment is the same as that of the first embodiment except that an HALO diffusion layer (fourth semiconductor region) 201 and an n + -type deep diffusion layer (fifth semiconductor region) 301 are formed, a description thereof will be omitted.
  • both the HALO diffusion layer 201 and the n + -type deep diffusion layer 301 are formed to make it possible to simultaneously realize improvement of the roll-off characteristic and a considerable reduction in junction leakage as described above.
  • a method of manufacturing a field effect transistor according to the embodiment will be described below with reference to FIGS. 27 to 34 .
  • an device isolation region (not shown) is formed on the p-type silicon substrate (first semiconductor region) 100 having a (100) orientation plane.
  • the gate insulating film 101 is formed to have an EOT of about 1.2 nm.
  • a polysilicon film serving as the gate electrode 102 is deposited by a low-pressure chemical vapor deposition (to be also referred to as LP-CVD hereinafter) method to have a thickness of about 100 to 150 nm.
  • the gate insulating film 101 and the gate electrode 102 are formed by patterning by a lithography technique and an etching technique such as a reactive ion etching (to be also referred to as RIE hereinafter). If necessary, post oxidation is performed in a thickness of 1 to 2 nm.
  • a silicon nitride film is deposited by the LP-CVD method or the like to have a thickness of about 24 nm. Thereafter, the silicon nitride film is etched back by the RIE method to form dummy gate side wall insulating films 121 on both the side surfaces of the gate electrode 102 .
  • spike annealing at 1050° C. may be performed to activate the impurity.
  • the dummy gate side wall insulating films 121 are removed by wet etching or the like. Subsequently, as shown in FIG. 30 , a silicon nitride film is deposited by the LP-CVD method to have a thickness of about 8 nm. Thereafter, the silicon nitride film is etched back by the RIE method to leave the silicon nitride film on only a side surface portion of the gate electrode 102 . In this manner, the gate side wall insulating film 104 is formed. In this case, only the single silicon nitride film is used as the side wall. However, a dual side wall insulating film obtained by laminating a TEOS oxide film and a silicon nitride film is desirably formed in terms of reliability as in the first embodiment.
  • As an impurity B or BF 2 is ion-implanted to form an HALO diffusion layer 201 .
  • spike annealing at 1030 to 1050° C. is performed to activate the impurity.
  • a TEOS oxide film is deposited by the LP-CVD method to have a thickness of about 10 nm and etched back by the RIE method to form a second side wall insulating film 112 .
  • Ni is sputtered in a thickness of 7 to 11 nm (more desirably, 9 nm or less), as shown in FIG. 33 .
  • heat treatment is performed at 350° C. for about 30 seconds to silicide silicon of source, drain, and gate electrodes.
  • silicide is performed up to a position deeper than the n-type extension layer 105 .
  • unreacted Ni is removed with a mixed solution of a sulfuric acid and a hydrogen peroxide solution or the like. Furthermore, heat treatment is performed at 500° C.
  • the source-drain silicide 107 and the gate silicide 103 are formed.
  • an As impurity in the n-type extension layer 105 is segregated by siliciding.
  • the n + -type high-concentration impurity layer 106 is formed.
  • the second side wall insulating film formed by the TEOS oxide film is removed with a diluted hydrofluoric acid or the like to obtain the structure shown in FIG. 26 .
  • the present invention is not limited to the above embodiments.
  • an n-channel MIS field effect transistor is described.
  • the present invention can be also applied to a p-channel MIS field effect transistor.
  • the description is made by using As as impurities in the second and third semiconductor regions, but the impurity is not limited to As.
  • an impurity can also be selected from elements such as P serving as a donor.
  • the impurity can be selected from elements such as B serving as an acceptor.
  • silicon is used as a semiconductor substrate material, the semiconductor substrate material is not limited to silicon. Silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), aluminum nitride (AlN), or the like can be used.
  • the orientation of the substrate material is not limited to a (100) orientation plane.
  • a (110) orientation plane, a (111) orientation plane or the like can be properly selected.
  • the present invention can also be applied to any MIS field effect transistor, including a three-dimensional structure such as an Fin structure or a double-gate structure.
  • various modifications of the present invention can be effected without departing from the spirit and scope of the invention.
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