US20070102731A1 - Semiconductor memory device and method of manufacturing the same - Google Patents

Semiconductor memory device and method of manufacturing the same Download PDF

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Publication number
US20070102731A1
US20070102731A1 US11/552,705 US55270506A US2007102731A1 US 20070102731 A1 US20070102731 A1 US 20070102731A1 US 55270506 A US55270506 A US 55270506A US 2007102731 A1 US2007102731 A1 US 2007102731A1
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insulating film
semiconductor substrate
gate wiring
region
element isolation
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Eiji Sakagami
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Toshiba Corp
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Individual
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAKAGAMI, EIJI
Publication of US20070102731A1 publication Critical patent/US20070102731A1/en
Priority to US12/354,908 priority Critical patent/US8043930B2/en
Priority to US13/267,495 priority patent/US20120025295A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to a nonvolatile semiconductor memory device having a layered gate structure with a shallow trench isolation (STI) element isolation insulating film and a method of manufacturing the same.
  • STI shallow trench isolation
  • STI shallow trench isolation
  • the width of STI in the memory cell region is minimized, and the STI is made shallow to minimize the aspect ratio in gap filling so as to ensure the STI gap filling capability.
  • the dielectric isolation between elements is more necessary than memory cells.
  • the STI in the peripheral circuit region is deeper than the STI in the memory cell region (see e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-368077).
  • the STI cannot be deepened because of the restrictions on the STI gap filling capability. Instead, in the peripheral circuit region, the STI is made higher than in the memory cell region. In this case, however, the following problems are posed.
  • the STI is high in the peripheral circuit region and low in the memory cell region. For this reason, the height from the surface of the silicon substrate to the mask material of the gate wiring is large in the peripheral circuit region and small in the memory cell region.
  • CMP chemical mechanical polishing
  • a barrier layer deposited on the mask material of the gate wiring is used as the stopper of CMP.
  • the barrier layer in the peripheral circuit region where the mask material is high is excessively polished by CMP. For this reason, the barrier layer on the peripheral circuit region side becomes thin at the boundary between the memory cell region and the peripheral circuit region, or the barrier layer is completely lost.
  • the difference in height to the barrier layer between the peripheral circuit region and the memory cell region influences metal interconnection formation to be performed later.
  • a resolution failure occurs in lithography at the step portion of the boundary region.
  • a semiconductor memory device comprising a semiconductor substrate which has a first region and a second region, a first element isolation insulating film which is formed in the semiconductor substrate in the first region, includes a first upper surface higher than an upper surface of the semiconductor substrate and a first bottom surface lower than the upper surface of the semiconductor substrate, and has a first height from the upper surface of the semiconductor substrate to the first upper surface, a second element isolation insulating film which is formed in the semiconductor substrate in the second region, includes a second upper surface higher than the upper surface of the semiconductor substrate and a second bottom surface lower than the upper surface of the semiconductor substrate, and has a second height from the upper surface of the semiconductor substrate to the second upper surface, the second height being larger than the first height, a first gate insulating film which is formed on the semiconductor substrate in the first region, a first gate wiring which is formed on the first gate insulating film, a first mask layer which is formed on the first gate wiring, a second gate insulating film which is formed on the
  • a semiconductor memory device manufacturing method comprising, in a semiconductor substrate having a first region and a second region, forming a first gate insulating film on the semiconductor substrate in the first region and forming a second gate insulating film on the semiconductor substrate in the second region, forming a first gate wiring material on the first gate insulating film and the second gate insulating film, forming a first element isolation insulating film by partially removing the first gate wiring material, the first gate insulating film, and the semiconductor substrate and forming a second element isolation insulating film by partially removing the first gate wiring material, the second gate insulating film, and the semiconductor substrate, making a first height from an upper surface of the semiconductor substrate to an upper surface of the first element isolation insulating film smaller than a second height from the upper surface of the semiconductor substrate to an upper surface of the second element isolation insulating film by removing an upper portion of the first element isolation insulating film, forming a second gate wiring material, third gate wiring material, and
  • a semiconductor memory device manufacturing method comprising, in a semiconductor substrate having a first region and a second region, forming a first gate insulating film on the semiconductor substrate in the first region and forming a second gate insulating film on the semiconductor substrate in the second region, forming a first gate wiring material on the first gate insulating film and the second gate insulating film, forming a first element isolation insulating film by partially removing the first gate wiring material, the first gate insulating film, and the semiconductor substrate and forming a second element isolation insulating film by partially removing the first gate wiring material, the second gate insulating film, and the semiconductor substrate, making a first height from an upper surface of the semiconductor substrate to an upper surface of the first element isolation insulating film smaller than a second height from the upper surface of the semiconductor substrate to an upper surface of the second element isolation insulating film by removing an upper portion of the first element isolation insulating film, forming a second gate wiring material in the first region, forming
  • FIG. 1 is a sectional view showing a semiconductor memory device having a memory cell region and peripheral circuit region according to the first embodiment of the present invention
  • FIG. 2A is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line IIA-IIA in FIG. 1 ;
  • FIG. 2B is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line IIB-IIB in FIG. 1 ;
  • FIG. 2C is a sectional view showing the semiconductor memory device in the memory cell region taken along a line IIC-IIC in FIG. 1 ;
  • FIG. 2D is a sectional view showing the semiconductor memory device in the memory cell region taken along a line IID-IID in FIG. 1 ;
  • FIGS. 3, 4 , 5 , 6 , 7 , and 8 are sectional views showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the first embodiment of the present invention
  • FIG. 9A is a sectional view showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the first embodiment of the present invention following FIG. 8 ;
  • FIG. 9B is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line IXB-IXB in FIG. 9A ;
  • FIG. 9C is a sectional view showing the semiconductor memory device in the memory cell region taken along a line IXC-IXC in FIG. 9A ;
  • FIG. 10A is a sectional view showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the first embodiment of the present invention following FIG. 9A ;
  • FIG. 10B is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line XB-XB in FIG. 10A ;
  • FIG. 10C is a sectional view showing the semiconductor memory device in the memory cell region taken along a line XC-XC in FIG. 10A ;
  • FIG. 11A is a sectional view showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the first embodiment of the present invention following FIG. 10A ;
  • FIG. 11B is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line XIB-XIB in FIG. 11A ;
  • FIG. 11C is a sectional view showing the semiconductor memory device in the memory cell region taken along a line XIC-XIC in FIG. 11A ;
  • FIG. 12 is a sectional view showing a semiconductor memory device having a memory cell region and peripheral circuit region according to the second embodiment of the present invention.
  • FIGS. 13 and 14 are sectional views showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the second embodiment of the present invention.
  • FIG. 15A is a sectional view showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the second embodiment of the present invention following FIG. 14 ;
  • FIG. 15B is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line XVB-XVB in FIG. 15A ;
  • FIG. 15C is a sectional view showing the semiconductor memory device in the memory cell region taken along a line XVC-XVC in FIG. 15A ;
  • FIG. 16A is a sectional view showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the second embodiment of the present invention following FIG. 15A ;
  • FIG. 16B is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line XVIB-XVIB in FIG. 16A ;
  • FIG. 16C is a sectional view showing the semiconductor memory device in the memory cell region taken along a line XVIC-XVIC in FIG. 16A ;
  • FIG. 17 is a sectional view showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the second embodiment of the present invention following FIG. 16A .
  • a nonvolatile semiconductor memory has two kinds of self-aligned shallow trench isolation (STI) element isolation insulating films (element isolation regions) which are shallow in a memory cell region and deep in a peripheral circuit region.
  • STI shallow trench isolation
  • element isolation regions element isolation insulating films
  • the height of STI under the gate wiring in the peripheral circuit region is larger than that of STI under the gate wiring in the memory cell region.
  • the height from the upper surface of a semiconductor substrate to the mask layer of the gate wiring is equal in the memory cell region and peripheral circuit region.
  • FIG. 1 is a sectional view showing a semiconductor memory device having a memory cell region and peripheral circuit region according to the first embodiment of the present invention.
  • FIG. 2A is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line IIA-IIA in FIG. 1 .
  • FIG. 2B is a sectional view showing the semiconductor memory device in the peripheral circuit region taken along a line IIB-IIB in FIG. 1 .
  • FIG. 2C is a sectional view showing the semiconductor memory device in the memory cell region taken along a line IIC-IIC in FIG. 1 .
  • FIG. 2D is a sectional view showing the semiconductor memory device in the memory cell region taken along a line IID-IID in FIG. 1 .
  • the semiconductor memory device according to the first embodiment will be described below.
  • the first embodiment is directed to a nonvolatile semiconductor memory having a memory cell region and peripheral circuit region.
  • the nonvolatile semiconductor memory are a NAND flash memory and NOR flash memory.
  • a tunnel insulating film 12 is formed on a semiconductor substrate (silicon substrate) 11 .
  • a floating gate electrode FG is formed on the tunnel insulating film 12 .
  • An oxide nitride oxide (ONO) insulating film 21 is formed on the floating gate electrode FG.
  • a control gate electrode CG is formed on the ONO insulating film 21 .
  • the floating gate electrode FG includes a polysilicon layer 14 .
  • the control gate electrode CG includes two polysilicon layers 22 and 24 .
  • a WSi (tungsten silicide) film 25 is formed on the control gate electrode CG.
  • a mask layer 26 is formed on the WSi film 25 .
  • a plurality of element isolation insulating films STI 1 with an STI structure are formed in the semiconductor substrate 11 in the memory cell region.
  • the element isolation insulating film STI 1 has a first portion STI 1 -A located under the control gate electrode CG and a second portion STI 1 -B located under a spacer 29 .
  • the element isolation insulating film STI 1 at an end of each of the plurality of cell transistors Tr 1 includes the first portion STI 1 -A and second portion STI 1 -B.
  • the upper surface of the first portion STI 1 -A of the element isolation insulating film STI 1 is higher than the upper surface of the semiconductor substrate 11 and is flush with, e.g., the upper surface of the tunnel insulating film 12 .
  • the upper surface of the second portion STI 1 -B of the element isolation insulating film STI 1 is almost flush with the upper surface of the semiconductor substrate 11 .
  • the bottom surfaces of the first and second portions STI 1 -A and STI 1 -B of the element isolation insulating film STI 1 have the same depth.
  • the bottom surfaces are deeper than the upper surface of the semiconductor substrate 11 and also deeper than the bottom surface of the diffusion layer (not shown) of the cell transistor Tr 1 .
  • the floating gate electrode FG and tunnel insulating film 12 are self-aligned to the element isolation insulating film STI 1 . For this reason, the width of the floating gate electrode FG and tunnel insulating film 12 in the gate width direction equals the distance between the element isolation insulating films STI 1 .
  • a gate insulating film 13 is formed on the semiconductor substrate 11 .
  • a gate wiring G is formed on the gate insulating film 13 .
  • a plurality of peripheral transistors Tr 2 are formed.
  • the gate wiring G includes the two polysilicon layers 14 and 24 .
  • the WSi film 25 is formed on the gate wiring G.
  • the mask layer 26 is formed on the WSi film 25 .
  • a plurality of element isolation insulating films STI 2 with an STI structure are formed in the semiconductor substrate 11 in the peripheral circuit region.
  • the element isolation insulating film STI 2 has a first portion STI 2 -A located under part of the gate wiring G (polysilicon layer 24 ) and a second portion STI 2 -B located under the spacer 29 .
  • the upper surface of the first portion STI 2 -A of the element isolation insulating film STI 2 is higher than the upper surface of the semiconductor substrate 11 and is flush with, e.g., the upper surface of the polysilicon layer 14 .
  • the upper surface of the second portion STI 2 -B of the element isolation insulating film STI 2 is almost flush with the upper surface of the semiconductor substrate 11 .
  • the bottom surfaces of the first and second portions STI 2 -A and STI 2 -B of the element isolation insulating film STI 2 have the same depth.
  • the bottom surfaces are deeper than the upper surface of the semiconductor substrate 11 and also deeper than the bottom surface of the diffusion layer (not shown) of the peripheral transistor Tr 2 .
  • the polysilicon layer 14 of the gate wiring G and the gate insulating film 13 are self-aligned to the element isolation insulating film STI 2 . For this reason, the width of the polysilicon layer 14 of the gate wiring G and the gate insulating film 13 in the gate width direction equals the distance between the element isolation insulating films STI 2 .
  • a barrier layer 30 is formed on the mask layer 26 in the memory cell region and peripheral circuit region. Insulating films 31 and 32 are formed on the barrier layer 30 . Contacts C 1 and C 2 connected to the WSi film 25 through the insulating film 32 , barrier layer 30 , and mask layer 26 are formed. The contact C 1 is located above the element isolation insulating film STI 1 . The contact C 2 is located above the element isolation insulating film STI 2 .
  • a height h 2 from the upper surface of the semiconductor substrate 11 to the upper surface of the mask layer 26 in the peripheral circuit region equals a height h 1 from the upper surface of the semiconductor substrate 11 to the upper surface of the mask layer 26 in the memory cell region.
  • a height X 2 (to be referred to as a height X 2 of the element isolation insulating film STI 2 hereinafter) from the upper surface of the semiconductor substrate 11 to the upper surface of the first portion STI 2 -A of the element isolation insulating film STI 2 in the peripheral circuit region is larger than a height X 1 (to be referred to as a height X 1 of the element isolation insulating film STI 1 hereinafter) from the upper surface of the semiconductor substrate 11 to the upper surface of the first portion STI 1 -A of the element isolation insulating film STI 1 in the memory cell region.
  • the height X 2 of the element isolation insulating film STI 2 is preferably twice or more the height X 1 of the element isolation insulating film STI 1 .
  • the reason for this is as follows.
  • the control gate electrode CG and semiconductor substrate 11 in the memory cell region are insulated by at least the tunnel insulating film 12 and ONO insulating film 21 .
  • the height X 2 of the element isolation insulating film STI 2 must be equal to or more than (thickness of tunnel insulating film 12 +thickness of ONO insulating film 21 ).
  • the upper limit value of the height X 2 of the element isolation insulating film STI 2 is preferably equal to or smaller than the height of the polysilicon layer 14 of the gate wiring G.
  • the reason for this is as follows. If the height X 2 of the element isolation insulating film STI 2 is larger than the height of the polysilicon layer 14 , the height of the gate wiring G becomes larger on the element isolation insulating film STI 2 than on the active region to generate a step difference. Hence, in CMP planarization of the buried insulating film 31 , erosion (dishing) for the barrier layer 30 in the peripheral circuit region occurs.
  • the upper surface of the first portion STI 1 -A of the element isolation insulating film STI 1 is preferably, e.g., lower than a level corresponding to the thickness of the floating gate electrode FG (polysilicon layer 14 ) and equal to or higher than the upper surface of the tunnel insulating film 12 .
  • the upper surface of the first portion STI 2 -A of the element isolation insulating film STI 2 is preferably, e.g., higher than a level corresponding to about 1 ⁇ 2 the thickness of the polysilicon layer 14 and equal to or lower than the upper surface of the polysilicon layer 14 .
  • a depth Y 2 (to be referred to as a depth Y 2 of the element isolation insulating film STI 2 hereinafter) from the upper surface of the semiconductor substrate 11 to the bottom surface of the element isolation insulating film STI 2 in the peripheral circuit region is larger than a depth Y 1 (to be referred to as a depth Y 1 of the element isolation insulating film STI 1 hereinafter) from the upper surface of the semiconductor substrate 11 to the bottom surface of the element isolation insulating film STI 1 in memory cell region.
  • the depth Y 2 of the element isolation insulating film STI 2 is preferably formed larger than the depth of a source/drain diffusion layer S/D of the high-breakdown-voltage peripheral transistor Tr 2 .
  • the depth Y 1 of the element isolation insulating film STI 1 is preferably formed larger than the depth of the source/drain diffusion layer S/D of the cell transistor Tr 1 .
  • the depth of the source/drain diffusion layer S/D of the peripheral transistor Tr 2 is preferably formed larger than the depth Y 1 of the element isolation insulating film STI 1 and smaller than the depth Y 2 of the element isolation insulating film STI 2 .
  • the depth of the source/drain diffusion layer S/D of the cell transistor Tr 1 is preferably formed smaller than the depth Y 1 of the element isolation insulating film STI 1 .
  • the depth of the source/drain diffusion layer S/D of the cell transistor Tr 1 is preferably formed to be about 2 ⁇ 3 the depth Y 1 of the element isolation insulating film STI 1 .
  • the aspect ratio of the minimum space portion in the peripheral circuit region must be larger than the aspect ratio of the minimum space portion in the memory cell. For this reason, the ratio of the depth Y 1 of the element isolation insulating film STI 1 to the depth Y 2 of the element isolation insulating film STI 2 is preferably given by
  • a thickness Tm 2 of the mask layer 26 in the peripheral circuit region is larger than a thickness Tm 1 of the mask layer 26 in the memory cell region.
  • a thickness Ts 2 of the WSi film 25 in the peripheral circuit region equals a thickness Ts 1 of the WSi film 25 in the memory cell region.
  • a thickness Tg 2 of the gate wiring G (polysilicon layers 14 and 24 ) in the peripheral circuit region is smaller than a thickness Tg 1 of the gate wiring (floating gate electrode FG, ONO insulating film 21 , and control gate electrode CG) in the memory cell region.
  • a thickness Tg 4 of the gate wiring (polysilicon layer 24 ) on the first portion STI 2 -A of the element isolation insulating film STI 2 in the peripheral circuit region is smaller than a thickness Tg 3 of the gate wiring (control gate electrode CG) on the first portion STI 1 -A of the element isolation insulating film STI 1 in the memory cell region.
  • FIGS. 3 to 11 C are sectional views showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the first embodiment of the present invention.
  • FIGS. 9A, 9B , and 9 C and FIGS. 11A, 11B , and 11 C show details of the manufacturing process, including sectional views ( FIGS. 9B and 11B ) of the peripheral circuit region shown in FIGS. 9A and 11A taken along a vertical direction and sectional views ( FIGS. 9C and 11C ) of the memory cell region shown in FIGS. 9A and 11A taken along a vertical direction.
  • the method of manufacturing the semiconductor memory device according to the first embodiment will be described below.
  • the tunnel insulating film 12 (e.g., SiO 2 film) is formed on the semiconductor substrate 11 in the memory cell region.
  • the gate insulating film (e.g., SiO 2 film) 13 is formed on the semiconductor substrate 11 in the peripheral circuit region.
  • the gate insulating film 13 is preferably formed thicker than the tunnel insulating film 12 .
  • Either of the gate insulating film 13 and tunnel insulating film 12 can be formed first.
  • the first polysilicon layer 14 serving as a gate wiring material is deposited.
  • An SiN film 15 serving as a chemical mechanical polish (CMP) stopper material in STI gap filling is deposited on the first polysilicon layer 14 .
  • CMP chemical mechanical polish
  • a trench 16 of the element isolation insulating film STI 1 is formed in the memory cell region by reactive ion etching (RIE).
  • a trench 17 of the element isolation insulating film STI 2 is formed in the peripheral circuit region by RIE.
  • the trench 17 in the peripheral circuit region is formed deeper than the trench 16 in the memory cell region.
  • An oxide film 18 is buried in the trenches 16 and 17 .
  • the oxide film 18 is planarized by CMP.
  • the element isolation insulating films STI 1 and STI 2 are removed to a predetermined depth by wet etching by using the SiN film 15 as a mask. Then, the SiN film 15 is removed by hot phosphoric acid. The element isolation insulating films STI 1 and STI 2 may then be further removed to a predetermined depth by wet etching. As a result, the upper surfaces of the element isolation insulating films STI 1 and STI 2 become flush with, e.g., the upper surface of the first polysilicon layer 14 .
  • a resist 19 is applied to the upper surfaces of the first polysilicon layer 14 and element isolation insulating films STI 1 and STI 2 and patterned to open the memory cell region.
  • the element isolation insulating film STI 1 in the memory cell region is removed to a predetermined depth by dry etching. Consequently, the upper surface of the element isolation insulating film STI 1 becomes lower than the upper surface of the first polysilicon layer 14 so that a trench 20 is formed.
  • the upper surface of the element isolation insulating film STI 1 is preferably lower than about 1 ⁇ 2 the thickness of the first polysilicon layer 14 and equal to or higher than the upper surface of the tunnel insulating film 12 .
  • the ONO insulating film 21 is deposited on the first polysilicon layer 14 and element isolation insulating films STI 1 and STI 2 .
  • the second polysilicon layer 22 is deposited on the ONO insulating film 21 .
  • the ONO insulating film 21 is formed from an SiO 2 film/SiN film/SiO 2 film.
  • a resist 23 is applied to the upper surface of the second polysilicon layer 22 and patterned to open the peripheral circuit region.
  • the second polysilicon layer 22 and ONO insulating film 21 are etched by using the patterned resist 23 . With this process, the first polysilicon layer 14 and element isolation insulating film STI 2 in the peripheral circuit region are exposed. Then, the resist 23 is removed.
  • the third polysilicon layer 24 , WSi film 25 , and mask layer 26 are deposited sequentially.
  • the WSi film 25 need not always use W as a refractory metal.
  • W a refractory metal.
  • Co or Ti may be used.
  • the mask layer 26 e.g., an SiO 2 film or SiN film is used.
  • a resist 27 is applied to the upper surface of the mask layer 26 and processed into the gate wiring pattern.
  • the mask layer 26 , WSi film 25 , third polysilicon layer 24 , and second polysilicon layer 22 in the peripheral circuit region and memory cell region are etched by using the patterned resist 27 .
  • etching is performed under a condition to decrease the selectivity of polysilicon to the oxide film and increase the selectivity to SiN.
  • the first polysilicon layer 14 and element isolation insulating film STI 1 are etched so that the gate wirings are processed ( FIG. 9B ).
  • etching is stopped on the upper surface of the SiN film of the ONO insulating film 21 ( FIG. 9C ). Then, the resist 27 is removed.
  • a resist 28 is applied to the upper surface of the mask layer 26 and patterned to cover the peripheral circuit region.
  • the SiN film and SiO 2 film of the ONO insulating film 21 and the first polysilicon layer 14 in the memory cell region are etched by dry etching. This dry etching is done under a condition to lower the mask layer 26 to a predetermined height. With this process, the upper surface of the mask layer 26 in the memory cell region becomes flush with that in the peripheral circuit region. Then, the resist 28 is removed.
  • ion implantation is executed to form diffusion layers necessary for forming a transistor.
  • the spacer 29 is formed on the side surface of the gate wiring. Heavily doped diffusion layers are formed.
  • the barrier layer 30 is deposited.
  • the gate wiring is buried by the insulating film 31 .
  • the insulating film 31 is planarized by CMP.
  • the insulating film 32 is formed on the insulating film 31 and barrier layer 30 and planarized.
  • the contacts C 1 and C 2 extending through the insulating film 32 , barrier layer 30 , and mask layer 26 are formed.
  • the thickness Tm 2 of the mask layer 26 in the peripheral circuit region is larger than the thickness Tm 1 of the mask layer 26 in the memory cell region.
  • the thickness Tg 2 of the gate wiring G (polysilicon layers 14 and 24 ) in the peripheral circuit region is smaller than the thickness Tg 1 of the gate wiring (floating gate electrode FG, ONO insulating film 21 , and control gate electrode CG) in the memory cell region.
  • the height h 1 from the upper surface of the semiconductor substrate 11 to the upper surface of the mask layer 26 in the memory cell region can equal the height h 2 from the upper surface of the semiconductor substrate 11 to the upper surface of the mask layer 26 in the peripheral circuit region. For this reason, any erosion (dishing) for the barrier layer 30 in the peripheral circuit region can be prevented in CMP planarization of the buried insulating film 31 of the gate wiring.
  • the element isolation insulating film STI 2 in the peripheral circuit region has the large depth Y 2 and large height X 2 .
  • the distance between the gate wiring and the bottom surface of the element isolation insulating film STI 2 in the peripheral circuit region can be increased while avoiding any gap filling failure of the element isolation insulating film STI 2 so that the element breakdown voltage can be increased.
  • the element isolation insulating film STI 2 can be made narrow, the chip size can further be reduced.
  • the height h 1 in the memory cell region is made equal to the height h 2 in the peripheral circuit region by adjusting the difference (Tg 1 >Tg 2 ) between the thicknesses Tg 1 and Tg 2 of the gate wirings by the thicknesses Tm 1 and Tm 2 (Tm 1 ⁇ Tm 2 ) of the mask layers 26 .
  • FIG. 12 is a sectional view showing a semiconductor memory device having a memory cell region and peripheral circuit region according to the second embodiment of the present invention.
  • the semiconductor memory device according to the second embodiment will be described below. A description of the same structure as in the first embodiment will be omitted.
  • the second embodiment is different from the first embodiment in that the height h 1 from the upper surface of a semiconductor substrate 11 to the upper surface of a mask layer 26 in the memory cell region is made equal to the height h 2 from the upper surface of the semiconductor substrate 11 to the upper surface of the mask layer 26 in the peripheral circuit region by making thickness Tg 1 of a gate wiring (floating gate electrode FG, ONO insulating film 21 , and control gate electrode CG) in the memory cell region equal to the thickness Tg 2 of a gate wiring G (polysilicon layers 14 , 41 , and 24 ) in the peripheral circuit region.
  • a gate wiring floating gate electrode FG, ONO insulating film 21 , and control gate electrode CG
  • a thickness Tm 2 of the mask layer 26 in the peripheral circuit region equals a thickness Tm 1 of the mask layer 26 in the memory cell region.
  • a thickness Ts 2 of a WSi film 25 in the peripheral circuit region equals a thickness Ts 1 of the WSi film 25 in the memory cell region.
  • the gate wiring G in the peripheral circuit region includes the three polysilicon layers 14 , 41 , and 24 .
  • the two polysilicon layers 41 and 24 extend onto a first portion STI 2 -A of an element isolation insulating film STI 2 .
  • a thickness Tg 4 of the gate wiring (polysilicon layers 41 and 24 ) on the element isolation insulating film STI 2 in the peripheral circuit region is smaller than a thickness Tg 3 of the gate wiring (control gate electrode CG) on an element isolation insulating film STI 1 in the memory cell region.
  • FIGS. 13 to 17 are sectional views showing steps in manufacturing the semiconductor memory device having the memory cell region and peripheral circuit region according to the second embodiment of the present invention.
  • FIGS. 15A, 15B , and 15 C and FIGS. 16A, 16B , and 16 C show details of the manufacturing process, including sectional views ( FIGS. 15B and 16B ) of the peripheral circuit region shown in FIGS. 15A and 16A taken along a vertical direction and sectional views ( FIGS. 15C and 16C ) of the memory cell region shown in FIGS. 15A and 16A taken along a vertical direction.
  • the method of manufacturing the semiconductor memory device according to the second embodiment will be described below.
  • a second polysilicon layer 22 and ONO insulating film 21 in the peripheral circuit region are removed so that the first polysilicon layer 14 and element isolation insulating film STI 2 in the peripheral circuit region are exposed.
  • the third polysilicon layer 41 is deposited.
  • a resist 42 is applied to the upper surface of the third polysilicon layer 41 and patterned to open the memory cell region.
  • the third polysilicon layer 41 is etched and left only in the peripheral circuit region by using the patterned resist 42 . Then, the resist 24 is removed.
  • a native oxide film (not shown) is formed on the polysilicon layer 22 in the memory cell region.
  • the native oxide film is used as a stopper in etching the third polysilicon layer 41 .
  • the upper surface of the third polysilicon layer 41 is preferably flush with the upper surface of the second polysilicon layer 22 .
  • the third polysilicon layer 41 is deposited to the same thickness as that of the second polysilicon layer 22 .
  • a process of making the upper surfaces of the second and third polysilicon layers 22 and 41 equal may be added.
  • the fourth polysilicon layer 24 , WSi film 25 , and mask layer 26 are deposited sequentially on the second and third polysilicon layers 22 and 41 .
  • the WSi film 25 need not always use W as a refractory metal.
  • W a refractory metal.
  • Co or Ti may be used.
  • the mask layer 26 e.g., an SiO 2 film or SiN film is used.
  • a resist 27 is applied to the upper surface of the mask layer 26 and processed into the gate wiring pattern.
  • the mask layer 26 , WSi film 25 , fourth polysilicon layer 24 , third polysilicon layer 41 , and first polysilicon layer 14 in the peripheral circuit region are etched by using the patterned resist 27 . With this process, the gate wiring in the peripheral circuit region is processed. Then, the resist 27 is removed.
  • a resist 28 is applied to the upper surface of the mask layer 26 and processed into the gate wiring pattern.
  • the mask layer 26 , WSi film 25 , fourth polysilicon layer 24 , and second polysilicon layer 22 in the memory cell region are etched by using the patterned resist 28 . With this process, the gate wiring in the memory cell region is processed.
  • the resist 28 is removed.
  • the gate wirings can be formed while making the height of the mask layer 26 in the memory cell region equal to that in the peripheral circuit region.
  • ion implantation is executed to form diffusion layers necessary for forming a transistor.
  • a spacer 29 is formed on the side surface of the gate wiring. Heavily doped diffusion layers are formed.
  • a barrier layer 30 is deposited.
  • the gate wiring is buried by an insulating film 31 .
  • the insulating film 31 is planarized by CMP.
  • an insulating film 32 is formed on the insulating film 31 and barrier layer 30 and planarized. Contacts C 1 and C 2 extending through the insulating film 32 , barrier layer 30 , and mask layer 26 are formed.
  • the same effect as in the first embodiment can be obtained. Additionally, in the second embodiment, since the thicknesses Tm 1 and Tm 2 of the mask layers 26 in the memory cell region and peripheral circuit region are equal, the contacts C 1 and C 2 can more easily be formed than in the first embodiment.
  • the present invention is not limited to the above-described embodiments, and various changes and modifications can be made in practicing it.
  • the element isolation insulating films STI 1 and STI 2 need not always be self-aligned to the gate wirings and can be formed independently of the gate wirings.
  • the embodiments of the present invention need not always be applied when the gate wirings in the memory cell region and peripheral circuit region have a level difference and can also be applied even when the gate wirings have a level difference between various regions (e.g., between the memory cell regions, between the peripheral circuit regions, between the memory cell region and a logic circuit region, or between the peripheral circuit region and a logic circuit region).

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
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CN105990250A (zh) * 2014-12-29 2016-10-05 旺宏电子股份有限公司 半导体元件及其制造方法
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US11217597B2 (en) 2016-12-28 2022-01-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US10770469B2 (en) 2016-12-28 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
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US10741748B2 (en) 2018-06-25 2020-08-11 International Business Machines Corporation Back end of line metallization structures
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US11329115B2 (en) 2018-12-06 2022-05-10 Hefei Xinsheng Optoelectronics Technology Co., Ltd Display substrate, manufacturing method thereof, and display apparatus

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US20120025295A1 (en) 2012-02-02
JP2007129136A (ja) 2007-05-24

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