US20060205208A1 - Method for manufacturing a semiconductor device and method for etching the same - Google Patents

Method for manufacturing a semiconductor device and method for etching the same Download PDF

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Publication number
US20060205208A1
US20060205208A1 US11/306,205 US30620505A US2006205208A1 US 20060205208 A1 US20060205208 A1 US 20060205208A1 US 30620505 A US30620505 A US 30620505A US 2006205208 A1 US2006205208 A1 US 2006205208A1
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insulating film
hard mask
forming
etching
film
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Toyokazu Sakata
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Assigned to OKI ELECTRIC INDUSTRY CO., LTD. reassignment OKI ELECTRIC INDUSTRY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAKATA, TOYOKAZU
Publication of US20060205208A1 publication Critical patent/US20060205208A1/en
Priority to US12/110,479 priority Critical patent/US7713863B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1031—Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and a method for etching the same.
  • the operating frequency of microprocessors has entered a new “GHz band” era, and a system that mounts a plurality of circuits with different functions on one semiconductor chip, a so-called a system-on-chip (SOC), has entered the field.
  • This semiconductor device employs a multilayer wiring structure in which wirings are formed in a plurality of layers in the thickness direction of the semiconductor device in order to improve its degree of integration.
  • a multilayer wiring structure referred to as a dual damascene structure has been developed in these years.
  • a dual damascene structure is a further advancement of the damascene structure.
  • the damascene structure Cu is used as a wiring material because of its low-resistance and high electromigration resistance properties, and wiring is implanted with the chemical mechanical polishing (CMP) method.
  • CMP chemical mechanical polishing
  • the dual damascene method a wiring groove and a via hole are formed in the interlayer insulating film, and a conductive substance such as Cu is simultaneously implanted in the groove and the hole.
  • a conductive substance such as Cu is simultaneously implanted in the groove and the hole.
  • an upper layer wiring and a via plug are formed at one time. Therefore, the manufacturing cost of a semiconductor device is reduced in the dual damascene method, compared to a normal damascene method, a so-called single damascene method, in which a wiring groove and a via hole are separately formed.
  • the operation speed of the semiconductor device is highly influenced by not only the resistance value of the wiring itself, but also by the inter-wiring capacitance formed by an interlayer insulating film that is formed in a place between a lower layer wiring and an upper layer wiring. Therefore, the resistance of the wiring itself and the inter-wiring capacitance have to be reduced in order to realize an increase in the operation speed of a semiconductor device.
  • the dual damascene structure is classified roughly into two structures.
  • One is the so-called homogeneous structure.
  • This is a unitary structure in which the same type of low-k film is used as the insulating film for a wiring portion and for a via hole portion.
  • the other is the so-called hybrid structure.
  • This is a heterogeneous structure in which different types of low-k films are used as the insulating film for a wiring portion and for a via hole portion.
  • the depth of the wiring grooves is controlled.
  • the homogeneous structure has a disadvantage in that the value of the effective dielectric constant (keff) becomes high.
  • the hybrid structure it is easy to set the etch selectivity between substances of different low-k film to be higher. Therefore, it is not required to use an etching stopper layer with a high dielectric constant, such as silicon nitride film and silicon carbide film. Because of this, the hybrid structure has an advantage in that the effective dielectric constant (keff) of the whole wiring structure can be reduced, compared to the homogeneous structure.
  • Japanese Patent Publication JP-A-2002-124568 (especially pages 6-7 and FIG. 2) describes a method for manufacturing a semiconductor device with the hybrid type dual damascene structure.
  • the corners of a hard mask used for forming a wiring groove and a via hole tend to be eliminated and inclined from the perpendicular during the process of etching an interlayer insulating film. This state is called the facet of a hard mask. If a facet state is produced, the wiring size of the hard mask will be wider than the design value. In some cases, this causes a short circuit between a wiring and its adjacent wiring. Because of this, there is a possibility that reliability will be lowered and the yield will be negatively influenced.
  • a facet of a hard mask is prevented in the process of etching by forming at least a layer of a dummy film, which does not exist in the structure at the end of the process of forming a semiconductor device, on the hard mask.
  • a protective hard mask is further formed on a hard mask that is required to form a wiring groove and a via hole. Therefore, the number of processes to manufacturing a semiconductor device and the cost thereof are increased in the method.
  • an object of the present invention is to resolve the above-described problems, and to provide a method for manufacturing a semiconductor device in which a facet or a retrograde of a hard mask is prevented.
  • a method for manufacturing a semiconductor device with a dual damascene structure comprises the steps of preparing a semiconductor substrate, forming a first wiring layer over said semiconductor substrate, forming an inorganic insulating film over said first wiring layer, forming a via hole in said inorganic insulating film by forming a first resist pattern with an opening on said inorganic insulating film and by etching said inorganic insulating film with said first resist pattern as an etching mask, eliminating said first resist pattern, forming an organic insulating film so that said organic insulting film covers an upper side of said inorganic insulating film and an interior of said via hole, forming a hard mask on said organic insulating film, forming a hard mask pattern by forming a second resist pattern with an opening on said hard mask and by etching said hard mask with said second resist pattern as an etching mask, forming a wiring groove by etching said organic insulating film with said second resist pattern and said hard mask pattern as etching masks until
  • a via hole is formed by etching an inorganic insulating film, which becomes an inter-via layer insulating film. Therefore, a hard mask is not needed for patterning a via hole, and the number of times a hard mask is exposed to the etching gas can be reduced. Thus, a facet and a retrograde of a hard mask can be inhibited, and the wiring can be sized at a desired design value. Therefore, reliability and yield can be improved.
  • FIGS. 1A through 1H are views of diagrams showing a process of manufacturing a semiconductor device in accordance with a first embodiment of the present invention
  • FIGS. 2A through 2H are views of diagrams showing a process of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
  • FIGS. 3A through 3I are views of diagrams showing a process of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.
  • FIGS. 1A though 1 H are cross-section diagrams to explain a method for manufacturing a semiconductor device with a dual damascene structure in accordance with the first embodiment of the present invention.
  • a semiconductor substrate 100 is prepared.
  • the semiconductor substrate 100 has an electronic circuit (not shown in the diagram) formed by a semiconductor element such as a transistor on its main surface.
  • an insulating film 101 is formed on the semiconductor substrate 100 , and a lower layer wiring 102 , which is made of Cu, is formed on the insulating film 101 .
  • a diffusion barrier film 103 is formed on the lower layer wring 102 .
  • the diffusion barrier film 103 is made of a silicon nitride film and its thickness is set to be 500 ⁇ .
  • the diffusion barrier film 103 protects diffusion of Cu, which is the material of the lower layer wiring 102 , and functions as an etching stopper layer with respect to the lower layer wiring 102 .
  • the diffusion barrier film 103 is not necessarily required in the method of manufacturing a semiconductor device in accordance with the first embodiment of the present invention.
  • the diffusion barrier film 103 does not have to be formed, if the etch selectivity between the lower layer wiring 102 and an inorganic insulating film 104 (i.e., an object of an etching) can be set to be a larger value in the process of forming a via hole 106 by etching in the process shown below in FIG. 1C .
  • the inorganic insulating film 104 is formed.
  • the inorganic insulating film 104 becomes a inter-via layer insulating film in which a via hole 106 is formed in a process shown below in FIG. 1C .
  • the inorganic insulating film 104 is made of methyl-silsequioxane (MSQ) film and its thickness is set to be 3000 ⁇ .
  • a MSQ film can be formed with a method of spin-coating an MSQ substance and hardening it with a heat treatment in an inert gas atmosphere such as N 2 .
  • the inter-wiring capacitance can be reduced by using the MSQ film as the inorganic insulating film 104 .
  • a hydrogen-silsequioxane (HSQ) film can be used as a substance of the inorganic insulating film 104 , instead of the MSQ film.
  • a resist is applied on the inorganic insulating film 104 and a resist pattern 105 with an opening 105 a is formed by photolithoetching the resist.
  • the diameter of the opening 105 a is set to be 0.12 ⁇ m.
  • a via hole 106 is formed by etching the inorganic insulating film 104 with the resist pattern 105 as an etching mask.
  • the diameter of the via hole 106 is as large as that of the opening 105 a , and it is set to be 0.12 ⁇ m, for instance.
  • octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas.
  • the etching conditions are set as follows.
  • the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.
  • the diffusion barrier film 103 functions as an etching stopper layer toward the lower layer wiring 102 . Therefore, the lower layer wiring 102 is not etched.
  • the resist pattern 105 is eliminated with ashing.
  • an organic insulating film 107 is formed so that it covers the inorganic insulating film 104 and the inside of the via hole 106 .
  • the organic insulating film 107 becomes an inter-wiring layer insulating film in which a wiring groove is formed in a process shown below in FIG. 1F .
  • the organic insulating film 107 is made of silicon low-k polymer (SiLKTM of Dow Chemical Company), and its thickness is set to be 3000 ⁇ .
  • the silicon low-k polymer film can be formed by spin-coating the silicon low-k polymer substance and hardening it with a heat treatment in an inert gas atmosphere, such as N 2 , for instance.
  • a silicon dioxide film, which becomes a hard mask 108 is formed with the chemical vapor deposition (CVD) method.
  • CVD chemical vapor deposition
  • a resist is applied on the hard mask 108 , and a resist pattern 109 with an opening 109 a is formed with photolithoetching, as shown in FIG. 1E .
  • a hard mask 108 a is formed by etching a silicon dioxide film (the hard mask 108 ) with the resist pattern 109 as an etching mask.
  • etching the hard mask 108 octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas.
  • the etching conditions are set as follows.
  • the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.
  • a wiring groove 110 is formed by etching the organic insulating film 107 with the resist pattern 109 and the hard mask pattern 108 a as etching masks. Also, a via hole 106 is exposed by eliminating the organic insulating film 107 that is implanted in the via hole 106 .
  • ammonia NH 3
  • the etching conditions are set as follows. That is, the gas flow rate of NH 3 is set to be 100 sccm, and the RF Power is set to be 500 W, and the chamber pressure is set to be 60 mTorr.
  • the resist pattern 109 can also be eliminated simultaneously. This is because the resist pattern 109 and the organic insulating film 107 (the SiLKTM film) are made of an organic substance. Because of this, an ashing treatment to eliminate the resist pattern 109 is not required. Therefore, the number of processes required for the method for manufacturing a semiconductor device can be reduced. Also, the hard mask pattern 108 a is covered with the resist pattern 109 throughout the etching process. Because of this, it is possible to prevent the etching gas from causing the facet and the retrograde of the hard mask 108 a.
  • trifluoromethane (CHF 3 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas.
  • the etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr.
  • the hard mask pattern 108 a which is made of a silicon dioxide film, is simultaneously etched to the designated thickness.
  • a barrier layer 111 which blocks invasion of Cu, and a seed layer 112 are sequentially formed so that they can cover the inside surface of the via hole 106 and the wiring groove 110 .
  • the barrier layer 111 is a laminated layer that is made of tantalum (Ta) and tantalum nitride (TaN).
  • the layers of the barrier layer 111 are sequentially comprised of a Ta layer, a TaN layer, and a Ta layer.
  • the thickness ( ⁇ ) of the Ta layer, the TaN layer, and the Ta layer are set to be 50, 400, 50, respectively.
  • the seed layer 112 is made of Cu and its thickness is set to be 1000 ⁇ , for instance.
  • a method was described in which a dual damascene structure is formed between the first wiring layer (i.e., the lower layer wiring 102 ) on the semiconductor substrate (i.e., the semiconductor substrate 100 ) and the second wiring layer (i.e., the upper layer wiring 114 ).
  • the dual damascene structure of the embodiment between other layers, and a desired multi-layer wiring structure can be formed by conducting the process described in FIGS. 1A through 1H repeatedly.
  • the via hole 106 is formed by etching the inorganic insulating film 104 that becomes the inter-via layer insulating film, before the organic insulating film 107 that becomes an inter-wiring layer insulating film is formed. Therefore, a hard mask is not required to conduct a patterning of the via hole 106 , and the number of times the hard mask is exposed to the etching gas can be reduced. Because of this, the facet and the retrograde of the hard mask pattern 108 a are inhibited, the wiring can be sized at the desired design value, and reliability and yield can be improved. Also, as shown in FIG.
  • the hard mask pattern 108 a in the process of forming the wiring groove 110 and the via hole 106 by eliminating the organic insulating film 107 by etching, the hard mask pattern 108 a is covered with the resist pattern 109 throughout the etching process. Therefore, the facet and the retrograde of the hard mask pattern by the etching gas can be inhibited. Also, the resist pattern 109 can be used for patterning the hard mask pattern 108 a as shown in FIG. 1E , and also can be used as an etching protective film of the hard mask pattern 108 a at the same time as shown in FIG. 1F .
  • the resist pattern 109 can also be eliminated at the same time, because the resist pattern 109 is made of an organic substance, as with the organic insulating film 107 that is made of the SiLKTM film. Therefore, it is not required to conduct an ashing treatment to eliminate the resist pattern 109 , and the number of steps in the process of manufacturing a semiconductor device and manufacturing cost thereof can be reduced.
  • FIGS. 2A though 2 H are cross-section diagrams to explain a method for manufacturing a semiconductor device with a dual damascene structure in accordance with the second embodiment of the present invention.
  • a semiconductor substrate 200 is prepared.
  • the semiconductor substrate 200 has an electronic circuit (not shown in the diagram) formed by a semiconductor element such as a transistor on its main surface.
  • an insulating film 201 is formed on the semiconductor substrate 200 , and a lower layer wiring 202 , which is made of Cu, is formed on the insulating film 201 .
  • a diffusion barrier film 203 is formed on the lower layer wring 202 .
  • the diffusion barrier film 203 is made of a silicon nitride film and its thickness is set to be 500 ⁇ .
  • the diffusion barrier film 203 protects diffusion of Cu, which is the material of the lower layer wiring 202 , and functions as an etching stopper layer with respect to the lower layer wiring 202 .
  • the diffusion barrier film 203 is not necessarily required in the method of manufacturing a semiconductor device in accordance with the second embodiment of the present invention.
  • the diffusion barrier film 203 does not have to be formed, if the etch selectivity between the lower layer wiring 202 and an inorganic insulating film 204 (i.e., an object of an etching) can be set to be a larger value in the process of forming a via hole 206 by etching in the process shown below in FIG. 2C .
  • the inorganic insulating film 204 is formed.
  • the inorganic insulating film 204 becomes a inter-via layer insulating film in which a via hole 206 is formed in a process shown below in FIG. 2C .
  • the inorganic insulating film 204 is made of methyl-silsequioxane (MSQ) film and its thickness is set to be 3000 ⁇ .
  • a MSQ film can be formed with a method of spin-coating an MSQ substance and hardening it with a heat treatment in an inert gas atmosphere such as N 2 .
  • the inter-wiring capacitance can be reduced by using the MSQ film as the inorganic insulating film 204 .
  • a hydrogen-silsequioxane (HSQ) film can be used as a substance of the inorganic insulating film 204 , instead of using the MSQ film.
  • a resist is applied on the inorganic insulating film 204 and a resist pattern 205 with an opening 205 a is formed by photolithoetching the resist.
  • the diameter of the opening 205 a is set to be 0.12 ⁇ m.
  • a via hole 206 is formed by etching the inorganic insulating film 204 with the resist pattern 205 as an etching mask.
  • the diameter of the via hole 206 is as large as that of the opening 205 a , and it is set to be 0.12 ⁇ m, for instance.
  • octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas.
  • the etching conditions are set as follows.
  • the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.
  • the resist pattern 205 is eliminated with ashing.
  • an organic insulating film 207 is formed so that it covers the inorganic insulating film 204 and the inside of the via hole 206 .
  • the organic insulating film 207 becomes an inter-wiring layer insulating film in which a wiring groove 211 is formed in a process shown below in FIG. 2F .
  • the organic insulating film 207 is made of silicon low-k polymer (SiLKTM of Dow Chemical Company), and its thickness is set to be 3000 ⁇ .
  • the silicon low-k polymer film can be formed by spin-coating the silicon low-k polymer substance and hardening it with a heat treatment in an inert gas atmosphere, such as N 2 , for instance.
  • a silicon dioxide film that becomes a hard mask 208 and a silicon nitride film that becomes an upper layer hard mask 209 are sequentially formed with the chemical vapor deposition (CVD) method. For example, the thickness of the silicon dioxide film that becomes a lower layer hard mask 208 is set to be 500 ⁇ . Also, the thickness of the silicon nitride film that becomes an upper layer hard mask 209 is set to be the same value with that of the diffusion barrier film 203 . For example, the thickness is set to be 500 ⁇ .
  • a resist is applied on the upper layer hard mask 209 , and a resist pattern 210 with an opening 210 a is formed with photolithoetching, as shown in FIG. 2E .
  • an upper layer hard mask pattern 209 a and a lower layer hard mask pattern 208 a are formed by etching a silicon dioxide film (i.e., the upper layer hard mask 209 ) and a silicon dioxide film (i.e., the lower layer hard mask 208 ) sequentially with the resist pattern 210 as an etching mask.
  • a silicon dioxide film i.e., the upper layer hard mask 209
  • a silicon dioxide film i.e., the lower layer hard mask 208
  • the etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr. Also, in etching the lower layer hard mask 208 , octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas.
  • the etching conditions are set as follows.
  • the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.
  • a wiring groove 211 is formed by etching the organic insulating film 207 with the resist pattern 210 , the upper layer hard mask pattern 209 a , and the lower layer hard mask pattern 208 a as etching masks. Also, a via hole 206 is exposed by eliminating the organic insulating film 207 that is implanted in the via hole 206 .
  • ammonia NH 3
  • the etching condition is set as follows.
  • the gas flow rate of NH 3 is set to be 100 sccm, and the RF Power is set to be 500 W, and the chamber pressure is set to be 60 mTorr.
  • the resist pattern 210 can also be eliminated simultaneously. This is because the resist pattern 210 and the organic insulating film 207 (the SiLKTM film) are made of an organic substance. Because of this, an ashing treatment to eliminate the resist pattern 210 is not required, and the number of processes required for the method for manufacturing a semiconductor device can be reduced.
  • the upper layer hard mask pattern 209 a and the lower layer hard mask pattern 208 a are covered with the resist pattern 209 throughout the etching process. Because of this, it is possible to prevent the etching gas from causing the facet and the retrograde of the upper layer hard mask pattern 209 a that is made of a silicon nitride film.
  • the upper layer hard mask pattern 209 a made of a silicon nitride film is eliminated by etching, and a portion of the diffusion barrier film 203 made of a silicon nitride film, which is exposed at the bottom of the via hole 206 , is simultaneously eliminated in this etching.
  • etching the diffusion barrier film 203 trifluoromethane (CHF 3 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas.
  • the etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr.
  • a barrier layer 212 which blocks invasion of Cu, and a seed layer 213 are sequentially formed so that they can cover the inside surface of the via hole 206 and the wiring groove 211 .
  • the barrier layer 212 is a laminated layer that is made of tantalum (Ta) and tantalum nitride (TaN).
  • the layers of the barrier layer 212 are sequentially comprised of a Ta layer, a TaN layer, and a Ta layer.
  • the thickness ( ⁇ ) of the Ta layer, the TaN layer, and the Ta layer are set to be 50, 400, 50, respectively.
  • the seed layer 213 is made of Cu and its thickness is set to be 1000 ⁇ , for instance.
  • a method is described in which a dual damascene structure is formed between the first wiring layer (i.e., the lower layer wiring 202 ) on the semiconductor substrate (i.e., the semiconductor substrate 200 ) and the second wiring layer (i.e., the upper layer wiring 215 ).
  • the dual damascene structure of the embodiment between other layers, and a desired multi-layer wiring structure can be formed by conducting the process described in FIGS. 2A through 2H repeatedly.
  • the method for manufacturing a semiconductor device of the second embodiment of the present invention has the same effects of the first embodiment of the present invention. That is, as shown in FIG. 2C , the via hole 206 is formed by etching the inorganic insulating film 204 that becomes the inter-via layer insulating film, before the organic insulating film 207 that becomes an inter-wiring layer insulating film is formed. Therefore, a hard mask is not required to conduct a patterning of the via hole 206 , and the number of times the hard mask is exposed to the etching gas can be reduced.
  • the wiring can be sized at the desired design value, and reliability and yield can be improved. Also, as shown in FIG. 2F , in the process of forming the wiring groove 211 and the via hole 206 by eliminating the organic insulating film 207 with etching, the upper layer hard mask pattern 209 a and the lower layer hard mask pattern 208 a are covered with the resist pattern 210 throughout the etching process. Therefore, the facet and the retrograde of the hard mask pattern by the etching gas can be inhibited.
  • the resist pattern 210 can be used for patterning the upper layer hard mask pattern 209 a and the lower layer hard mask pattern 208 a as shown in FIG. 2E , and also can be used as an etching protective film of the upper layer hard mask pattern 209 a and the lower layer hard mask pattern 208 a at the same time as shown in FIG. 2F . Because of this, it is not required to form a dummy film (e.g., a third hard mask pattern) to protect the upper layer hard mask pattern 209 a and the lower layer hard mask pattern 208 a , and the number of steps in the process of manufacturing a semiconductor device and the cost thereof can be reduced. Also, as shown in FIG.
  • the resist pattern 210 in the process of forming the wiring groove 211 and the via hole 206 by eliminating the organic insulating film 207 with etching, the resist pattern 210 can also be eliminated at the same time, because the resist pattern 210 is made of an organic substance, as with the organic insulating film 207 that is made of the SiLKTM film. Therefore, it is not required to conduct an ashing treatment to eliminate the resist pattern 210 , and the number of steps in the process of manufacturing a semiconductor device and the manufacturing cost thereof can be reduced.
  • FIGS. 3A though 3 H are cross-section diagrams to explain a method for manufacturing a semiconductor device with a dual damascene structure in accordance with the third embodiment of the present invention.
  • a semiconductor substrate 300 is prepared.
  • the semiconductor substrate 300 has an electronic circuit (not shown in the diagram) formed by a semiconductor element such as a transistor on its main surface.
  • an insulating film 301 is formed on the semiconductor substrate 300 , and a lower layer wiring 302 , which is made of Cu, is formed on the insulating film 301 .
  • a diffusion barrier film 303 is formed on the lower layer wring 302 .
  • the diffusion barrier film 303 is made of a silicon nitride film and its thickness is set to be 500 ⁇ .
  • the diffusion barrier film 303 protects diffusion of Cu, which is the material of the lower layer wiring 302 , and functions as an etching stopper layer with respect to the lower layer wiring 302 .
  • the diffusion barrier film 303 is not necessarily required in the method of manufacturing a semiconductor device in accordance with the third embodiment of the present invention.
  • the diffusion barrier film 303 does not have to be formed, if the etch selectivity between the lower layer wiring 302 and an organic insulating film 304 (i.e., an object of an etching) can be set to be a larger value in the process of forming a via hole 306 by etching in the process shown below in FIG. 3C .
  • the organic insulating film 304 is formed.
  • the organic insulating film 304 becomes a inter-via layer insulating film in which a via hole 306 is formed in a process shown below in FIG. 3C .
  • the organic insulating film 304 is made of a SiLKTM film and its thickness is set to be 3000 ⁇ .
  • a SiLKTM film can be formed with a method of spin-coating a SiLKTM substance and hardening it with a heat treatment in an inert gas atmosphere such as N 2 .
  • a GX-3TM film can be used as the material of the organic insulating film 304 , instead of the SiLKTM film.
  • a resist is applied on the organic insulating film 304 and a resist pattern 305 with an opening 305 a is formed by photolithoetching the resist.
  • the diameter of the opening 305 a is set to be 0.12 ⁇ m.
  • a via hole 306 is formed by etching the organic insulating film 304 with the resist pattern 305 as an etching mask.
  • the diameter of the via hole 306 is as large as that of the opening 305 a , and it is set to be 0.12 ⁇ m, for instance.
  • ammonia NH 3
  • the etching conditions are set as follows. That is, the gas flow rate of NH 3 is set to be 100 sccm, and the RF Power is set to be 500 W, and the chamber pressure is set to be 60 mTorr.
  • the resist pattern 305 can also be eliminated, because the resist pattern 305 is made of an organic substance as with the SiLKTM film that comprises the organic insulating film 304 . Because of this, an ashing treatment is not required to eliminate the resist pattern 305 and the number of manufacturing processes of a semiconductor device can be reduced.
  • trifluoromethane (CHF 3 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas.
  • the etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr.
  • a surface modification layer 307 is formed by modifying the surface of the organic insulating film 304 that is made of the organic SiLKTM film with a plasma treatment.
  • the surface modification layer 307 has the effect of enhancing its adhesiveness with an inorganic insulating film 308 formed in a process shown below in FIG. 3E .
  • the inorganic insulating film 308 is formed so that it covers the organic insulating film 304 and the inside of the via hole 306 .
  • the inorganic insulating film 308 becomes an inter-wiring layer insulating film in which a wiring groove 312 is formed in a process shown below in FIG. 3H .
  • the inorganic insulating film 308 is made of a methyl-silsequioxane (MSQ) film and its thickness is set to be 3000 ⁇ .
  • a MSQ film can be formed with a method of spin-coating a MSQ substance and hardening it with a heat treatment in an inert gas atmosphere such as N 2 .
  • a silicon dioxide film that becomes a lower layer hard mask 309 and a silicon nitride film that becomes an upper layer hard mask 310 are sequentially formed. For example, the thickness of the silicon dioxide film that becomes the lower layer hard mask 309 is set to be 500 ⁇ . Also, the thickness of the silicon nitride film that becomes the upper layer hard mask 310 is set to be that of the diffusion barrier film 303 , for example, 500 ⁇ .
  • a resist is applied on the upper layer hard mask 310 , and a resist pattern 311 with an opening 311 a is formed with photolithoetching, as shown in FIG. 3F .
  • an upper layer hard mask pattern 310 a and a lower layer hard mask pattern 309 a are formed by etching a silicon nitride film (i.e., the upper layer hard mask 310 ) and a silicon dioxide film (i.e., the lower layer hard mask 309 ) with the resist pattern 311 as an etching mask.
  • a silicon nitride film i.e., the upper layer hard mask 310
  • a silicon dioxide film i.e., the lower layer hard mask 309
  • the etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr.
  • the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr.
  • octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas.
  • the etching conditions are set as follows.
  • the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.
  • the resist pattern 311 is eliminated with an ashing treatment.
  • an ashing treatment is conducted for the resist pattern 311 after the formation of the inorganic insulating film 308 made of the MSQ film, there is a possibility that the lower layer wiring 302 , which is made of Cu and exposed at the bottom of the via hole 306 , will be damaged. Therefore, damage of the lower layer wiring by this ashing treatment is prevented by eliminating the resist pattern 311 .
  • a wiring groove 312 is formed by etching the inorganic insulating film 308 with the upper layer hard mask pattern 310 a and the lower layer hard mask pattern 309 a as etching masks. Also, a via hole 306 is exposed by eliminating the inorganic insulating film 308 that is implanted in the via hole 306 .
  • octafluocyclobutane C 4 F 8
  • oxygen O 2
  • the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.
  • the upper layer hard mask pattern 310 a made of a silicon nitride film can also be eliminated simultaneously.
  • the value of the etch selectivity between the inorganic insulating film 308 made of the MSQ film and the organic insulating film 304 made of the SiLKTM film is more than 50. Therefore, only the inorganic insulating film 308 made of the MSQ film can be effectively eliminated.
  • a barrier layer 313 which blocks invasion of Cu, and a seed layer 314 are sequentially formed, so that they can cover the inside surface of the via hole 306 and the wiring groove 312 .
  • the barrier layer 313 is a laminated layer that is made of tantalum (Ta) and tantalum nitride (TaN).
  • the layers of the barrier layer 313 are sequentially comprised of a Ta layer, a TaN layer, and a Ta layer.
  • the thickness ( ⁇ ) of the Ta layer, the TaN layer, and the Ta layer are set to be 50, 400, 50, respectively.
  • the seed layer 314 is made of Cu and its thickness is set to be 1000 ⁇ , for instance.
  • a method is described in which a dual damascene structure is formed between the first wiring layer (i.e., the lower layer wiring 302 ) on the semiconductor substrate (i.e., the semiconductor substrate 300 ) and the second wiring layer (i.e., the upper layer wiring 316 ).
  • the dual damascene structures of the embodiment between other layers, and a desired multi-layer wiring structure can be formed by conducting the process described in FIGS. 3A through 3I repeatedly.
  • the via hole 306 is formed by etching the organic insulating film 304 that becomes an inter-via layer insulating film, before the inorganic insulating film 308 that becomes an inter-wiring layer insulating film is formed. Therefore, a hard mask is not required to conduct a patterning of the via hole 306 , and the number of times the hard mask is exposed to the etching gas can be reduced. Because of this, the facet and the retrograde of the upper layer hard mask pattern 310 a made of a silicon nitride film are inhibited, the wiring size can be formed at the desired design value, and reliability and yield can be improved.
  • the surface modification layer 307 is formed by modifying the surface of the organic insulating film 304 made of the organic SiLKTM film with a plasma treatment. Therefore, its adhesiveness with an inorganic insulating film 308 formed on the organic insulating film can be enhanced, and reliability and yield can be improved. Also, as shown in FIG. 3C , in the process of forming the via hole 306 by eliminating the organic insulating film 304 by etching, the resist pattern 305 can also be eliminated at the same time, because the resist pattern 305 is made of an organic substance, as with the organic insulating film 304 that is made of the SiLKTM film. Therefore, it is not required to conduct an ashing treatment to eliminate the resist pattern 305 , and the number of steps in the process of manufacturing a semiconductor device and the manufacturing cost thereof can be reduced.
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