US20050280102A1 - Field effect transistor and method for manufacturing the same - Google Patents

Field effect transistor and method for manufacturing the same Download PDF

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US20050280102A1
US20050280102A1 US11/089,371 US8937105A US2005280102A1 US 20050280102 A1 US20050280102 A1 US 20050280102A1 US 8937105 A US8937105 A US 8937105A US 2005280102 A1 US2005280102 A1 US 2005280102A1
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layer
forming
channel layer
gate electrode
source
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Inventor
Chang-Woo Oh
Dong-gun Park
Dong-won Kim
Dong-uk Choi
Kyoung-hwan Yeo
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, DONG-UK, KIM, DONG-WON, OH, CHANG-WOO, PARK, DONG-GUN, Yeo, Kyoung-hwan
Publication of US20050280102A1 publication Critical patent/US20050280102A1/en
Priority to US12/588,193 priority Critical patent/US8101475B2/en
Priority to US13/284,889 priority patent/US8415210B2/en
Abandoned legal-status Critical Current

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates, in general, to a field effect transistor (FET) and method for manufacturing the same.
  • FET field effect transistor
  • DIBL drain induced barrier lowering
  • junction resistance (RS, RD) is also reduced.
  • the junction resistance does not have a substantial influence on an ‘on current’ of the transistor.
  • the junction resistance has a substantial influence and a relatively large junction resistance may greatly reduce the transistor on current.
  • it may be desirable to improve the junction resistance characteristics of a transistor such as a MOS transistor.
  • junction resistance is a function of a spreading resistance occurring at a channel edge (edge of a junction region). That is, if the spreading resistance is reduced, the junction resistance can be reduced.
  • the spreading resistance is associated with a doping profile of a junction region. If the doping profile of the junction region can be reduced abruptly at the channel edge, referred to as ‘junction abruptness”, the spreading resistance may be reduced.
  • junction abruptness the doping profile of the junction region can be reduced abruptly at the channel edge.
  • the junction region is formed by an impurity ion implantation and annealing process.
  • the doping profile at the junction region thus has an undesirable slope of at least about 3 nm/decade at the side portion of the junction region.
  • This undesirable slope formed at sides of the junction region due to the ion implantation and the annealing process represents a substantial limitation in the efforts to reduce the spreading resistance, since desirable junction abruptness at the channel edge cannot be obtained.
  • An exemplary embodiment of the present invention is directed to field effect transistor (FET).
  • the FET may include a semiconductor substrate having an isolation film formed thereon to define an active region, a gate electrode formed on a given portion of the semiconductor substrate, and a channel layer formed on a portion of the gate electrode.
  • Source and drain regions maybe formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions are perpendicular to a surface of the semiconductor substrate.
  • a FET which may include a semiconductor substrate having an isolation film formed thereon to define an active region, a channel layer formed on a portion of the active region and having a width and a length, and a gate electrode formed on the channel layer so as to extend in the width direction of the channel layer.
  • the FET may include source and drain regions disposed on corresponding sides of the channel layer in a length direction of the channel layer so that boundaries between the channel layer and the source and drain regions are perpendicular to a surface of the semiconductor substrate.
  • the FET may include a pair of insulating spacers, one insulating spacer formed on each sidewall of the gate electrode.
  • Another exemplary embodiment of the present invention is directed to a method for manufacturing a field effect transistor, in which a junction layer may be formed on a semiconductor substrate and an isolation film may be formed on a given portion of the substrate. Source and drain regions with a space between the source and drain regions may be formed in the junction layer. A channel layer may be formed in the space and a gate electrode may be formed on the channel layer.
  • Another exemplary embodiment of the present invention is directed to a method for manufacturing a field effect transistor, in which a channel layer may be formed on a semiconductor substrate and a gate electrode formed on the channel layer.
  • a spacer may be formed on each corresponding sidewall of the gate electrode, and regions reserved for a source region and a drain region may be defined in the channel layer.
  • An impurity-containing epitaxial layer may be formed in the defined regions to form the source and drain regions.
  • FIGS. 1 through 7 are plan views of a transistor according to an exemplary embodiment of the present invention.
  • FIGS. 8 through 15 are sectional views of a transistor according to an exemplary embodiment of the present invention.
  • FIGS. 16 through 19 are sectional views illustrating a modification of a transistor according to an exemplary embodiment of the present invention.
  • FIGS. 20 through 22 are plan views of a transistor according to another exemplary embodiment of the present invention.
  • FIGS. 23 through 25 are sectional views of a transistor according to another exemplary embodiment of the present invention.
  • FIGS. 26 and 27 are sectional views illustrating a modification of a transistor according to another exemplary embodiment of the present invention.
  • FIGS. 28 through 30 are plan views of a transistor according to a another exemplary embodiment of the present invention.
  • FIGS. 31 through 33 are sectional views of a transistor according to another exemplary embodiment of the present invention.
  • FIGS. 34 and 35 are sectional views illustrating a modification of a transistor according to another exemplary embodiment of the present invention.
  • perpendicular may be understood as meaning perpendicular or substantially perpendicular; a boundary hereafter may be referred to hereafter as being perpendicular to a substrate surface, which means perpendicular or substantially perpendicular to the surface.
  • a channel layer or a junction region may be defined by anisotrophic etching.
  • junction regions formed on both sides of the channel region or a channel region between junction regions may be grown by an epitaxial method. Accordingly, boundaries between the channel layer and the junction regions may be formed so as to be perpendicular to a substrate surface. Thus, a doping profile of the junction region at this boundary may have a definite abruptness. Accordingly, spreading resistance and hence junction resistance can be reduced.
  • FIGS. 1 through 7 are plan views of a transistor according to an exemplary embodiment of the present invention
  • FIGS. 8 through 15 are sectional views of the transistor shown in FIGS. 1-7
  • FIGS. 8, 9A , 10 , 11 A, 12 , 13 , 14 and 15 A are sectional views taken along the lines x-x′ of FIGS. 1 through 7
  • FIGS. 9B, 11B , 13 B and 15 B are sectional views taken along the lines y-y′ of FIGS. 1 through 7 .
  • a junction layer 105 including impurities may be formed on a semiconductor substrate 100 .
  • the junction layer 105 can be formed by implanting impurities on an overall surface of the semiconductor substrate 100 , performing an annealing process thereon and activating the impurities.
  • the junction layer 105 may be a silicon layer including doped impurities that can be formed by a deposition process or by a Selective Epitaxial Growth (SEG) process.
  • SEG Selective Epitaxial Growth
  • epitaxy is a process by which a thin layer of a single-crystal material may be deposited on a single-crystal substrate. Epitaxial growth occurs in such a way that the crystallographic structure of the substrate is reproduced in the growing material; also crystalline defects of the substrate may be reproduced in the growing material.
  • Selective epitaxy is epitaxial growth on the substrate which is only partially a single-crystal material, For example, in the case of single crystal silicon (Si) partially covered with oxide, Si will grow epitaxially only (selectively) on the surface of a single-crystal Si.
  • a process of selective epitaxial growth to grow a layer is known as a SEG process.
  • the type of impurities implanted or doped in the junction layer 105 may be different than the impurities of the substrate 100 .
  • the junction layer 105 may have a concentration of impurities for a source and a drain and may be of a substantially shallow depth (thickness) suitable for a short channel transistor.
  • a mask pattern 110 for example a silicon nitride pattern, may be formed on the junction layer 105 so as to define an isolation film 115 .
  • a trench may then be formed by etching the exposed semiconductor substrate 100 to a desired, given depth using the mask pattern 110 as a mask.
  • An isolation film 115 is thus formed by filling the trench with an insulating material.
  • the isolation film 115 may be formed after the formation of the junction layer 105
  • the junction layer 105 can be formed after the isolation film 115 is first formed and then the mask pattern 110 is removed.
  • the mask pattern 110 may be removed by a known method. Then, a hard mask layer 120 may be deposited on the resulting structure.
  • the hard mask layer 120 may be a silicon nitride layer and may be provided for anti-reflection during a photolithography process to be applied to hard mask layer 120 .
  • a photoresist pattern 125 may be formed on the hard mask layer 120 so as to expose a region for a gate electrode.
  • a dotted line of FIG. 2 represents a boundary between the isolation film and the active region.
  • the semiconductor substrate 100 and the isolation film 115 which are disposed below the junction layer 105 , may be exposed by performing an anisotrophic etching on the hard mask layer 120 and the junction layer 105 in a shape of the photoresist pattern 125 that is formed on the hard mask layer 120 .
  • a groove or gap 130 may be formed within the junction layer 105 by the anisotrophic etching, so as to define source region 105 a and drain region 105 b . Since the source and drain regions 105 a and 105 b are defined by the anisotrophic etching, their sidewalls may be formed so as to be perpendicular to the substrate 100 surface.
  • the photoresist pattern 120 may be removed by a known method.
  • a channel layer 135 may then be formed by epitaxially growing the exposed semiconductor substrate 100 in the gap 130 in accordance with a SEG process, for example.
  • the channel layer 135 may be a non-doped epitaxial layer (intrinsic epitaxial layer) and/or a doped epitaxial layer (extrinsic epitaxial layer) including no doped impurity or a doped impurity. Additionally, in case where impurities are doped into the channel layer 135 , the doped impurities may be n type or p type.
  • a chemical mechanical polishing (CMP) or an etch back process may be performed on the surface of the semiconductor substrate 100 so as to planarize the surface of the semiconductor substrate 100 .
  • CMP chemical mechanical polishing
  • the source region 105 a and drain region 105 b may also be formed of an epitaxial layer having a doped impurity, for example.
  • a gate oxide layer 140 may be formed by oxidizing the surface of the exposed channel layer 135 .
  • the gate oxide layer 140 may be formed as part of a process of forming the gate electrode of the FET.
  • a conductive layer 145 for the gate electrode may be deposited so as to sufficiently fill a gap between the hard mask layers 120 .
  • the conductive layer 145 for the gate electrode may be a doped poly silicon layer, for example.
  • the conductive layer 145 may be chemical mechanical polished to expose the surface of the hard mask layer 120 . Then, the hard mask layer 120 is removed to form the gate electrode 150 . At this time, sidewalls of the gate electrode 150 may substantially align with a boundary between the channel layer 135 and the source region 105 a , and/or a boundary between the channel layer 135 and drain region 105 b , as shown in FIG. 14 , for example.
  • a thermal annealing process can be additionally performed so as to adjust an overlap length between the gate electrode 150 and the source and drain regions 105 a and 105 b.
  • corresponding spacers 155 may be formed on corresponding sidewalls of the gate electrode 150 by a known method.
  • a transition metal layer may then be deposited on the resulting structure and a thermal process performed thereon to form a silicide layer 160 on the gate electrode 150 , source region 105 a and drain region 105 b.
  • a portion of the isolation film 115 formed at one side the source and drain regions 105 a and 105 b may be removed to a given depth using a suitable etching process.
  • this removed portion of the isolation film 115 may be shown by a notch in the isolation film 115 .
  • the isolation film 115 may be removed by an amount equal to the depth of the source and drain regions 105 a and 105 b . In this manner, surface area of the silicide layer 160 may be expanded.
  • a given portion of the isolation film 115 disposed in a width direction of the channel layer 135 may be removed to a given depth. By doing so, an upper surface of the channel layer 135 and the side surfaces in the width direction of the channel layer 135 may be exposed.
  • a gate oxide layer 140 may be formed on the surface of the exposed channel layer 135 , and the gate electrode 150 and the silicide layer 160 may be formed.
  • the gate electrode 150 may be formed so as to enclose 3-dimensions of the channel layer 135 , such that a FinFET (so called because the free-standing sidewall spacers of the formed FET resemble fins) using the 3-dimensions as a channel can be formed. Forming a FET such as a Fin FET as described above may reduce adverse effects of the short channel effect, and may be applied to a next generation semiconductor device, for example.
  • a storage node may be formed after the gate oxide layer 140 is formed.
  • the storage node may consist of a floating gate electrode 170 formed of polysilicon layer and an inter gate insulating layer 175 formed of oxide-nitride-oxide (ONO), for example.
  • the storage node may be a charge storage unit, such as a single ONO layer or nano-crystal layer. If the storage node is embodied as a single ONO layer, the gate oxide layer 140 can be omitted. In this manner, a flash memory can be manufactured by forming the storage node on a lower portion of the gate electrode 145 . Also as shown in FIG. 18 , a flash FinFET can be manufactured by forming the floating gate electrode 170 and the inter gate insulating layer 175 once a portion of the isolation film 115 has been removed to a given depth, for example.
  • a high mobility material 136 may be formed on the surface of the channel layer 135 .
  • the high mobility material 136 may be a material layer or stacked structure selected from the group consisting of C, Si, Ge and combinations thereof.
  • the high mobility material 136 may be formed by a SEG process, for example.
  • Transistor mobility may be improved by forming the high mobility material 136 on the surface of the channel layer 135 .
  • the junction layer 105 may be formed of a doped silicon layer on the semiconductor substrate 100 .
  • the source and drain regions 105 a and 105 b may be formed by performing anisotrophic etching on the junction layer 105 .
  • a SEG process may be performed to fill a gap or groove 130 between the source and drain regions 105 a and 105 b , thereby forming the channel layer 135 .
  • Boundaries between the channel layer 135 and the source and drain regions 105 a and 105 b may be perpendicular to the surface of the semiconductor substrate 100 , so that the doping profile of the source and drain regions 105 a and 105 b has a desired, definite abruptness. In this manner, junction abruptness may be improved.
  • FIGS. 20 through 22 are plan views of a transistor according to another exemplary embodiment of the present invention
  • FIGS. 23 through 25 are sectional views of the transistor of FIGS. 20-22
  • FIGS. 23A, 24 and 25 A are sectional views taken along the lines x-x′ of FIGS. 20 through 22
  • FIGS. 23B and 25B are sectional views taken along the lines y-y′ of FIGS. 20 through 22 .
  • a channel layer 205 may be formed on a semiconductor substrate 200 .
  • the channel layer 205 may be formed across part of or across the entire surface of the semiconductor substrate 200 , and may be a doped silicon layer.
  • An impurity concentration of the channel layer 205 may be that of an implanted threshold voltage control ion of a FET (i.e., ion-implantation process).
  • the channel layer 205 can be formed by implanting impurities into the semiconductor substrate 200 and activating the impurities. Also, the channel layer 205 can be formed by a deposition or a SEG process, for example.
  • the impurities may be introduced into the channel layer 205 together with the deposition (growth) at the same time, or may be introduced into the channel layer 205 by an ion-implantation process after the channel layer 205 is formed.
  • the channel layer 205 may have a thickness suitable for the junction depth of the single channel transistor.
  • a mask pattern (such as shown in FIG. 1 ) for an isolation film may be formed on the channel layer 205 to expose a region for an isolation film.
  • the mask pattern for the isolation film may be a silicon nitride layer, for example.
  • a trench may be then formed by etching a given portion of the channel layer 205 and the semiconductor substrate 200 in a shape of the mask pattern.
  • An isolation film 210 may thus be formed by filling the trench with an insulating material.
  • the isolation film 210 may also be formed before the formation of the channel layer 205 .
  • a gate oxide layer 215 , gate electrode material 220 and a hard mask layer 225 may be sequentially stacked on the isolation film 210 and the channel layer 205 .
  • the gate oxide layer 215 can be formed by a thermal oxidation process.
  • the gate electrode material 220 may be a doped polysilicon layer and the hard mask layer 225 may be a silicon nitride layer.
  • a photoresist pattern 230 may be formed on the hard mask layer 225 so as to define a gate electrode 222 .
  • the hard mask layer 225 and gate electrode material 220 may be etched using the photoresist pattern 230 as a mask, thereby defining the gate electrode 222 .
  • Spacers 235 may then be formed on sidewalls of the gate electrode 222 .
  • the spacers 235 may be formed by performing a blanket etching on given thickness.
  • the spacers 235 may be provided for insulation between the gate electrode 222 and source and drain regions (not shown), to be formed later.
  • Gaps or exposed regions 240 a and 240 b may be formed by performing an anisotrophic etching on the exposed gate oxide layer 215 and the channel layer 205 using the gate electrode 222 and the spacers 235 as a mask. Since the channel layer 205 is patterned by anisotrophic etching, its sidewalls are perpendicular to the surface of the semiconductor substrate 200 .
  • a source region 245 a and a drain region 245 b may be formed by performing a SEG process on the semiconductor substrate 200 corresponding to the exposed regions 240 a and 240 b .
  • the source and drain regions 245 a and 245 b may be grown in a state that impurities are doped. Then, in some cases, the source and drain regions 245 a and 245 b may be planarized to expose the surface of the hard mask layer 225 .
  • the doping profile of the source and drain regions 245 a and 245 b has a desired, definite abruptness.
  • the junction abruptness can be improved.
  • the source and drain regions 245 a and 245 b ‘rise up’ the upper portion of the substrate 200 surface. Therefore, although thickness from a bottom of the gate electrode 222 to a bottom of the source and drain regions 245 a and 245 b is shallow, a total thickness of the source and drain regions 245 a and 245 b is actually increased, so that the junction resistance is improved.
  • a storage node may be formed before the formation of the gate electrode 222 .
  • the storage node may include a floating gate electrode 250 and an inter gate insulating layer 255 , or a single ONO layer or a nano-crystal layer, for example.
  • the floating gate electrode 250 may be a doped polysilicon layer and the inter gate insulating layer 255 may be an ONO layer. If the storage node is a single ONO layer, the gate oxide layer 215 can be omitted. In this manner, a flash memory can be manufactured by forming the storage node on a lower portion of the gate electrode 222 .
  • a high mobility material 212 may be formed on the surface of the channel layer 205 before the formation of the gate oxide layer 215 .
  • the high mobility material 212 may be a material layer or stacked structure selected from the group consisting of C, Si, Ge and combinations thereof.
  • the high mobility material 212 may be formed by a SEG process, for example. Transistor mobility may be improved by forming the high mobility material 212 on the surface of the channel layer 205 .
  • the gate electrode 222 and the channel layer 205 may be defined by the anisotrophic etching, and the source and drain regions 245 a and 245 b may be formed or built up on both sides of the channel layer 205 by the SEG process. Therefore, the boundaries between the channel layer 205 and the source and drain regions 245 a and 245 b may be perpendicular to the surface of the semiconductor substrate 200 , so that the doping profile of the source and drain regions 245 a and 245 b has a desired, definite abruptness. In this manner, junction abruptness may thus be improved.
  • FIGS. 28 through 30 are plan views of a transistor according to another exemplary embodiment of the present invention
  • FIGS. 31 through 33 are sectional views of the transistor in FIGS. 28-30
  • FIGS. 31A, 32 and 33 are sectional views taken along the lines x-x′ of FIGS. 28 through 30
  • FIG. 31B is a sectional view taken along the line y-y′ of FIG. 28 .
  • a channel layer 305 may be formed on a semiconductor substrate 300 by the same method as the above-described embodiments.
  • the channel layer 305 may have a junction region thickness suitable for a short channel transistor, for example.
  • An oxide layer 315 and a silicon nitride layer 320 may be sequentially stacked on the channel layer 305 , and given portions of the silicon nitride layer 320 and the oxide layer 315 patterned to expose a region for a device isolation, thereby forming a mask pattern for an isolation film.
  • a trench may be formed by etching given portions of the channel layer 305 and the semiconductor substrate 300 in a shape of the mask pattern.
  • An isolation film 310 may be formed by filling the trench with an insulating material. At this time, the isolation film 310 can be formed before the formation of the channel layer 305 .
  • a photoresist pattern for opening the region reserved for gate electrode may be formed on the resulting structure.
  • the exposed silicon nitride layer 320 may be etched in a shape of the photoresist pattern (not shown).
  • the exposed isolation film 310 may be etched.
  • reference numeral 310 a represents the recessed isolation film 310 .
  • the surface of the isolation film 310 a may be positioned at a bottom of the channel layer 305 so as to expose the sidewalls of the channel layer 305 . Then, the photoresist pattern is removed.
  • a conductive layer for a gate electrode may be deposited on the resulting structure. Then, a damascene gate electrode 325 may be formed by performing a CMP on the conductive layer so as to expose the surface of the silicon nitride layer 320 . In order to protect the gate electrode 325 , a hard mask layer 330 may be formed by oxidizing the surface of the gate electrode 325 .
  • the oxide layer 315 as well as the silicon nitride layer 320 may be removed and then a new gate oxide layer formed before the deposition of the conductive layer for the gate electrode 325 .
  • the gate electrode 325 may be formed by etching the conductive layer for the gate electrode 325 using the hard mask layer 330 as a mask.
  • Spacers 335 are formed on both sidewalls of the gate electrode 325 .
  • the spacers 335 act as an insulating layer and can be formed by performing a blanket etching on an insulating layer to a given thickness or oxidizing the sidewalls of the gate electrode 325 to a given oxide thickness.
  • the spacers 335 are provided for insulation between the gate electrode 325 and source and drain region (not shown), which will be formed later.
  • An anisotrophic etching may be performed on the exposed gate oxide layer 315 and the channel layer 305 using the gate electrode 325 and the spacers 335 as a mask. In this manner, regions or gaps 340 a and 340 b , reserved for the source and drain regions, may be formed. Since the channel layer 305 is patterned by the anisotrophic etching, its sidewalls may be perpendicular to the surface of the semiconductor substrate 300 .
  • source and drain regions 345 a and 345 b may be formed via a SEG process, for example, on the semiconductor substrate 300 disposed at the exposed gaps or 340 a and 340 b reserved for the source and drain regions.
  • the source and drain regions 345 a and 345 b may be formed on side portions disposed in a length direction of the channel layer 305 .
  • the source and drain regions 345 a and 345 b may be grown in a state that impurities are doped. Then, in some cases, the source and drain regions 345 a and 345 b may be planarized to expose the surface of the hard mask layer 320 .
  • the junction abruptness may be additionally improved. Similar to as shown in FIGS. 15A and 15B , a silicide layer may also be formed on the source and drain regions 345 a and 345 b.
  • a storage node can be formed before the gate oxide layer 315 is formed.
  • the storage node may be a stacked structure of a floating gate electrode 350 and an inter gate insulating layer 355 , or an ONO layer or a nano-crystal layer.
  • the gate oxide layer 315 can be omitted. In this manner, a flash FinFET can be manufactured by forming the storage node on a lower portion of the gate electrode 325 .
  • a high mobility material 312 may be further formed on the surface of the channel layer 305 before the formation of the gate oxide layer 315 .
  • the high mobility material 312 may be a material layer or stacked structure selected from the group consisting of C, Si, Ge and combinations thereof.
  • the high mobility material 312 may be formed by a SEG process, for example. In this manner, a FinFET with an improved mobility can be improved by forming the high mobility material 312 on the surface of the channel layer 305 .
  • the boundaries between the channel layer 305 and the source and drain regions 345 a and 345 b may be perpendicular to the surface of the semiconductor substrate 300 , so that the doping profile of the source and drain regions 345 a and 345 b has a desired, definite abruptness.
  • the transistor according to the exemplary embodiments of the present invention may have a FinFET structure in which the gate electrode 325 and the floating gate electrode 350 is overlapped with the upper and side surfaces of the channel layer 305 to reduce the occurrence of the short channel effect.
  • the source and drain regions may be defined by the anisotrophic etching, and the channel region formed between the source and drain regions (and/or the source and drain regions formed on both sides of the channel layer) may be formed by a SEG process. Therefore, boundaries between the channel layer and the source and drain regions may be perpendicular (i.e., perpendicular or substantially perpendicular) to the semiconductor substrate, so that the doping profile of the source and drain regions has a desired abruptness. Thus, the junction abruptness can be improved and the spreading resistance occurring at the boundaries of the junction region can be reduced.
  • junction depth of the source and source regions is reduced, any increase in the junction resistance may be avoided. Therefore, the single channel effect can be suppressed so that the on current of the transistor can be improved.

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