US20050166006A1 - System including a host connected serially in a chain to one or more memory modules that include a cache - Google Patents

System including a host connected serially in a chain to one or more memory modules that include a cache Download PDF

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US20050166006A1
US20050166006A1 US10/842,298 US84229804A US2005166006A1 US 20050166006 A1 US20050166006 A1 US 20050166006A1 US 84229804 A US84229804 A US 84229804A US 2005166006 A1 US2005166006 A1 US 2005166006A1
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memory
cache
recited
controller
address
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US10/842,298
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Gerald Talbot
Frederick Weber
Shwetal Patel
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Assigned to ADVANCED MICRO DEVICES, INC. reassignment ADVANCED MICRO DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WEBER, FREDERICK D., PATEL, SHWETAL A., TALBOT, GERALD R.
Publication of US20050166006A1 publication Critical patent/US20050166006A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache

Definitions

  • This invention relates to computer system memory and, more particularly, to memory module configurations and the memory subsystem topology.
  • a motherboard or system board may include a number of memory expansion sockets.
  • One or more small circuit boards, referred to as memory modules, may be inserted into the sockets as needed to increase the memory capacity of the computer system.
  • Each of the memory modules typically includes multiple memory devices that provide a given amount of memory capacity.
  • the memory devices are usually implemented using some type of dynamic random access memory (DRAM).
  • DRAM types include synchronous DRAM (SDRAM) as well as the various types of double data rate SDRAM (DDR SDRAM).
  • the memory modules are connected to a memory/DRAM controller via a memory bus that includes address, control (including clock signals), and data signals.
  • the address, control and data signals may be multiplexed and thus share the same sets of wires.
  • the address, control and data signals may use separate wires.
  • each of the address and control signals are routed to each expansion socket such that the memory modules, when inserted, are connected in parallel to the memory/DRAM controller.
  • parallel bus arrangements For example, depending on the topology of the interconnect, the maximum memory bus speed may be limited due to transmission line effects such as signal reflections.
  • the memory/DRAM controller may reside on the same integrated circuit (IC) chip as the system processor, while in other systems the memory/DRAM controller may reside in one IC (e.g., a Northbridge) of a chipset.
  • a host is coupled to a serially connected chain of memory modules.
  • At least one memory module includes a cache for storing data stored in a system memory.
  • system memory may include a respective plurality of memory chips mounted on each memory module.
  • each memory module may include a memory control hub including a controller configured to determine whether data associated with a received memory request is stored within the cache.
  • a given cache may include a storage for storing cache tags corresponding to the data stored within the given cache.
  • the controller is configured to access the cache in response to determining that the data associated with the received memory request is stored within the cache.
  • the host includes a memory controller configured to generate memory requests to the memory modules.
  • the memory controller may include a storage for storing cache tags corresponding to data stored within each cache.
  • the memory control hub includes a controller that may be configured to access the memory chips in response to receiving a memory command having a memory address that matches a memory address associated with the memory chips.
  • the controller may be configured to access the cache in response to receiving a memory command having a memory address that matches a memory address associated with the cache.
  • FIG. 1 is a block diagram of one embodiment of a system including a serially connected chain of system memory modules.
  • FIG. 2 is a block diagram of one embodiment of a memory module of FIG. 1 including one cache implementation.
  • FIG. 3 is a block diagram of another embodiment of a memory module of FIG. 1 including another cache implementation.
  • FIG. 4 is a block diagram of one embodiment of a system including a serially connected chain of cache memory modules.
  • FIG. 5 is a diagram of one embodiment of a memory read packet.
  • FIG. 6 is a diagram of one embodiment of a cache memory read packet.
  • FIG. 7 is a block diagram of one embodiment of a computer system.
  • System 50 includes a host 100 coupled to a system memory 125 via a memory link 1 I A.
  • System 50 may be configured to operate as part of a computing device such as a computer system or server system, for example.
  • System memory 125 includes a memory module 150 A coupled to a memory module 150 B via a memory link 110 B.
  • Memory module 150 B is shown coupled to a memory link 110 C, which may be coupled to an additional memory module (not shown) as desired to form a serially connected chain of memory modules that is coupled to host 100 .
  • a memory link 110 C which may be coupled to an additional memory module (not shown) as desired to form a serially connected chain of memory modules that is coupled to host 100 .
  • components including a reference number followed by a reference letter may be referred to generally by the reference number alone. For example, when referring generally to all memory modules, reference may be made to memory module 150 .
  • memory module 150 A includes a memory control hub 160 A, which is coupled to a plurality of memory devices that are designated memory chip 171 A through 171 N, where N may be any number, as desired.
  • memory control hub 160 A may be coupled to the memory chips via any type of memory interconnect.
  • the memory interconnect may be a typical address, control and data bus configuration.
  • memory module 150 B includes a memory control hub 160 B, which is coupled to a plurality of memory devices that are designated memory chip 181 A through 181 N, where N may be any number, as desired.
  • memory control hub 160 B may be coupled to the memory chips via any type of memory interconnect as described above. It is noted that each of memory chips 171 A through 171 N and 181 A through 181 N may be any type of memory device such as a memory device in the DRAM family of memory devices, for example.
  • memory links 110 A- 110 C form a memory interconnect.
  • each of memory links 110 A- 110 C forms a point-to-point memory interconnect that is implemented as two sets of unidirectional lines.
  • One set of unidirectional lines is referred to as a downlink and is configured to convey transactions away from host 100 in a downstream direction.
  • the other set of unidirectional lines is referred to as an uplink and is configured to convey transactions toward host 100 in an upstream direction.
  • each set of unidirectional lines may be implemented using a plurality of differential signal pairs.
  • each memory link 110 includes an 18-bit downlink and a 16-bit uplink, where each bit is a differential signal pair.
  • the memory interconnect formed by memory links 110 may be configured to convey packets.
  • each of memory links 110 may form a point-to-point memory interconnect that is implemented as one set of bi-directional lines. As such, transactions may flow both upstream and downstream on the set of bi-directional wires.
  • the bi-directional lines may be implemented using a plurality of differential signal pairs. It is noted that in other embodiments, other signaling schemes may be used, such as multi-level signaling, for example.
  • all transactions from host 100 flow downstream through all memory modules 150 on the downlink and all response transactions flow upstream from the responding memory module 150 through each upstream memory module 150 on the uplink. More particularly, in one embodiment, host 100 may request to retrieve or store data within system memory 125 .
  • memory controller 105 initiates a corresponding transaction such as a memory read transaction or a memory write transaction, for example.
  • Memory controller 105 transmits the transaction to system memory 125 via memory link 110 A.
  • the transaction is received by memory control hub 160 A of memory module 150 A.
  • memory control hub 160 A In response to receiving the transaction, memory control hub 160 A is configured to transmit the received transaction to memory module 150 B via memory link 110 B without decoding or modifying the transaction. This is referred to as forwarding the transaction downstream.
  • each transaction received on a downlink by a given memory control hub 160 of a given memory module 150 is forwarded to the next memory module 150 in the chain that is coupled to the downlink without decoding the transaction.
  • decoding of the transaction may occur in parallel with the forwarding of the transaction. In other embodiments, the decoding of the transaction may occur after the transaction has been forwarded.
  • memory controller 105 initiates a read request transaction
  • the memory module 150 having the memory location corresponding to the address in the request will respond with the requested data.
  • the response will be transmitted on the memory module's uplink toward host 100 .
  • the intervening memory module will forward the response transaction on its uplink to either host 100 or the next memory module in the chain in an upstream direction.
  • the responding memory module may inject the response into a sequence of transactions that are being forwarded upstream on the uplink.
  • memory controller 105 may be configured to make requests to system memory 125 without knowledge of which of memory modules 150 A and 150 B a particular address is associated. For example, each of memory modules 150 may be assigned a range of memory addresses during a system configuration sequence.
  • Each memory control hub 160 may include logic (not shown in FIG. 1 ) that may decode the address of an incoming request. Thus, a memory control hub 160 of a given memory module 150 may initiate a memory read cycle or memory write cycle to the memory chips on the given memory module 150 in response to decoding a memory request having an address that is in the address range assigned to the given memory module 150 .
  • each memory control hub 160 may include a DRAM controller (not shown in FIG. 1 ) for initiating memory cycles to the memory chips to which it is connected.
  • memory controller 105 may initiate a subsequent memory access request prior to receiving a response to a previous memory access request. In such an embodiment, memory controller 105 may keep track of outstanding requests and may thus process the responses in a different order than they were sent.
  • memory control hubs 160 A and 160 B include a cache memory designated 175 A and 175 B, respectively.
  • Cache memories 175 A-B may each serve as a cache memory for data stored elsewhere in the computing system.
  • cache memories 175 A-B may each serve as a cache memory for data stored within the respective memory chips of each memory module.
  • cache memories 175 A-B may each serve as a cache memory for data stored within other memory modules in the chain that may be further from the host and thus have longer latencies.
  • cache memories 175 A-B may serve as a cache memory for data stored in a remote processor node. In the embodiment described in conjunction with the description of FIG.
  • cache 175 includes storage for cache tags. However, in the embodiment described in conjunction with the description of FIG. 2 , cache 175 does not include storage for cache tags. In such an embodiment, memory controller 105 may include cache tag storage (not shown). It is noted that although cache memories 175 are shown as part of memory control hub 160 (e.g., on the same device), it is contemplated that in other embodiments, cache memories 175 may be implemented on different devices than memory control hub 160 .
  • the memory interconnect includes one or more high-speed point-to-point memory links such as memory links 110 A- 110 C each including an uplink such as uplink 111 A and a downlink such as downlink 112 A, for example.
  • downlinks may be 18-bit links while uplinks may be 16-bit links.
  • an 18-bit downlink may include 16 control, address and data (CAD) signals, a busy signal and a Control (CTL) signal.
  • a given uplink may include 16 control, address and data (CAD) signals.
  • an uplink such as uplink 211 A may also include a CTL signal.
  • each memory module 150 may be provided to each memory module 150 .
  • a reset signal, a power OK signal and a reference clock may be provided to each memory module 150 from host 100 .
  • other signals may be provided between each memory module. For example, as described above, a next memory module present signal may be provided between memory modules.
  • configuration and control transactions may be used to configure memory control hub 160 .
  • configuration and control transactions may be used to access configuration registers, assign a memory address range to a memory module or to assign a hub address to a memory control hub.
  • Memory transactions may be used to access the memory locations within the memory chips (e.g., 171 A- 171 N . . . 181 A- 181 N).
  • certain memory transactions may be used to directly access cache 175 .
  • hub addressing there are two types of addressing supported: hub addressing and memory addressing.
  • hub addressing eight hub bits identify the specific memory control hub being accessed.
  • a hub address of FFh may be indicative of a broadcast to all memory control hubs.
  • memory addressing each hub decodes the upper portion of the address bits to determine which hub should accept the request and the lower portion to determine the memory location to be accessed.
  • the additional memory addressing type may be used to specifically access a cache memory located on a given memory module.
  • the last four entries of table 1, below, illustrate some exemplary cache access command codes.
  • each of the memory links is configured to convey the transactions using one or more packets.
  • the packets include control and configuration packets and memory access packets, each of which may include a data payload depending on the type of command the packet carries.
  • the sets of wires that make up memory links 110 may be used to convey control, address and data.
  • the packets may be generally characterized by the following: Each packet includes a number of bit positions which convey a single bit of information. Each packet is divided into several bit times and during a given bit time, all of the bit positions of the packet are sampled. As such, the control information and data share the same wires of a given link (e.g., CAD wires). As will be described in greater detail below, in one embodiment, packets are multiples of bit pairs and the first bit-time of every packet is sampled at an even bit-time. Packets begin with a control header that may be either one or two bit-pairs in length. In one embodiment, the first five bits of the control header is the command code. Table 1 below illustrates the various types of packets and their associated command codes.
  • packets are transmitted with an error detecting code (EDC).
  • EDC error detecting code
  • the EDC is a 32-bit cyclic redundancy code (CRC), although other embodiments may employ other EDC's as desired.
  • addresses are sent most significant bit-time first to speed decode within memory control hub 160 while data is sent least significant byte first. It is noted however, that other embodiments are contemplated in which the addresses may be sent least significant bit-time first and data my be sent most significant byte first.
  • Packets may carry a payload of byte enables and/or data. Packets with no payload are referred to as header-only packets.
  • the size of the data short reads may be up to one half of a programmed cache line size.
  • the size of the data for long reads and block writes may be up to the programmed cache line size.
  • the size of the data for byte writes may be a maximum of 64 bytes regardless of the cache line size setting.
  • the CTL signal may be used to convey information about each packet. As illustrated in Table 2 below, some exemplary CTL encodings are shown. TABLE 2 CTL encodings for downstream use Even Odd Content of CAD 0 0 Data or Byte Enable Payload 1 1 Control Header 0 1 CRC for a Packet with Payload 1 0 CRC for a Header-Only Packet
  • Different values of CTL for the header and payload portions of a packet may provide enough information to allow header-only packets to be inserted within the payload of another packet. This may be useful for reducing the latency of read commands by allowing them to issue while a write packet is still being sent on the link.
  • Table 3 illustrates an exemplary packet including a payload in tabular format. The packet in table 3 also shows that a header-only packet is inserted in the payload during bit times 4 - 7 . It is noted however, that other packet encodings are possible and contemplated. For example, in other embodiments, a portion of the CRC bits may be transmitted during each bit time.
  • Memory module 150 includes a memory control hub 160 coupled to memory chips 261 A through 261 N via z memory bus 265 .
  • Memory control hub 160 includes a control unit 240 coupled to a DRAM controller 250 .
  • DRAM controller 250 is coupled to memory chips 261 A- 261 N and to a cache memory 175 .
  • Control unit 240 includes an uplink control 241 and a downlink control 242 .
  • memory bus 265 may be any type of memory interconnect.
  • memory control hub 160 is coupled to a memory link 110 A in an upstream direction and a memory link 110 B in a downstream direction. It is further noted that the frequency of operation of memory bus 265 may be independent of the frequency of operation of memory links 110 .
  • cache memory 175 is shown as part of memory control hub 160 , in other embodiments, cache memory 175 may be separate from memory control hub 160 , but may still be included on the same memory module.
  • uplink control unit 241 may be configured to receive and forward packets received from another memory module downstream. The receiving and forwarding of the upstream packets creates an upstream transaction sequence. In addition, uplink control unit 241 may be configured to inject packets that originate within memory module 150 into the transaction stream.
  • downlink control unit 242 may be configured to receive packets that originate at the host and if a memory module is connected downstream, to forward those packets to the downstream memory module. In addition, downlink control unit 242 may be configured to copy and decode the packets. In one embodiment, if the packets include an address that is within the range of addresses assigned to memory module 150 and the packet is a memory access request, downlink control unit 242 may pass the command associated with the packet to DRAM controller 250 . However, if the packet is not a memory request, but is instead a configuration packet, downlink control unit 242 may pass the configuration command associated with the packet to the core logic of control unit 240 (not shown) for processing. It is noted that in one embodiment, if the packet does not include an address that is within the range of addresses assigned to memory module 150 , memory control hub 160 may drop or discard the packet if memory module 150 is the last memory module in the chain.
  • memory control hub 160 is configured to receive a module present signal (not shown), which when activated by a downstream memory module, indicates to an upstream memory module that there is a downstream memory module present. In such an embodiment, if memory control hub 160 receives a transaction and no downstream memory module is determined to be present, memory control hub 160 may drop the transaction. In addition, if no downstream memory module is determined to be present, a memory control hub 160 may power down the downstream transmit and receive circuits; thereby reducing power consumption and possibly radiated emissions.
  • a module present signal not shown
  • cache memory 175 of FIG. 2 is configured to cache frequently accessed data, whether that data is stored within memory chips 261 A-N or some other place within the system.
  • DRAM controller 250 is configured to initiate memory cycles to either to cache memory 175 or to memory chips 261 A- 261 N in response to memory commands received by memory control hub 160 .
  • DRAM controller 250 may respond with a cache miss which may initiate a request to another memory in response to memory commands received by memory control hub 160 .
  • cache memory 175 may be implemented using memory devices that are typically used for cache memory in a processor.
  • the memory devices may be in the static RAM (SRAM) or fast SRAM (FSRAM) family of devices.
  • cache memory 175 is configured to store cache data while memory controller 105 includes storage for cache tags corresponding to the cache data stored within cache memory 175 .
  • memory controller 105 is configured to perform a tag lookup within a tag storage (not shown) prior to initiating a memory access request to system memory 125 . In doing so, memory controller 105 determines whether the data is located in cache memory 175 or not. In either case, the access times associated with the request may be planned for and the responses scheduled accordingly.
  • each memory module may be associated with a particular address space.
  • DRAM controller 250 is configured to generate read or write cycles to either cache 175 or memory chips 261 A-N.
  • the address space associated with memory chips 261 A-N may be different than the address space associated with cache memory 175 .
  • the address space associated with memory chips 261 A-N of all memory modules may be 00000000h through FFFFFFFFh, while the address space associated with of all cache memories may be 00000h through FFFFFh.
  • a memory access command code is used and to access the address space associated with cache memory 175 , a cache access command code is used. Exemplary memory and cache read packets are described below in conjunction with the descriptions of FIG. 5 and FIG. 6 , respectively. Since the memory controller 105 has determined whether the data resides in cache memory 175 or in DRAM chips 261 A-N, memory controller 105 sends the access request using the correct addressing type.
  • the memory space associated with memory module 150 may include addresses associated with memory chips 261 A-N as well as addresses associated with cache memory 175 .
  • the address space associated with memory module 150 includes addresses in the range 00000000h through 3FFFFFFF
  • the address space associated with cache memory 175 may be allocated to addresses 00000000h through 000FFFFFh and the remaining addresses may be allocated to memory chips 261 A-N.
  • DRAM controller 250 may access memory chips 261 A-N.
  • the type of packet may be a standard memory read or write packet including the requested address.
  • DRAM controller 250 may include memory control logic (not shown) that may provide support for ensuring that cached data is written back to memory chips 261 A-N.
  • DRAM controller 250 may provide a write back buffer and/or an eviction/victim buffer and support logic (not shown) for cache memory 175 .
  • DRAM controller 250 may implement an eviction algorithm such as a least recently used (LRU) algorithm, for example, for evicting data from cache memory 175 .
  • LRU least recently used
  • memory controller 105 may provide explicit write back instructions to DRAM controller 250 .
  • cache memory 175 of FIG. 2 may also be configured to cache frequently accessed data stored within a remote processor node (not shown in FIG. 2 ) or the memory chips of another downstream memory module.
  • memory controller 105 may explicitly write data to cache memory 175 rather than writing to cache memory 175 as an artifact of writing to memory chips 261 A-N.
  • FIG. 3 a block diagram of another embodiment of a memory module such as the memory module of FIG. 1 is shown. Components that correspond to those shown in FIG. 1 are numbered identically for clarity and simplicity.
  • Memory module 150 of FIG. 3 includes a memory control hub 160 coupled to memory chips 261 A through 261 N via a memory bus 265 .
  • Memory control hub 160 includes a control unit 240 coupled to a DRAM controller 250 .
  • DRAM controller 250 is coupled to memory chips 261 A- 261 N and to a cache memory 175 .
  • the operation of the memory interconnect and aspects of the operation of the DRAM controller 250 of memory module 150 of FIG. 3 are similar to the operation of memory module 150 Of FIG. 2 .
  • memory control hub 160 of FIG. 3 includes a cache memory 175 that includes a cache tag storage 175 A and a cache data storage 175 B. Differences in functionality are described further below.
  • cache data storage 175 B is configured to cache frequently accessed data stored within memory chips 261 A-N.
  • cache tag storage 175 A is configured to store address tags corresponding to the data stored within cache data storage 175 B. Accordingly, data written to and read from memory chips 261 A-N may be stored within cache data storage 175 B.
  • DRAM controller 250 is configured to initiate memory cycles to either memory chips 261 A- 261 N or to cache data storage 175 B in response to memory commands received by memory control hub 160 .
  • cache memory 175 A and 175 B may be implemented using memory devices that are typically used for cache memory in a processor.
  • the memory devices may be in the static RAM (SRAM) or fast SRAM (FSRAM) family of devices.
  • SRAM static RAM
  • FSRAM fast SRAM
  • cache memory 175 A-B is shown as part of memory control hub 160 (e.g., on the same device), it is contemplated that in other embodiments, cache memory 175 A-B may be implemented as a separate device (e.g., on a different IC).
  • memory controller 105 is configured to initiate a memory access request to system memory 125 .
  • each memory module may be associated with a particular address space.
  • DRAM controller 250 is configured to determine whether the requested data is stored within cache data storage 175 B. In the case of a read request, if the data is stored within cache data storage 175 B (cache hit), DRAM controller 250 is configured to generate read cycles to cache data storage 175 B. If, on the other hand, if the data is not stored within cache data storage 175 B (cache miss), DRAM controller 250 is configured to generate read cycles to memory chips 261 A-N.
  • memory controller 105 may not have any a priori knowledge of whether a given read request will hit in the cache or not. Since read response latencies for cache hits and misses is typically different, the latency of a given read request is unknown to memory controller 105 . To handle the unknown read response latency, memory controller 105 may include logic (not shown) that handles out-of-order read responses by tracking outstanding read responses.
  • write data e.g., data that may be posted to cache data storage 175 B
  • this functionality may be implemented in memory controller 105 while in other embodiments this functionality may be implemented in DRAM controller 250 .
  • DRAM controller 250 is configured to determine whether the requested data is stored within cache data storage 175 B. In one embodiment, if the data is not stored within cache data storage 175 B (cache miss), DRAM controller 250 may allocate a location within cache data storage 175 B for the write data and possibly evict data already present. As described above, DRAM controller may include logic (not shown), such as write back buffers or eviction/victim buffers to support operation of cache data storage 175 A and tag storage 175 B.
  • DRAM controller 250 may write the received data into cache data storage 175 B.
  • the evicted data and the newly written data may be written back to memory chips 261 A-N as determined by DRAM controller 250 . If the write data is stored within cache data storage 175 B (cache hit) and has not been flushed to memory chips 261 A-N, DRAM controller 250 may simply overwrite the data within cache data storage 175 B.
  • DRAM controller 250 may write the data back to memory chips 261 A-N. DRAM controller 250 may then write the received data into the locations within cache data storage 250 . Alternatively, DRAM controller 250 may move the dirty data already in cache data storage 175 B into a write back buffer to be written back to memory chips 261 A-N at some later point in time.
  • a memory access command code is used to access the address space associated with memory chips 261 A-N .
  • An exemplary memory read packet is described below in conjunction with the description of FIG. 5 .
  • System 400 includes a host processor 410 coupled to a cache memory module 450 A and a cache memory module 450 B via a memory link 110 A and a memory link 110 B, respectively.
  • Host processor 410 is also coupled to a system memory 425 via a memory interconnect 430 .
  • Cache memory module 450 B is shown coupled to a memory link 110 C, which may be coupled to an additional cache memory module (not shown) as desired to form a serially connected chain of cache memory modules that is coupled to processor host 410 .
  • cache memory module 450 may be connected in this manner. It is further noted that components including a reference number followed by a reference letter may be referred to generally by the reference number alone. For example, when referring generally to all cache memory modules, reference may be made to cache memory module 450 .
  • memory links 110 A-B and cache memory modules 450 A-B provide any level of external cache capability to processor 410 .
  • cache memory modules 45 GA-B may be an external L3 or L4 cache and may provide a means of providing a very large external cache memory.
  • Each cache memory module includes a cache memory control hub 460 which includes a cache memory 475 .
  • Processor 410 may include cache control logic (not shown) configured to generate cache transactions and to maintain cache coherency.
  • the external cache memory provided by cache memory modules 450 A-B may be used to cache frequently used data. That data may be stored within system memory 425 or any other storage.
  • system memory 425 may be representative of any type of system memory such as the system memory including the memory modules described above in conjunction with the descriptions of FIG. 1-3 , for example.
  • additional memory modules may be connected downstream from memory module 450 B.
  • the additional memory modules may be representative of the memory modules illustrated in FIG. 1 through FIG. 3 and may include memory chips.
  • the additional memory modules may not include cache memories.
  • Cache memory transactions that are conveyed upon memory links 110 A-C may be representative of the transactions described above in conjunction with the description of FIG. 1 , above.
  • FIG. 5 and FIG. 6 illustrate exemplary memory access packets that may be conveyed on memory links 110 A through 110 C of FIG. 1 .
  • FIG. 5 a diagram of one embodiment of a memory read packet is shown.
  • memory read packet 525 is 16 bits wide and includes six bit times or three bit-pairs.
  • the five-bit command code e.g., 10h or 11h
  • bit positions 0 - 4 are reserved.
  • An eight-bit tag is conveyed in bit positions 8 - 15 .
  • bit time one the length of the data that should be returned conveyed in bit positions 0 - 5 .
  • a value of 00h indicates no data
  • a value of 01h indicates two bit-pairs of data
  • a value of 02h indicates four bit-pairs of data
  • a zero length read results in an acknowledge packet (Ack) being returned to the requester.
  • Ack acknowledge packet
  • a read of a half cache line or less may result in a short RdResp and a read of more than a half cache line may result in either a single long RdResp or two short RdResp.
  • the cache line size may be programmed by software into the configuration registers of host 100 and each memory control hub 160 . Bit positions 6 - 7 are reserved. Address bits 39 - 32 of the requested location in DRAM are conveyed in bit positions 8 - 15 .
  • bit time two the address bits 31 - 16 of the requested location in DRAM are conveyed in bit positions 0 - 15 and during bit time 3 , the address bits 3 - 15 of the requested location in DRAM are conveyed in bit positions 3 - 15 .
  • the packet priority is conveyed in bit positions 0 - 1 .
  • the priority may be indicative of the priority of the packet relative to other requests. For example, one priority may be to delay all requests with lower priority even if they are already in progress and to execute this request ahead of them.
  • Bit position 2 is reserved.
  • bits 0 - 15 and 16 - 31 , respectively, of a CRC are conveyed in bit positions 0 - 15 .
  • cache read packet 525 is 16 bits wide and includes 4 bit times or two bit-pairs.
  • the five-bit command code e.g., 15h or 16h
  • bit positions 0 - 4 are reserved.
  • An eight-bit tag is conveyed in bit positions 8 - 15 .
  • bit time one the length of the data that should be returned is conveyed in bit positions 0 - 5 .
  • a value of 00h indicates no data
  • a value of 01h indicates two bit-pairs of data
  • a value of 02h indicates four bit-pairs of data
  • a zero length read results in an acknowledge packet (Ack) being returned to the requestor.
  • Ack acknowledge packet
  • a read of a half cache line or less may result in a short RdResp and a read of more than a half cache line may result in either a single long RdResp or two short RdResp.
  • the cache line size may be programmed by software into the configuration registers of host 100 and each memory control hub 160 . Address bits 25 - 16 of the requested location in cache are conveyed in bit positions 6 - 15 .
  • bit time two the address bits 15 - 0 of the requested location in cache 175 are conveyed in bit positions 7 - 16 .
  • bit times three and four bits 0 - 15 and 16 - 31 , respectively, of a CRC are conveyed in bit positions 0 - 15 .
  • FIG. 7 is a block diagram of one embodiment of a computer system.
  • Computer system 700 includes processor nodes 612 A- 612 D each interconnected by coherent packet interface links 615 A-D. Each link of coherent packet interface 615 may form a high-speed point-to-point link.
  • Processor nodes 612 A-D may each include one or more processors.
  • Computer system 700 also includes an I/O node 620 which is coupled to processor node 612 A via a non-coherent packet interface 650 A. I/O node 620 may be connected to another I/O node (not shown) in a chain topology for example, by non-coherent packet interface 650 B.
  • Processor nodes 612 A is illustrated as a host node and may include a host bridge for communicating with I/O node 620 via NC packet interface 650 A. Processor nodes 612 B-D may also include host bridges for communication with other I/O nodes (not shown).
  • the non-coherent packet interface links formed by NC packet interface 650 A-B may also be referred to as point-to-point links.
  • I/O node 620 is connected to a pair of peripheral buses 625 A-B.
  • FIG. 7 further illustrates respective system memories (e.g., 617 A and 617 B) coupled to processor nodes 612 A and 612 B.
  • processor node 612 A and 612 B are each illustrative of a host as shown in FIG. 1 , and each system memory 617 may be implemented in the configuration described in conjunction with the descriptions of FIG. 2 and FIG. 3 above.
  • the interconnects between each of processor nodes 612 A and 612 B and their respective system memories 617 may be reflective of the memory interconnect including memory link 110 C described above in FIG. 1 through FIG. 6 . It is noted that in other embodiments, other numbers of processor nodes may be used.
  • each of processor nodes 612 C and 612 D may be similarly connected to a respective system memory such as system memory 617 , for example.
  • a cache memory of a memory control hub located within system memory 617 A may cache data stored within either of system memories 617 A or 617 B, for example.
  • each link of coherent packet interface 615 is implemented as sets of unidirectional lines (e.g. lines 615 A are used to transmit packets from processing node 612 A to processing node 612 B and lines 615 B are used to transmit packets from processing node 612 B to processing node 612 C). Other sets of lines 615 C-D are used to transmit packets between other processing nodes as illustrated in FIG. 7 .
  • the coherent packet interface 615 may be operated in a cache coherent fashion for communication between processing nodes (“the coherent link”).
  • non-coherent packet interface 650 may be operated in a non-coherent fashion for communication between I/O nodes and between I/O nodes and a host bridge such as the host bridge of processor node 612 A (“the non-coherent link”).
  • the interconnection of two or more nodes via coherent links may be referred to as a “coherent fabric”.
  • the interconnection of two or more nodes via non-coherent links may be referred to as a “non-coherent fabric”. It is noted that a packet to be transmitted from one processing node to another may pass through one or more intermediate nodes.
  • a packet transmitted by processing node 612 A to processing node 612 C may pass through either processing node 612 B or processing node 612 D as shown in FIG. 7 .
  • Any suitable routing algorithm may be used.
  • Other embodiments of computer system 700 may include more or fewer processing nodes than the embodiment shown in FIG. 6 .
  • Peripheral buses 625 A and 625 B are illustrative of a common peripheral bus such as a peripheral component interconnect (PCI) bus. It is understood, however, that other types of buses may be used.
  • PCI peripheral component interconnect
  • system memory configuration described above may be used in conjunction with a computer system employing a processor chipset that includes a Northbridge.
  • a memory controller within the Northbridge may serve as the host.

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GB2416056A (en) 2006-01-11
US20050071542A1 (en) 2005-03-31
CN1788260A (zh) 2006-06-14
US20040230718A1 (en) 2004-11-18
KR101095025B1 (ko) 2011-12-20
CN100444141C (zh) 2008-12-17
KR20060009345A (ko) 2006-01-31
JP4836794B2 (ja) 2011-12-14
US7421525B2 (en) 2008-09-02
US7016213B2 (en) 2006-03-21
TW200508875A (en) 2005-03-01
DE112004000821B4 (de) 2016-12-01
WO2004102403A3 (fr) 2005-08-25
GB0521694D0 (en) 2005-11-30
WO2004102403A2 (fr) 2004-11-25
JP2006528394A (ja) 2006-12-14
DE112004000821T5 (de) 2006-05-11
GB2416056B (en) 2006-08-23
TWI351613B (en) 2011-11-01

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