JP4836794B2 - シリアルメモリインターコネクトを介して複数のメモリモジュールに接続されたホストを含むシステム - Google Patents
シリアルメモリインターコネクトを介して複数のメモリモジュールに接続されたホストを含むシステム Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
- G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache
Description
図1および図2をまとめて参照すると、メモリインターコネクトは、メモリリンク110A〜110Cなどの1つ以上の高速ポイント・ツゥー・ポイントメモリリンクを含み、メモリリンク110A〜110Cの各々は、例えば、アップリンク211Aなどのアップリンクおよびダウンリンク212Aなどのダウンリンクを含む。上述したように、1つの実施形態において、ダウンリンクは18ビットリンクであってもよく、アップリンクは16ビットリンクであってもよい。このようにして、18ビットダウンリンクが、16制御アドレスデータ(CAD:control,address and data)信号、ビジー信号、および制御(CTL:Control)信号を含んでもよい。所与のアップリンクが、16制御アドレスデータ(CAD)信号を含んでもよい。しかしながら、別の実施形態において、アップリンク211AなどのアップリンクがCTL信号を含んでもよいことが考えられる。
表1パケットタイプおよびコマンドコード
|コード|ヘッダ|コマンド |記述 |方向 |正常応答 |アドレ|
| |長(ビ| | | | |スタイ|
| |ットタ| | | | |プ |
| |イム)| | | | | |
|00h|− |NOP |動作なし/|双方向|− |− |
| | | |アイドル状| | | |
| | | |態 | | | |
|04h|2 |AddrSet |アドレスセ|ダウン|Addr |ハブ |
| | | |ット | |Ack | |
|05h|2 |AddrAck |アドレス認|アップ|− |− |
| | | |識 | | | |
|06h|2 |Ack |認識 |アップ|− |− |
|07h|2 |Nak |認識せず/|アップ|− |− |
| | | |エラー | | | |
|08h|2 |SRdResp |短いリード|アップ|− |− |
| | | |応答 | | | |
|09h|2 |LRdResp |長いリード|アップ|− |− |
| | | |応答 | | | |
|0Ah|2 |ConfigRd |コンフィギ|ダウン|RdResp |ハブ |
| | | |ュレーショ| | | |
| | | |ンリード | | | |
|0Ch|2 |ConfigWr |コンフィギ|ダウン|Ack |ハブ |
| | | |ュレーショ| | | |
| | | |ンライト | | | |
|0Eh|2 |DIMMCtl |DIMM制|ダウン|Ack |ハブ |
| | | |御 | | | |
|10h|4 |SMemRd |短いメモリ|ダウン|RdResp/Ack|メモリ|
| | | |リード | | | |
|11h|4 |LMemRd |長いメモリ|ダウン|RdResp |メモリ|
| | | |リード | | | |
|12h|4 |BlkMemWr |ブロックメ|ダウン|Ack |メモリ|
| | | |モリライト| | | |
|13h|4 |SbytMemWr|短いバイト|ダウン|Ack |メモリ|
| | | |メモリライ| | | |
| | | |ト | | | |
|14h|4 |LbytMemWr|長いバイト|ダウン|Ack |メモリ|
| | | |メモリライ| | | |
| | | |ト | | | |
表2 ダウンストリーム使用のCTL符号化
│偶数 │奇数 │CADの内容 │
│0 │0 │データまたはバイトイネーブ│
│ │ │ルペイロード │
│1 │1 │制御ヘッダ │
│0 │1 │ペイロードありのパケットの│
│ │ │CRC │
│1 │0 │ヘッドオンリーパケットのC│
│ │ │RC │
表3 ペイロードありのパケットと、ペイロード内に挿入されたヘッダオンリーパケット
│ビットタイム│CTL │CAD │
│0 │1 │ヘッダ1ビット[15:0] │
│1 │1 │ヘッダ1ビット[31:16]│
│2 │0 │データビット[15:0] │
│3 │0 │データビット[31:16] │
│4 │1 │ヘッダ2ビット[15:0] │
│5 │1 │ヘッダ2ビット[31:16]│
│6 │1 │CRC2ビット[15:0] │
│7 │0 │CRC2ビット[31:16]│
│8 │0 │データビット[47:32] │
│9 │0 │データビット[64:48] │
│10 │0 │CRC1ビット[15:0] │
│11 │1 │CRC1ビット[31:16]│
Claims (8)
- ホスト(100)と、
複数のメモリリンク(110A、B、C)と、
前記複数のメモリリンク(110A、B、C)を介して前記ホストにチェーン状にシリアル結合された複数のメモリモジュール(150A、150B)とを含むシステム(50)であって、
前記複数のメモリリンク(110A、B、C)の各々は、前記ホスト(100)の方へトランザクションを伝達するための一方向アップリンク(211)と、前記一方向アップリンク(211)とは別の、前記ホスト(100)で生じたトランザクションを伝達するための一方向ダウンリンク(212)とを含み、前記一方向アップリンクおよび前記一方向ダウンリンクの各々が、制御およびコンフィギュレーションパケットと、メモリアクセスパケットとを含むパケットを用いてトランザクションを伝達するように構成された複数の信号を含む、別々の一方向リンクであり、パケットの少なくとも一部分が、制御アドレスデータ情報を含み、前記制御アドレスデータ情報が、所与の前記一方向アップリンク又は前記一方向ダウンリンクのいずれか一つの同一のワイヤを共有し、
前記複数のメモリモジュール(150A、150B)の各々は、複数のメモリチップ(261A〜N)と、前記複数のメモリチップ(261A〜N)へのアクセスを制御するように結合されたメモリ制御ハブ(160A、160B)とを含み、
前記メモリ制御ハブ(160A、160B)の各々は、前記複数のメモリチップ(261A〜N)に結合されたDRAMコントローラ(250)と、前記複数のメモリリンクの一つである第1のメモリリンク(110A)の前記一方向アップリンク(211A)及び前記複数のメモリリンクの一つである第2のメモリリンク(110B)の前記一方向アップリンク(211B)に結合されたアップリンク制御ユニット(241)と、前記第1のメモリリンク(110A)の前記一方向ダウンリンク(212A)及び前記第2のメモリリンク(110B)の前記一方向ダウンリンク(212B)に結合されたダウンリンク制御ユニット(241)とを含み、
前記一方向ダウンリンクの前記複数の信号は、前記ホスト(100)と前記メモリ制御ハブ(160A、160B)との間に結合された前記複数のメモリモジュール(150A、150B)の前記メモリ制御ハブ(160A、160B)によって投入されることになるローカルトランザクションの数を、各々の前記メモリ制御ハブ(160A、160B)に対して指示するビジー信号を更に含み、
前記メモリ制御ハブ(160A、160B)は、前記ビジー信号に応えて、前記一方向アップリンク(211)にパケットを投入する、システム(50)。 - 前記メモリ制御ハブの各々が、前記複数のメモリチップ(261A〜N)へのアクセスを制御するように結合されており、かつ、前記一方向アップリンク(211)及び前記一方向ダウンリンク(212)の両方を介して前記ホスト(100)に結合されており、
前記複数のメモリモジュール(150A、150B)は、少なくとも、チェーンを形成する第1のメモリモジュール(150A)と、チェーンを形成する最後のメモリモジュールとを含み、
前記複数のメモリモジュール(150A、150B)は、前記第1のメモリモジュール(150A)が前記複数のメモリリンク(110A、B、C)の一つである前記第1のメモリリンクを介して前記ホスト(100)に接続されるようにシリアル接続されてチェーンを形成し、
前記複数のメモリモジュール(150A、150B)は、チェーンを形成する前記最後のメモリモジュールを除いて、前記複数のメモリリンク(110A、B、C)のうちの二つに接続され、前記最後のメモリモジュールは、前記複数のメモリリンク(110A、B、C)のうちの一つにのみ接続される、請求項1に記載のシステム。 - 前記最後のメモリモジュールの前記メモリ制御ハブ(160A、160B)は、受け取ったパケットが前記最後のメモリモジュールに割り当てられたアドレスレンジ内にあるアドレスを含まないパケットであれば、前記パケットを破棄する、請求項2に記載のシステム。
- 前記メモリ制御ハブが、前記第1のメモリリンクの前記一方向ダウンリンク(212A)上で前記トランザクションを受信し、前記トランザクションの復号とは関係なく、前記第2のメモリリンクの前記一方向ダウンリンク(212B)上で前記トランザクションを伝達するように構成された、請求項1に記載のシステム。
- 前記メモリ制御ハブに含まれる前記DRAMコントローラ(250)が、前記メモリ制御ハブと関連するメモリアドレスと整合するメモリアドレスを有するメモリコマンドに前記トランザクションを復号することに応答して、前記複数のメモリチップにアクセスするように構成された、請求項4に記載のシステム。
- 前記メモリ制御ハブが、前記第1のメモリリンクの前記一方向アップリンク上で前記トランザクションを受信し、前記第2のメモリリンクの前記一方向アップリンク上で前記トランザクションを伝達するように構成され、
前記メモリ制御ハブが、前記第2のメモリリンクの前記一方向アップリンク上で伝達されている前記トランザクションのシーケンスにローカルトランザクションを選択的に投入するように構成された制御ユニットを含む、請求項1に記載のシステム。 - 前記ホストが、前記メモリモジュールの各々に関連するメモリサイズまたは前記メモリモジュールの任意のものに関連するアドレスレンジが分からなくても、メモリリエクストトランザクションを発行するように構成されたメモリコントローラ(105)を含む、請求項1に記載のシステム。
- 前記メモリコントローラが、先行メモリリードリクエストトランザクションに対する応答を受信する前に、メモリリードリクエストトランザクションを発行するようにさらに構成された、請求項7に記載のシステム。
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US47007803P | 2003-05-13 | 2003-05-13 | |
US60/470,078 | 2003-05-13 | ||
PCT/US2004/014441 WO2004102403A2 (en) | 2003-05-13 | 2004-05-10 | A system including a host connected to a plurality of memory modules via a serial memory interconnect |
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JP2006528394A JP2006528394A (ja) | 2006-12-14 |
JP4836794B2 true JP4836794B2 (ja) | 2011-12-14 |
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US (4) | US20050071542A1 (ja) |
JP (1) | JP4836794B2 (ja) |
KR (1) | KR101095025B1 (ja) |
CN (1) | CN100444141C (ja) |
DE (1) | DE112004000821B4 (ja) |
GB (1) | GB2416056B (ja) |
TW (1) | TWI351613B (ja) |
WO (1) | WO2004102403A2 (ja) |
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- 2004-05-10 US US10/842,297 patent/US7016213B2/en not_active Expired - Fee Related
- 2004-05-10 KR KR1020057021598A patent/KR101095025B1/ko active IP Right Grant
- 2004-05-10 JP JP2006532883A patent/JP4836794B2/ja active Active
- 2004-05-10 DE DE112004000821.2T patent/DE112004000821B4/de active Active
- 2004-05-10 CN CNB2004800131820A patent/CN100444141C/zh active Active
- 2004-05-10 GB GB0521694A patent/GB2416056B/en active Active
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Also Published As
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GB2416056B (en) | 2006-08-23 |
JP2006528394A (ja) | 2006-12-14 |
WO2004102403A3 (en) | 2005-08-25 |
US20040230718A1 (en) | 2004-11-18 |
US20050162882A1 (en) | 2005-07-28 |
CN100444141C (zh) | 2008-12-17 |
GB0521694D0 (en) | 2005-11-30 |
US7421525B2 (en) | 2008-09-02 |
DE112004000821T5 (de) | 2006-05-11 |
US7016213B2 (en) | 2006-03-21 |
TW200508875A (en) | 2005-03-01 |
WO2004102403A2 (en) | 2004-11-25 |
GB2416056A (en) | 2006-01-11 |
CN1788260A (zh) | 2006-06-14 |
KR101095025B1 (ko) | 2011-12-20 |
US20050166006A1 (en) | 2005-07-28 |
US20050071542A1 (en) | 2005-03-31 |
DE112004000821B4 (de) | 2016-12-01 |
TWI351613B (en) | 2011-11-01 |
KR20060009345A (ko) | 2006-01-31 |
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