TWI456582B - 快閃記憶體系統控制設計 - Google Patents

快閃記憶體系統控制設計 Download PDF

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Publication number
TWI456582B
TWI456582B TW096111391A TW96111391A TWI456582B TW I456582 B TWI456582 B TW I456582B TW 096111391 A TW096111391 A TW 096111391A TW 96111391 A TW96111391 A TW 96111391A TW I456582 B TWI456582 B TW I456582B
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flash memory
pages
memory devices
programming
data file
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TW096111391A
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English (en)
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TW200805396A (en
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Jin-Ki Kim
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Mosaid Technologies Inc
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G06F2212/1036—Life time enhancement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/24—Nonvolatile memory in which programming can be carried out in one memory bank or array whilst a word or sector in another bank or array is being erased simultaneously

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Claims (6)

  1. 一種用於具有複數個快閃記憶體裝置的一快閃記憶體系統中之高速耗損程度控制燒錄之方法，包含下列步驟：接收具有k個分頁之一資料檔案，其中k是大於0的一整數；藉由計算上限函數z=k/i，選擇與k的大小及該快閃記憶體系統的組態設定參數對應之一燒錄設定檔，該組態設定參數包含j個快閃記憶體裝置，其中該j個快閃記憶體裝置的每一者在每一區塊中具有i個分頁，其中j與i為大於0的整數；以及根據該燒錄設定檔，而在該複數個快閃記憶體裝置的至少兩個快閃記憶體裝置中之每一快閃記憶體裝置中燒錄該資料檔案的該等k分頁中之至少一分頁，當z大於i時，該燒錄設定檔包含多重檔案結構，該多重檔案結構包含，當z小於或等於j時，將該資料檔案的j*i個分頁中之m個單位儲存在j個快閃記憶體裝置中，且將該資料檔案的k-(m*(j*i))個分頁儲存在j個快閃記憶體裝置的z個快閃記憶體裝置中，其中m為大於0的整數。
  2. 如申請專利範圍第1項之方法，其中該燒錄步驟包含下列步驟：將燒錄命令循序地提供給該等j個快閃記憶體裝置中之每一快閃記憶體裝置，以便燒錄該資料檔案的該等j*i個分頁，其中每一燒錄命令係用於燒錄該等k個分頁中之至少一分頁。
  3. 如申請專利範圍第2項之方法，其中該燒錄步驟包含下列步驟：將燒錄命令循序地提供給該等z個快閃記憶體裝置中之每一快閃記憶體裝置，以便燒錄該等k-(m*(j*i))個分頁，其中每一燒錄命令係用於燒錄該等k個分頁中之至少一分頁。
  4. 如申請專利範圍第1項之方法，其中至少二該複數個快閃記憶體裝置相互串聯。
  5. 如申請專利範圍第4項之方法，其中該複數個快閃記憶體裝置之該至少二者之第一快閃記憶體裝置執行第一燒錄作業以回應第一命令，且當該第一閃記憶體裝置正執行該第一燒錄作業時，該複數個快閃記憶體裝置之該至少二者之第二快閃記憶體裝置起始第二燒錄作業以回應第二命令。
  6. 如申請專利範圍第5項之方法，其中在該第二快閃記憶體裝置起始該第二燒錄作業前，將該第二命令透過該第一快閃記憶體裝置傳遞給該第二快閃記憶體裝置。
TW096111391A 2006-03-31 2007-03-30 快閃記憶體系統控制設計 TWI456582B (zh)

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EP (2) EP2242058B1 (zh)
JP (1) JP5214587B2 (zh)
KR (1) KR101194965B1 (zh)
CN (2) CN102063931B (zh)
AT (1) ATE488009T1 (zh)
DE (1) DE602007010439D1 (zh)
ES (1) ES2498096T3 (zh)
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