US20040037112A1 - Nonvolatile semiconductor memory device having improved redundancy relieving rate - Google Patents

Nonvolatile semiconductor memory device having improved redundancy relieving rate Download PDF

Info

Publication number
US20040037112A1
US20040037112A1 US10/357,411 US35741103A US2004037112A1 US 20040037112 A1 US20040037112 A1 US 20040037112A1 US 35741103 A US35741103 A US 35741103A US 2004037112 A1 US2004037112 A1 US 2004037112A1
Authority
US
United States
Prior art keywords
memory cell
memory cells
data
spare
nonvolatile semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/357,411
Other languages
English (en)
Inventor
Tsukasa Ooishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OOISHI, TSUKASA
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI DENKI KABUSHIKI KAISHA
Publication of US20040037112A1 publication Critical patent/US20040037112A1/en
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI DENKI KABUSHIKI KAISHA
Priority to US11/145,980 priority Critical patent/US7061800B2/en
Priority to US11/409,121 priority patent/US7277330B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/02—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using magnetic elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells

Definitions

  • the present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a spare memory cell for replacing a defective memory cell.
  • a semiconductor memory device which executes data storage
  • various data storage formats are employed to store data in memory cells.
  • a semiconductor memory device constituted so that the pass current of each memory cell changes according to data stored in the memory cell when the memory cell is accessed.
  • the data stored in a selected memory cell is read in accordance with the comparison between the pass current of the selected memory cell to be accessed and a preset reference current.
  • MRAM Magnetic Random Access Memory
  • MRAM device which includes memory cells each having the MTJs is disclosed, for example, in the following technical documents:
  • FIG. 18 is a schematic diagram showing a configuration of a memory cell which has a tunnel junction (hereinafter, also simply referred to as “MTJ memory cell”).
  • MTJ memory cell tunnel junction
  • the MTJ memory cell includes a tunneling magneto-resistance element TMR having electric resistance which changes in accordance with the data level of magnetically written storage data, and an access transistor ATR.
  • Access transistor ATR is connected in series to tunneling magneto-resistance element TMR between a write bit line WBL and a read bit line RBL.
  • access transistor ATR a field effect transistor formed on a semiconductor substrate is typically employed.
  • write bit line WBL and write digit line WDL each for carrying data write currents in different directions during data write, a word line WL for instructing data read, and read bit line RBL receiving the supply of the data read currents are provided.
  • tunneling magneto-resistance element TMR is electrically coupled between write bit line WBL set at a ground voltage GND and read bit line RBL.
  • FIG. 19 is a conceptual view for describing a data write operation for writing data to the MTJ memory cell.
  • tunneling magneto-resistance element TMR includes a ferromagnetic material layer FL which has a fixed constant magnetic direction (hereinafter, also simply referred to as “fixed magnetic layer”) and a ferromagnetic material layer VL which is magnetized in a direction according to a magnetic field applied from externally (hereinafter, also simply referred to as “free magnetic layer”).
  • a tunneling barrier (tunneling film) TB formed from an insulating film is provided between fixed magnetic layer FL and free magnetic layer VL.
  • Free magnetic layer VL is magnetized in the same direction or the opposite direction to that of fixed magnetic layer FL in accordance with the level of stored data to be written.
  • Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
  • the electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetic direction of fixed magnetic layer FL and that of free magnetic layer VL. Specifically, if the magnetic direction of fixed magnetic layer FL is parallel to that of free magnetic layer VL, the electric resistance value of tunneling magneto-resistance element TMR is a minimum value Rmin. If these magnetic directions are opposite (non-parallel) to each other, the electric resistance value of tunneling magneto-resistance element TMR is a maximum value Rmax.
  • word line WL is deactivated and access transistor ATR is turned off.
  • a data write current for magnetizing free magnetic layer VL is carried to each of bit line BL and write digit line WDL in a direction according to the level of the write data.
  • FIG. 20 is a conceptual view for describing the relationship between the data write current and the magnetic direction of a tunneling magneto-resistance element during data write.
  • the horizontal axis indicates a magnetic field applied in an easy axis (EA: Easy Axis) direction in free magnetic layer VL in tunneling magneto-resistance element TMR.
  • the vertical axis H(HA) indicates a magnetic field applied in a hard axis (HA: Hard Axis) direction in free magnetic layer VL.
  • Magnetic fields H(EA) and H(HA) correspond to two magnetic fields generated by currents carried to bit line BL and write digit line WDL, respectively.
  • the fixed magnetic direction of fixed magnetic layer FL is along the easy axis of free magnetic layer VL.
  • Free magnetic layer VL is magnetized in a direction parallel or non-parallel (opposite) to fixed magnetic layer FL along the easy axis direction in accordance with the level of stored data (“1” or “0”).
  • the MTJ memory cell can store 1-bit data (“1” and “0”) corresponding to the two magnetic directions of free magnetic layer VL.
  • the magnetic direction of free magnetic layer VL can be rewritten only when the sum of magnetic fields H(EA) and H(HA) applied to free magnetic layer VL reaches a region outside of an asteroid characteristic line shown in FIG. 20.
  • the data write magnetic field applied to free magnetic layer VL has an intensity corresponding to the region inside of the asteroid characteristic line, the magnetic direction of free magnetic layer VL has no change.
  • the data write magnetic field in the easy axis direction is designed so as to have an intensity of H WR in the MTJ memory cell to which the data is to be written. That is, the value of the data write current carried to each of bit line BL and write digit line WDL is designed so as to obtain this data write magnetic field H WR .
  • tunneling magneto-resistance element TMR In order to rewrite the stored data of the MTJ memory cell, i.e., to rewrite the magnetic direction of tunneling magneto-resistance element TMR, it is necessary to carry a data write current at predetermined level or higher to each of write digit line WDL and bit line BL. Thereby, free magnetic layer VL in tunneling magneto-resistance element TMR is magnetized in the direction parallel or opposite (non-parallel) to that of fixed magnetic layer FL in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetic direction which is written to tunneling magneto-resistance element TMR once, i.e., the stored data of the MTJ memory cell is held in a nonvolatile manner until new data is written.
  • FIG. 21 is a conceptual view for describing a data read operation for reading data from the MTJ memory cell.
  • access transistor ATR is turned on in response to the activation of word line WL.
  • Write bit line WBL is set at ground voltage GND.
  • tunneling magneto-resistance element TMR is electrically coupled to read bit line RBL while being pulled down at ground voltage GND.
  • a memory cell current Icell according to the electric resistance of tunneling magneto-resistance element TMR, i.e., according to the level of the stored data in the MTJ memory cell, passes through a current path which includes read bit line RBL and tunneling magneto-resistance element TMR.
  • a predetermined current for example, it is possible to read the data stored in the MTJ memory cell.
  • tunneling magneto-resistance element TMR changes according to the magnetic direction which can be rewritten by the data write magnetic field applied thereto. Therefore, if electric resistance values Rmax and Rmin of tunneling magneto-resistance element TMR are made to correspond to the levels (“1” and “0”) of the stored data, respectively, it is possible to store nonvolatile data.
  • the spare memory cells are often provided in a portion peripheral of a memory cell array. If the spare memory cells are located in such a peripheral portion, the finished dimensions of elements tend to exhibit a wide range of variation compared with the central portion of the memory cell array. If a spare memory cell is defective, a chip cannot be relieved even by replacing a defective memory cell by the spare memory cell.
  • the present invention provides a nonvolatile semiconductor memory device including: a plurality of normal memory cells each storing data of one bit in a nonvolatile manner; a plurality of spare memory cells each used in place of a defective memory cell when the defective memory cell is present in the plurality of normal memory cells, and constituted so that two spare memory cells store data of one bit as a whole; a control circuit, in accordance with an external access, selecting a first memory cell group corresponding to an address signal from among the plurality of normal memory cells and selecting a second memory cell group from among the plurality of spare memory cells in parallel to selection of the first memory cell group; and a select and amplification section selecting a read memory cell group in accordance with the address signal from among the first and second memory cell groups, and amplifying and outputting the data held in the read memory cell group.
  • a main advantage of the present invention is as follows. Since the two spare memory cells store data of one bit as a whole, a spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.
  • FIG. 1 is a schematic block diagram showing the configuration of a nonvolatile semiconductor memory device 1 according to a first embodiment of the present invention
  • FIG. 2 is a block diagram for describing a data read system of nonvolatile semiconductor memory device 1 shown in FIG. 1;
  • FIG. 3 is a block diagram for describing a data write system of nonvolatile semiconductor memory device 1 shown in FIG. 1;
  • FIG. 4 is a circuit diagram showing the configurations of the read and write systems of nonvolatile semiconductor memory device 1 shown in FIGS. 2 and 3 in more detail;
  • FIG. 5 is a circuit diagram for describing an example of a circuit which controls deactivation when a spare memory cell is selected in a write driver 131 ;
  • FIG. 6 is a circuit diagram showing the configuration of a program array 36 shown in FIG. 1;
  • FIG. 7 shows the change of the resistance value of a normal MTJ element
  • FIG. 8 shows the change of the resistance value of the MTJ element which has data fixed
  • FIG. 9 is a circuit diagram showing the configuration of a CAM array 38 shown in FIG. 1;
  • FIG. 10 is a circuit diagram showing the configuration of a consistency detection section 431 shown in FIG. 9;
  • FIG. 11 is a circuit diagram showing the configuration of a select and amplification section 40 shown in FIG. 1;
  • FIG. 12 shows the configuration of a data read system of a nonvolatile semiconductor memory device according to a second embodiment of the present invention
  • FIG. 13 is a circuit diagram for describing a memory array 10 a and a spare memory array 12 a described with reference to FIG. 12 in more detail;
  • FIG. 14 is a plan view showing the shapes of memory cells in a phase-changing memory
  • FIG. 15 is a cross-sectional view taken along line A-A of FIG. 14;
  • FIG. 16 is an equivalent circuit diagram of the memory cell array shown in FIG. 14;
  • FIG. 17 is a circuit diagram showing a case where the present invention is applied to a phase-changing memory
  • FIG. 18 is a schematic diagram showing the configuration of a memory cell having a tunnel junction
  • FIG. 19 is a conceptual view for describing a data write operation for writing data to an MTJ memory cell
  • FIG. 20 is a conceptual view for describing the relationship between a data write current and the magnetic direction of a tunneling magneto-resistance element during data write.
  • FIG. 21 is a conceptual view for describing a data read operation for reading data from the MTJ memory cell.
  • FIG. 1 is a schematic block diagram showing the configuration of a nonvolatile semiconductor memory device 1 according to a first embodiment of the present invention.
  • nonvolatile semiconductor memory device 1 randomly accesses a memory cell in response to an external control signal CMD and an external address signal ADD and executes the input of write data DIN and the output of read data DAT.
  • Nonvolatile semiconductor memory device 1 includes a control circuit 5 which controls the entire operation of nonvolatile semiconductor memory device 1 in accordance with control signal CMD, and a memory array 10 which includes MTJ memory cells MC arranged in a matrix.
  • word lines WL and write digit lines WDL are arranged to correspond to the respective rows of the MTJ memory cells.
  • bit lines BL and source lines SL are arranged to correspond to the respective columns of the MTJ memory cells MC.
  • FIG. 1 typically shows the arrangement of one MTJ memory cell MC, and one word line WL, one write digit line WDL, one bit line BL and one source line SL correspond to MTJ memory cell MC.
  • Nonvolatile semiconductor memory device 1 also includes a row decoder 20 which decodes a row address RA shown by an address signal and executes row selection in memory array 10 , a column decoder 25 which decodes a column address CA shown by address signal ADD and executes column selection in memory array 10 , and a read/write control circuit 30 .
  • Read/write control current 30 generically expresses a circuit for carrying a data write current to bit line BL during data write and a circuit for carrying a data read current to bit line BL during data read.
  • Nonvolatile semiconductor memory device 1 further includes a spare memory array 12 provided adjacent to memory array 10 , and a redundancy select section 32 .
  • Spare memory array 12 shares word line WL and write digit line WDL with memory array 10 .
  • Redundancy select section 32 selects a part of a plurality of spare bit lines SBL included in spare memory array 12 .
  • nonvolatile semiconductor memory device 1 includes a pad 34 for applying a predetermined high potential SVCC from externally, a CAM (Content Addressable Memory) array 38 to which replacement address information is transferred from program array 36 , and a select and amplification section 40 .
  • a pad 34 for applying a predetermined high potential SVCC from externally for applying a predetermined high potential SVCC from externally, a CAM (Content Addressable Memory) array 38 to which replacement address information is transferred from program array 36 , and a select and amplification section 40 .
  • CAM Content Addressable Memory
  • the replacement address information which is held in program array 36 in a nonvolatile manner is transferred to CAM array 38 when a power supply is turned on.
  • CAM array 38 compares the transferred replacement address information with input address information ADD at high rate, and outputs a control signal RCON.
  • Redundancy select section 32 selects a part of a plurality of spare bit lines SBL in accordance with control signal RCON.
  • Select and amplification section 40 selects read data transmitted from read/write control circuit 30 and redundancy select section 32 in accordance with control signal RCON and outputs read data DAT.
  • Control circuit 5 , row decoder 20 , column decoder 25 , read/write control circuit 30 , CAM array 38 and redundancy select section 32 form a select control circuit of nonvolatile semiconductor memory device 1 as a whole.
  • This select control circuit selects a first memory cell group corresponding to address signal ADD from among a plurality of normal memory cells in accordance with an external access.
  • the select control circuit selects a second memory cell group from among a plurality of spare memory cells. By selecting spare memory cells in parallel to the normal memory cells, a read operation rate is accelerated.
  • FIG. 2 is a block diagram for describing a data read system of nonvolatile semiconductor memory device 1 shown in FIG. 1.
  • memory array 10 includes normal memory cell blocks 51 to 53 and reference cell columns 61 to 63 .
  • the data read from normal memory cell blocks 51 to 53 is compared with a reference value which corresponds to an intermediate level between a high level and a low level held in reference cell columns 61 to 63 , respectively, whereby the data stored in each memory cell is determined.
  • Spare memory array 12 includes spare memory cell columns 71 to 73 . Two memory cells store data of one bit as a whole in each spare memory cell. Therefore, compared with normal memory cells each of which stores data of one bit, the reliability of the spare memory cells is improved.
  • Selectors 81 to 83 are provided to correspond to normal memory blocks 51 to 53 , respectively.
  • IO line pairs IOP 1 to IOP 3 are provided to correspond to normal memory cell blocks 51 to 53 , respectively.
  • the output of selector 81 is connected to one of the IO lines in IO line pair IOP 1 by a connection section 91 , and that of reference cell column 61 is connected to the other IO line in IO line pair IOP 1 by a connection section 92 .
  • the output of selector 82 is connected to one of the IO lines in IO line pair IOP 2 by a connection section 93 , and that of reference cell column 62 is connected to the other IO line in IO line pair IOP 2 by a connection section 94 .
  • the output of selector 83 is connected to one of the IO lines in IO line pair IOP 3 by a connection section 95 , and that of reference cell column 63 is connected to the other IO line in IO line pair IOP 1 by a connection section 96 .
  • FIG. 2 shows a case where the three IO line pairs and the three normal memory blocks are provided
  • the number of IO line pairs and that of normal memory blocks may be larger or smaller than 3 as long as the number of normal memory blocks is equal to that of the corresponding IO line pairs.
  • An accessed memory cell in a normal memory cell block is connected to one of the IO line in an IO line pair, and a memory cell in the corresponding reference cell column is connected to the other IO line in the IO line pair.
  • a part of spare memory cell columns 71 to 73 are selected by a selector 84 .
  • Selector 84 selects two out of the three spare memory cell columns in accordance with control signal RCON outputted from CAM array 38 shown in FIG. 1, and connects the two selected spare cell columns to two IO line pairs IOP 4 and IOP 5 provided to be dedicated to the data transmission for the spare memory cells.
  • Each spare memory cell column is constituted so that two memory cells store data of one bit as a whole.
  • Two spare bit lines SBL are provided per spare memory cell column.
  • Selector 84 selects two out of the three spare memory cell columns to transmit data from these selected cell columns to spare column-dedicated IO line pairs IOP 4 and IOP 5 .
  • the selection of selector 84 is made in accordance with control signal RCON outputted from CAM array 38 which detects redundancy.
  • a spare bit line to be used according to an input address is connected to the spare column-dedicated IO line pair by selector 84 .
  • selector 84 may not be provided. In this case, the data from spare memory array 12 is all outputted up to a select section 100 . Thereby, it is unnecessary to apply a redundancy detection result to the selector section of a bit line output section, which may possibly accelerate operation rate.
  • selector 84 is provided and selector 84 selects two out of the three spare memory cell columns when connecting the selected columns to the IO line pairs for the following reason. If the number of IO line pairs increases, the area of nonvolatile semiconductor memory device 1 disadvantageously increases by as much as the increased number of provided IO line pairs.
  • Selectors 81 to 83 and connection sections 91 to 96 shown in FIG. 2 correspond to a part of read/write control circuit 30 shown in FIG. 1.
  • selector 84 corresponds to a part of redundancy select section 32 shown in FIG. 1.
  • selected memory cells are connected to a total of five IO line pairs.
  • Select and amplification section 40 includes select section 100 which selects three out of five IO line pairs IOP 1 to IOP 5 in accordance with control signal RCON and sense amplifiers 101 to 103 for reading the data of the memory cells connected to the IO line pairs selected by select section 100 .
  • the number of sense amplifiers is set 3 equal to that of data necessary to be outputted to terminals 111 to 113 .
  • IO line pair to which a defective memory cell detected by CAM array 38 shown in FIG. 1 is connected and the IO line pair connected to an unnecessary spare bit line are not connected to sense amplifiers 101 to 103 .
  • Sense amplifier 101 to 103 are connected to the memory cells which store data corresponding to inputted addresses through the corresponding IO line pairs.
  • sense amplifiers 101 to 103 are normal memory cells, sense amplifiers 101 to 103 are also connected to a reference memory cell which is present in the corresponding reference cell column and compare current values carried to the two memory cells.
  • sense amplifiers 101 to 103 compare current values carried to the two complementary memory cells.
  • each spare memory cell column two memory cells store data of one bit as a whole, dedicated IO line pairs for reading data from the spare memory cells are provided, and the spare memory cells are selected depending on which IO line pairs the sense amplifiers which detect current on the connected IO line pairs are connected to.
  • FIG. 3 is a block diagram for describing a data write system of nonvolatile semiconductor memory device 1 shown in FIG. 1.
  • nonvolatile semiconductor memory device 1 is MRAM
  • a path for accessing the spare memory cell columns changes between data write and data read.
  • the input data (three pieces of data in FIG. 3) are normally transmitted to write drivers 121 to 123 and 131 to 133 for corresponding blocks and each of the corresponding write drivers is controlled to carry a current to desired bit line BL.
  • Write data DIN is distributed to spare memory array 12 by a distribution circuit 150 based on control signal RCON which shows the redundancy detection result.
  • RCON which shows the redundancy detection result.
  • the write driver corresponding to this defective memory cell is deactivated in the normal memory cell region.
  • the write driver corresponding to the spare memory cell to which data is to be written in place of the defective normal memory cell is activated.
  • the write driver thus activated performs a data write operation in accordance with the data.
  • Each of the write drivers in the normal region may perform a data write operation even if its corresponding memory cell is a defective memory cell. In this embodiment, however, the write driver corresponding to the defective memory cell is deactivated with a configuration to be described later with reference to FIG. 5 so as to avoid increasing a write current.
  • Inputted write data DIN is distributed to memory array 10 or spare memory array 12 in accordance with control signal RCON showing the redundancy detection result. If the address to which write data DIN is to be written corresponds to the defective memory cell, distribution circuit 150 distributes write data DIN not to the corresponding normal memory block in the normal memory array but to spare memory cell columns 71 to 73 . Further, corresponding one of write drivers 141 to 143 is activated.
  • FIG. 4 is a circuit diagram showing the configurations shown in FIGS. 2 and 3 in more detail.
  • FIG. 4 typically shows normal memory cell block 51 , reference cell column 61 , spare memory cell column 71 and their related circuits.
  • Normal memory cell block 51 includes memory cells MC arranged in a matrix.
  • One memory cell MC stores data of one bit.
  • Write drivers 121 and 131 for data write and connection section 91 for data read are connected to bit lines BLA and BLB.
  • Write drivers 121 and 131 are arranged on the both ends of each of bit lines BLA and BLB.
  • the direction of a current carried to bit lines when data “0” is written to memory cell MC is opposite to that of a current carried thereto when data “1” is written to memory cell MC. Specifically, if data “1” is written to memory cell MC, a transistor 181 in write driver 121 is set conductive and a transistor 192 in write driver 131 is set conductive. Thereby, a current is carried across bit line BLA in a direction from write driver 121 to write driver 131 .
  • transistors 183 , 184 , 193 and 194 are controlled based on write data DIN.
  • reference symbol W 1 denotes a signal which is activated when data “1” is written to memory cell MC and reference symbol W 0 denotes a signal which is activated when data “0” is written thereto.
  • the transistors in write drivers 121 are controlled to be activated in a reversed manner from the transistors in write drivers 131 .
  • the transistors may be activated to fix the potential of bit lines to ground potential GND or all of transistors 181 to 184 and 191 to 194 may be set nonconductive to turn the bit lines in a floating state.
  • FIG. 5 is a circuit diagram for describing an example of a circuit in write driver 131 , which controls deactivation when a spare cell is selected.
  • a control unit 195 includes an AND circuit 196 which receives a control signal /HIT and a signal SW 0 , and an AND circuit 197 which receives control signal /HIT and a signal SW 1 .
  • the output of AND circuit 196 is applied to the gate of transistor 191 .
  • the output of AND circuit 197 is applied to the gate of transistor 192 . If CAM array 38 shown in FIG. 1 determines that the input address coincides with the address of a defective memory cell, the write drivers for the normal memory cells are deactivated to decrease power consumption. If control signal /HIT is deactivated to L level, the levels of outputs of AND circuits 196 and 197 become L level to thereby make both transistors 191 and 192 nonconductive. As a result, bit line BLA turns into a floating state.
  • transistors 171 to 174 become conductive and transistors 161 to 164 become nonconductive.
  • digit line driver 155 activates one of digit lines WDL 1 to WDL 4 in accordance with a write address.
  • a connection gate 215 connects a spare bit line SBLA to spare bit line SBLB.
  • Digit line driver 155 activates one of word lines WL 1 to WL 4 in accordance with a read address.
  • Connection section 91 includes a connection gate 211 which is provided between bit line BLA and an IO line IO 1 A and the gate of which receives a select signal CSLA, and a connection gate 212 which is provided between bit line BLB and an IO line IO 1 B and the gate of which receives a select signal CSLB.
  • Select signal CSLA is outputted from a decoding circuit 221 included in column decoder 25 which decodes column address CA.
  • Select signal CSLB is outputted from a decoding circuit 222 included in column decoder 25 .
  • Reference cell column 61 includes reference memory cells MCR each of which stores a reference value for determining the data of corresponding normal memory cell MC.
  • the write and read of the reference value to each reference memory cell MCR are performed in the same manner as those of data to each normal memory cell MC. However, during data read, the connection of the reference memory cell to the IO line is specially contrived.
  • a bit line BLR corresponding to a reference memory cell column is connectable to both IO lines IO 1 A and IO 1 B by connection section 92 .
  • Connection section 92 includes a connection gate 213 which is connected between bit line BLR and IO line IO 1 B and the gate of which receives a control signal SREFA, and a connection gate 214 which is connected between bit line BLR and IO line IO 1 A and the gate of which receives a control signal SREFB.
  • Select signal SREFA is activated when select signal CSLA is activated. Thereby, if bit line BLA is connected to IO line IO 1 A, reference bit line BLR is connected to IO line IO 1 B. As a result, an amplification section 104 detects the difference in current value between a current carried to memory cell MC and that carried to memory cell MCR.
  • select signal SREFB is activated when select signal CSLB is activated. Therefore, if bit line BLB is connected to IO line IO 1 B, bit line BLR is connected to IO line IO 1 A.
  • the reason for connecting adjacent bit lines BLA and BLB to different IO lines is to uniformly distribute the junction capacities of connection gates 211 and 212 to the IO lines. In accordance with this rule, it is necessary to selectively connect reference bit line BLR to appropriate IO line.
  • each spare memory cell column two memory cells store data of one bit as a whole.
  • bit line SBLA and SBLB are connected to each other by connection gate 215 during data write.
  • bit lines SBLA and SBLB are connected to each other on one side by connection gate 215 , the direction in which the current is carried to bit line SBLA and that in which the current is carried to bit line SBLB during data write are always opposite each other. As a result, complementary pieces of data are written to two spare memory cells selected by a digit line.
  • Spare memory cell columns 72 and 73 are arranged in nonvolatile semiconductor memory device 1 .
  • Selector 84 selects two out of the three spare memory cell columns to connect the selected spare memory cell columns to IO line pairs IOP 4 and IOP 5 dedicated to the data read operation for reading data from spare memory cells.
  • connection gate 215 does not connect bit lines SBLA and SBLB in spare memory cell column 71 and different currents are carried to spare memory cells SMCA and SMCB.
  • one normal memory cell stores data of one bit by comparing the normal memory cell with the reference memory cell which holds a reference value.
  • Two spare memory cells store data of one bit as a whole. Namely, complementary pieces of data are written to two spare memory cells, respectively and the two spare memory cells are connected to a sense amplifier, thereby reading the stored data of one bit.
  • the spare memory cell region which is often arranged in the peripheral portion of the memory cell array is more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell thereby increases.
  • FIG. 6 is a circuit diagram showing the configuration of program array 36 shown in FIG. 1.
  • program array 36 includes a digit line driver 301 , write drivers 303 , 305 , and control circuits 302 and 306 which control write drivers 303 and 305 , respectively.
  • Program array 36 also includes bit lines 351 to 354 , a source line 330 , a write digit lines 331 to 335 and word lines 341 to 345 .
  • program array 36 includes MRAM memory cells 361 to 364 provided corresponding to digit line 331 and word line 341 . Likewise, memory cells are arranged corresponding to the other word lines and digit lines and a memory cell array 307 is thereby constituted.
  • transistors 321 to 325 become conductive and digit line driver 301 selectively activates digit lines 331 to 335 .
  • transistors 311 to 315 become conductive and transistors 321 to 325 become nonconductive.
  • Digit line driver 301 selectively activates word lines 341 to 345 during data read.
  • Memory cell columns connected to bit lines 351 and 352 correspond to a region which stores flags each indicating whether or not a program set is used. Program addresses are stored in the other region.
  • two memory cells stores data of one bit as a whole so as to secure high reliability as in the case of the spare memory cell array.
  • Data write is realized by, for example, writing complementary pieces of data to memory cells 361 and 362 .
  • control circuits 302 and 306 control the directions of currents in accordance with write data.
  • Reference symbol W 1 denotes a gate which is activated when data “1” is written and W 0 denotes a gate which is activated when data “0” is written.
  • Program array 36 further includes sense amplifiers 395 and 396 and control gates 391 to 394 which connect sense amplifiers to bit lines. If data is read from memory cells 361 and 362 , connection gates 391 and 392 connect bit lines 351 and 352 to sense amplifier 395 , respectively. If digit line driver 301 activates word line 341 , sense amplifier 395 detects the difference between a current carried into source line 330 through memory cell 361 and a current carried into source line 330 through memory cell 362 . A detection result is transferred, as a signal P 1 , to CAM array 38 shown in FIG. 1.
  • connection gates 393 and 394 are made conductive, sense amplifier 396 detects a current difference and transfers a detection result, as a signal Pn, to CAM array 38 .
  • This transfer operation is performed when a current is carried to the chip, for example.
  • CAM array 38 can detect the consistency between an input address and a program address at high rate.
  • FIG. 7 shows the change of the resistance value of a normal MTJ element.
  • a magnetic field H changes if a current is carried to the digit line.
  • the resistance of the MTJ element of the memory cell changes between high resistance Rmax and low resistance Rmin. If high voltage SVCC is applied, the MTJ element is destroyed and the resistance value of the MTJ element becomes Rb 1 which is far lower than low resistance Rmin.
  • FIG. 8 shows the change of the resistance value of an MTJ element after data is fixed.
  • the written data can be read as the expected value, it can be determined that memory cell 361 is not destroyed. If opposite data is written to memory cell 361 and the state can be fixedly read, then it can be determined that memory cell 361 is a destroyed program set. Thereby, if a failure which generates after a normal relieving step is to be relieved, it is possible to program a defective address in program array 36 while avoiding the already destroyed program set.
  • FIG. 9 is a circuit diagram showing the configuration of CAM array 38 shown in FIG. 1.
  • CAM array 38 includes a flag storage section 401 , an address storage section 402 , a consistency detection section 403 , and a storage section 404 which stores the location of a spare memory cell column to be used.
  • Flag storage section 401 includes five latch circuits 411 to 415 corresponding to five program sets which store different replacement information.
  • Address storage section 402 includes program sets 421 to 425 corresponding to latch circuits 411 to 415 , respectively.
  • Consistency detection section 403 includes consistency detection sections 431 to 435 corresponding to program sets 421 to 425 , respectively.
  • Storage section 404 includes storage units 441 to 445 which are activated in accordance with the outputs of consistency detection sections 431 to 435 . The outputs of storage units 441 to 445 become control signal RCON.
  • Signals P 1 to Pn outputted from program array 36 as already described above with reference to FIG. 6 are inputted into flag storage section 401 and address storage section 402 and held in the latch circuits.
  • the output of flag storage section 401 is outputted to consistency detection section 403 and to a selector 405 .
  • Selector 405 selects one of the outputs of latch circuits 411 to 415 in accordance with a set address SETADD for specifying one of program sets 421 to 425 .
  • Output circuit 406 is activated in accordance with a signal FREAD activated in a test mode to thereby output the output of selector 405 to terminal PO.
  • FIG. 10 is a circuit diagram showing the configuration of consistency detection section 431 shown in FIG. 9.
  • consistency detection section 431 receives a flag signal FLAG corresponding to program set 421 in flag storage section 402 , the outputs of latches 452 to 45 n included in program set 421 and inputted address signal ADD.
  • Latch 452 holds the least significant bit of the replacement address and latch 45 n holds the most significant bit thereof.
  • Consistency detection section 431 includes consistency detection circuits 461 to 46 n each of which performs comparison between a replacement address outputted from program set 421 and an input address signal in every bit, and an AND circuit 470 receiving a signal FLAG and the outputs of consistency detection circuits 461 to 46 n and outputting a signal HITI.
  • consistency detection sections 431 to 435 determine whether the outputs of program sets 421 to 425 in which corresponding flags are activated coincide with inputted addresses. According to the determination results, selector 84 performs a select operation during data read.
  • selector 84 shown in FIG. 2 performs a select operation to connect two out of three spare memory cell columns 71 to 73 to the IO line pairs in accordance with the contents held in storage units 441 to 445 included in storage section 404 . Further, to connect IO line pairs IOP 1 to IOP 5 to sense amplifiers 101 to 103 , the IO line pair corresponding to the address of a defective column is made unconnected and the data read from the spare bit line is transmitted to the sense amplifier through the spare column-dedicated IO line pair.
  • the write driver for the bit line connected to the detected defective memory cell is deactivated and the write data is transmitted to the write driver for the spare bit line.
  • the number of program sets and that of spare memory cell columns do not always have a one-by-one correspondence.
  • the number of program sets can be arbitrarily selected relative to that of redundant spare memory cell columns. By providing flag bits, it is possible to detect an unused program set when a replacement address is added. In addition, the flexibility for the selection of the number of redundant memory cells and that of program sets each storing a replacement address increases.
  • FIG. 11 is a circuit diagram showing the configuration of select and amplification section 40 shown in FIG. 1.
  • select and amplification section 40 includes a select section 100 and an amplification section 104 .
  • Select section 100 selects three out of the five IO line pairs in accordance with control signal RCON.
  • Select section 100 includes a switching circuit 481 which selects one of IO lines IO 1 A, IO 2 A and IO 3 A and connects the selected 10 line to an IO line RIO 1 A, and a switching circuit 491 which selects one of IO lines IO 1 B, IO 2 B and IO 3 B and connects the selected IO line to an IO line RIO 1 B.
  • Select section 100 also includes a switching circuit 482 which selects one of IO lines IO 2 A, IO 3 A and IO 4 A and connects the selected IO line to an IO line RIO 2 A, and a switching circuit 492 which selects one of IO lines IO 2 B, IO 3 B and IO 4 B and connects the selected IO line to an IO line RIO 2 B.
  • select section 100 includes a switching circuit 483 which selects one of IO lines IO 3 A, IO 4 A and IO 5 A and connects the selected 10 line to an IO line RIO 3 A, and a switching circuit 493 which selects one of IO lines IO 3 B, IO 4 B and IO 5 B and connects the selected IO line to an IO line RIO 3 B.
  • Amplification section 104 includes a sense amplifier 101 which detects the difference between a current carried to the memory cell connected to IO line RIO 1 A and that carried to the memory cell connected to IO line RIO 1 B to thereby read stored data, a sense amplifier 102 which detects the difference between a current carried to the memory cell connected to IO line RIO 2 A and that carried to the memory cell connected to IO line RIO 2 B to thereby read stored data, and a sense amplifier 103 which detects the difference between a current carried to the memory cell connected to IO line RIO 3 A and that carried to the memory cell connected to IO line RIO 3 B to thereby read stored data.
  • Switching circuit 481 includes a decoder 500 which decodes control signal RCON, connection gates 501 , 502 and 503 which connect IO lines IO 1 A, IO 2 A and IO 3 A, respectively to IO line RIO 1 A in accordance with the output of decoder 500 .
  • Decoder 500 decodes a specific bit of the IO line corresponding to a defective memory cell and a bit for specifying a spare cell column including a spare memory cell which replaces the defective memory cell. Decoder 500 sets one of connection gates 501 , 502 and 503 in a connected state based on the decoding result.
  • FIG. 12 is a block diagram of a data read system of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.
  • the nonvolatile semiconductor memory device in the second embodiment differs from that shown in FIG. 2 in that a memory array 10 a instead of memory array 10 and a spare memory array 12 a instead of spare memory array 12 are provided.
  • Memory array 10 a includes normal memory cell blocks 51 a to 53 a , reference rows 601 to 603 provided to correspond to normal memory cell blocks 51 a to 53 a , and selectors 81 a to 83 a .
  • the output of selector 81 a is connected to IO line pair IOP 1 .
  • the output of selector 82 a is connected to IO line pair IOP 2 .
  • the output of selector 83 a is connected to IO line pair IOP 3 .
  • Spare memory array 12 a includes spare memory cell columns 71 a to 73 a , and a selector 84 a which selects one of spare memory cell columns 71 a to 73 a in accordance with control signal RCON.
  • the output of selector 84 a is connected to IO line pairs IOP 4 and IOP 5 .
  • select and amplification section 40 Since the configuration of select and amplification section 40 is the same as that described with reference to FIG. 2, it will not be repeatedly described herein.
  • the second embodiment is the same as the first embodiment in that two spare bit lines SBL are arranged in each spare cell column and two spare cells store data of one bit as a whole.
  • the second embodiment differs from the first embodiment in that reference rows 601 to 603 each holding a reference value during data read are arranged in parallel to the word lines of the normal memory cell blocks.
  • Selectors 81 a to 83 a are provided to correspond to normal memory cell blocks 51 a to 53 a , respectively.
  • IO line pairs IOP 1 to IOP 3 are provided to correspond to normal memory cell blocks 51 a to 53 a , respectively.
  • selector 81 a The output of selector 81 a is connected to IO line pair IOP 1 .
  • a corresponding memory cell in normal memory cell block 51 a is connected to one of the IO lines in IO line pair IOP 1 through selector 81 a .
  • a corresponding memory cell in reference row 601 is connected to the other IO line in IO line pair IOP 1 through selector 81 a.
  • selector 82 a The output of selector 82 a is connected to IO line pair IOP 2 .
  • a corresponding memory cell in normal memory cell block 52 a is connected to one of the IO lines in IO line pair IOP 2 through selector 82 a .
  • a corresponding memory cell in reference row 602 is connected to the other IO line in IO line pair IOP 2 through selector 82 a.
  • selector 83 a The output of selector 83 a is connected to IO line pair IOP 3 .
  • a corresponding memory cell in normal memory cell block 53 a is connected to one of the IO lines in IO line pair IOP 3 through selector 83 a .
  • a corresponding memory cell in reference row 603 is connected to the other IO line in IO line pair IOP 3 through selector 83 a.
  • FIG. 12 a case where the three IO line pairs and the three normal memory cell blocks are provided is shown. However, as long as the number of normal memory cell blocks is equal to that of corresponding IO line pairs, the number of normal memory cell blocks and that of IO line pairs may be larger or smaller than 3.
  • An accessed memory cell in the normal memory cell block is connected to one IO line in the corresponding IO line pair and a memory cell in the corresponding reference row is connected to the other IO line in the corresponding IO line pair.
  • Selector 84 a selects a part of spare memory cell columns 71 a to 73 a . Selector 84 a selects two out of the three spare memory cell columns in accordance with control signal RCON outputted from the CAM array and connects the selected spare memory cell columns to two IO line pairs IOP 4 and IOP 5 , respectively.
  • Each spare memory cell column is constituted so that two memory cells store data of one bit as a whole.
  • Two spare bit lines SBL are provided per spare memory cell column.
  • Selector 84 a first selects two out of the three spare memory cell columns to transmit data from these selected spare memory cell columns to spare column-dedicated IO line pairs IOP 4 and IOP 5 .
  • the selection of selector 84 a is made in accordance with control signal RCON indicating a redundancy detection result.
  • a spare bit line to be used according to an input address is connected to the spare column-dedicated IO line pair by selector 84 a.
  • selector 84 a may not be provided. In this case, the data from spare memory array 12 a is all outputted up to select section 100 . Thereby, it is unnecessary to apply the redundancy detection result to the selector section of a bit line output section, which may possibly accelerate operation rate.
  • selector 84 a is provided so as to select two out of the three spare memory cell columns when each selected memory cell column is connected to the IO line pair for the following reason. If the number of IO line pairs increases, the area of the nonvolatile semiconductor memory device disadvantageously increases by as much as the increased number of provided IO line pairs.
  • memory cells are connected to a total of five line pairs.
  • Five IO line pairs IOP 1 to IOP 5 are connected to selection and amplification section 40 .
  • Select and amplification section 40 includes select section 100 which selects three out of five line pairs IOP 1 to IOP 5 in accordance with control signal RCON, and sense amplifiers 101 to 103 for reading the data of the memory cells connected to the IO line pairs selected by select section 100 .
  • the number of sense amplifiers is set 3 equal to that of data necessary to be outputted to terminals 111 to 113 .
  • IO line pair to which a defective memory cell detected by the CAM array is connected and the IO line pair connected to an unnecessary spare bit line are not connected to sense amplifiers 101 to 103 .
  • Sense amplifiers 101 to 103 are connected to the memory cells which store data corresponding to inputted addresses through the corresponding IO line pairs.
  • sense amplifiers 101 to 103 are normal memory cells, sense amplifiers 101 to 103 are also connected to a reference memory cell which is present in the corresponding reference memory cell column and compare current values carried to the two memory cells.
  • sense amplifiers 101 to 103 compare the values of currents carried to the two complementary memory cells.
  • each spare memory cell column two memory cells store data of one bit as a whole, dedicated IO line pairs for reading data from the spare memory cells are provided, and the spare memory cells are selected depending on which IO line pairs are connected to the sense amplifiers which detect current on the connected IO line pairs.
  • FIG. 13 is a circuit diagram for describing memory array 10 a and spare memory array 12 a described with reference to FIG. 12 in more detail.
  • Normal memory cell block 51 a includes memory cells 611 , 612 , 614 and 615 .
  • Reference row 601 provided adjacent to normal memory cell block 51 a includes memory cells 613 and 616 .
  • Write drivers 630 and 631 and a selector 651 are provided to correspond to normal memory cell block 51 a and reference row 601 .
  • Write driver 630 includes transistors 681 to 684 .
  • Write driver 631 includes transistors 691 to 694 .
  • the driver is denoted by reference symbol W 1 which becomes conductive when data “1” is written.
  • the driver is denoted by reference symbol W 0 which becomes conductive when data “0” is written.
  • Two data read word lines are alternately connected to the memory cells in one row. Namely, a word line WL 1 A is connected to a memory cell 611 and a word line WL 1 B is connected to a memory cell 614 . Likewise, a word line WL 2 A is connected to a memory cell 612 and a word line WL 2 B is connected to a memory cell 615 . It is noted that a data write digit line WDL 1 is provided to be common to each memory cell row. Namely, memory cells 611 and 614 are connected to digit line WDL 1 and memory cells 612 and 615 are connected to digit line WDL 2 .
  • One word line is provided in each reference row. Namely, a word line WL 3 is connected to a memory cell 616 and a word line WL 4 is connected to a memory cell 613 .
  • Data of memory cells 611 and 612 is read by detecting a current carried from a bit line BLAa to each source line. At this moment, the data of each of memory cells 611 and 612 is compared with that of reference memory cell 616 . Due to this, a signal READA is activated to make transistors 666 , 667 and 668 conductive. If digit line driver 655 selects a row, memory cell 611 or 612 is selected. At this moment, digit line driver 656 selects word line WL 3 . As a result, a current is carried to amplification section 104 through gate circuits 771 and 772 included in selector 651 , IO line pair IOP 1 and select section 100 .
  • a signal READAB is activated to thereby make transistors 661 , 662 and 663 conductive.
  • digit line driver 655 activates word lines WL 1 B or WL 2 B.
  • digit line driver 656 activates word line WL 4 and selects memory cell 613 .
  • Spare memory cell column 71 a includes spare memory cells 617 to 620 .
  • Spare memory cell column 72 a includes spare memory cells 621 to 624 .
  • a write driver 641 is provided to correspond to spare memory cell column 71 a .
  • Write driver 641 includes transistors 701 to 704 .
  • a write driver 642 is provided to correspond to spare memory cell column 72 a .
  • Write driver 642 includes transistors 705 to 708 . Among transistors 701 to 708 , if the transistor becomes conductive when data “0” is written, the transistor is denoted by reference symbol W 0 . If the transistor becomes conductive when data “1” is written, the transistor is denoted by reference symbol W 1 .
  • spare memory cells 617 and 619 store data of one bit as one pair.
  • Spare memory cells 618 and 620 store data of one bit as one pair.
  • spare memory cell column 72 a two memory cells store data of one bit as a pair.
  • data is read from memory cells 611 and 612 , data is read from spare memory cell column 71 a in parallel to the read of data from memory cells 611 and 612 . Namely, if memory cell 611 is selected in response to the activation of word line WL 1 A, then spare memory cells 617 and 619 are selected and data is read from spare memory cells 617 and 619 by amplification section 104 through selector 84 a , IO line pairs and select section 100 .
  • digit lines are provided to be common to the normal memory cells and spare memory cells. Two word lines are alternately connected to the normal memory cells in one row.
  • the reference rows it is possible to employ the reference memory cell connected to the bit line adjacent the bit line to which the selected normal memory cell is connected. Therefore, the read path becomes equal between the normal memory cells and the reference memory cells, thereby making it difficult to cause a data read error.
  • phase-changing memory has been proposed as a nonvolatile semiconductor memory device.
  • the phase-changing memory is also referred to as “OUM (Ovonic Unified Memory)”.
  • FIG. 14 is a plan view showing the shapes of memory cells in the phase-changing memory.
  • FIG. 15 is a cross-sectional view taken along line A-A of FIG. 14.
  • a word line 801 is formed of an n-type impurity region on a P-type substrate 806 and a p-type impurity region 805 is formed above word line 801 .
  • Substrate 806 , word line 801 and impurity region 805 form a vertical PNP type parasitic bipolar transistor.
  • a heater element 804 is formed above p-type impurity region 805 , a chalcogenide layer 803 is formed above heater element 804 and a bit line 802 is formed above chalcogenide layer 803 .
  • Chalcogenide is germanium-selenium-tellurium alloy. Even a small amount of chalcogenide can be transformed between an amorphous state and a crystal state by heating the chalcogenide by a resistor. The resistance of chalcogenide is high in an amorphous state and low in a crystal state.
  • FIG. 16 is an equivalent circuit diagram of the memory cell array shown in FIG. 14.
  • a memory cell 810 includes a chalcogenide layer 811 and a PNP type bipolar transistor 812 .
  • a memory cell is selected by a word line 801 and a current is carried from a bit line 802 to a collector line 807 of the selected memory cell.
  • the quantity of emitted heat of a heater electrode provided in contact with chalcogenide layer 811 is controlled to make it possible to transform the state of chalcogenide layer 811 between a crystal state and an amorphous state.
  • FIG. 17 is a circuit diagram showing a case where the present invention is applied to the phase-changing memory.
  • memory cells MC arranged in a matrix are provided in a normal memory cell block 51 b .
  • a reference cell column 61 b which holds a reference value when data is read from normal memory cell block 51 b is provided adjacent to normal memory cell block 51 b .
  • Two memory cells store data of one bit as a whole in a spare memory cell column 71 b .
  • Spare memory cells SMCA and SMCB hold complementary values to each other. As a result, a spare memory cell does not require a reference memory cell and the reliability of the spare memory cell becomes higher than that of a normal memory cell.
  • Word lines WL 1 to WL 4 are provided to be common to normal memory cell block 51 b , reference cell column 61 b and spare memory cell column 71 b .
  • Word lines WL 1 to WL 4 are driven by word line drivers 851 to 854 , respectively.
  • Word line drivers 851 to 854 are selectively activated by a word line decoder 850 in accordance with an address signal.
  • Bit lines BLA, BLB, SBLA and SBLB are driven by a write driver 861 during data write.
  • Write driver 861 includes transistors 871 to 878 .
  • Write driver decoder 860 changes the potentials of bit lines and driving time according to write information so as to change the phase of the chalcogenide layer of each memory cell.
  • a corresponding bit line is selected by decoder 880 and a read gate 862 and one of gate circuits 886 and 887 is connected to one of IO lines in an IO line pair.
  • signal CSLA is selected by a decoder gate 881 , signal SREFA is activated and a reference memory cell is connected to the other IO line in the IO line pair by a gate circuit 888 .
  • bit line BLB is connected to one IO pair in the IO line pair by gate circuit 887 .
  • signal SREFB is activated to make gate circuit 889 conductive and bit line BLR is connected to the other IO line in the IO line pair.
  • bit lines and IO line pairs are alternately connected to one another. Due to this, reference bit line BLR is also connected to one of the IO line in the IO line pair to correspond to the selected normal memory cell column.
  • spare memory cell columns are constituted so that two memory cells store data of one bit as a whole, opposite pieces of data are written simultaneously to the two memory cells selected by the same word line.
  • FIG. 17 typically shows one memory cell column 71 b .
  • a selector 84 b selects two out of the three spare memory cell columns and the selected spare memory cell column is connected to spare column-dedicated IO line pairs IOP 4 and IOP 5 .
  • an accessed memory cell is compared with a memory cell in reference cell column 61 b to thereby read data. If a word line is activated, decoder 880 and read gate 862 select the bit line to which the accessed memory cell is connected. The selected bit line is also connected to IO line pair IOP 1 . A precharge current is carried to the bit line and the selected memory cell through the IO line pair and the state of a sense amplifier changes according to the resistance value of the selected memory cell. The memory cell in reference cell column 61 b is simultaneously selected by the same word line as that for the accessed memory cell. Bit lines for the both memory cells are connected to amplification section 104 and the state of the accessed memory cell and that of the reference memory cell are compared with each other.
  • the spare memory cell column is constituted to store data of one bit by two memory cells as a whole, it does not require a reference memory cell. In this way, by constituting the redundancy section to hold and store complementary data of one bit in two memory cells, it is possible to operate the spare memory cell array more stably even if there is a variation in finished dimensions of elements between the access memory cells and the reference memory cells.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
US10/357,411 2002-08-22 2003-02-04 Nonvolatile semiconductor memory device having improved redundancy relieving rate Abandoned US20040037112A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/145,980 US7061800B2 (en) 2002-08-22 2005-06-07 Nonvolatile semiconductor memory device having improved redundancy relieving rate
US11/409,121 US7277330B2 (en) 2002-08-22 2006-04-24 Nonvolatile semiconductor memory device having improved redundancy relieving rate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002-241808(P) 2002-08-22
JP2002241808A JP2004079138A (ja) 2002-08-22 2002-08-22 不揮発性半導体記憶装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/145,980 Division US7061800B2 (en) 2002-08-22 2005-06-07 Nonvolatile semiconductor memory device having improved redundancy relieving rate

Publications (1)

Publication Number Publication Date
US20040037112A1 true US20040037112A1 (en) 2004-02-26

Family

ID=31884564

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/357,411 Abandoned US20040037112A1 (en) 2002-08-22 2003-02-04 Nonvolatile semiconductor memory device having improved redundancy relieving rate
US11/145,980 Expired - Fee Related US7061800B2 (en) 2002-08-22 2005-06-07 Nonvolatile semiconductor memory device having improved redundancy relieving rate
US11/409,121 Expired - Fee Related US7277330B2 (en) 2002-08-22 2006-04-24 Nonvolatile semiconductor memory device having improved redundancy relieving rate

Family Applications After (2)

Application Number Title Priority Date Filing Date
US11/145,980 Expired - Fee Related US7061800B2 (en) 2002-08-22 2005-06-07 Nonvolatile semiconductor memory device having improved redundancy relieving rate
US11/409,121 Expired - Fee Related US7277330B2 (en) 2002-08-22 2006-04-24 Nonvolatile semiconductor memory device having improved redundancy relieving rate

Country Status (4)

Country Link
US (3) US20040037112A1 (ja)
JP (1) JP2004079138A (ja)
CN (1) CN100338686C (ja)
TW (1) TWI277093B (ja)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040233711A1 (en) * 2003-05-21 2004-11-25 Tsuneo Inaba Magnetic memory device
US20040252544A1 (en) * 2003-06-11 2004-12-16 Tyler Lowrey Die customization using programmable resistance memory elements
US20050024933A1 (en) * 2003-05-07 2005-02-03 Stmicroelectronics S.R.L. Process for manufacturing device having selector transistors for storage elements and memory device fabricated thereby
US20050213401A1 (en) * 2004-03-23 2005-09-29 Yuui Shimizu Semiconductor integrated circuit device
US20050219920A1 (en) * 2004-03-30 2005-10-06 Nec Electronics Corporation Semiconductor memory and method for manufacturing the same
US20060023524A1 (en) * 2004-07-14 2006-02-02 Nec Electronics Corporation Nonvolatile semiconductor memory and method for setting replacement information in nonvolatile semiconductor memory
US20070223696A1 (en) * 2004-11-08 2007-09-27 Junko Furuyama Secure Device and Relay Terminal
US20070242501A1 (en) * 2006-04-18 2007-10-18 Industrial Technology Research Institute Structure and access method for magnetic memory cell and circuit of magnetic memory
US20090313424A1 (en) * 2008-06-13 2009-12-17 Em Microelectronics-Marin S.A. Memory device and method for secure readout of protected data
US7836364B1 (en) * 2006-05-30 2010-11-16 Marvell International Ltd. Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions
US20120155157A1 (en) * 2010-12-20 2012-06-21 Hynix Semiconductor Inc. Magnetic random access memory apparatus, methods for programming and verifying reference cells therefor
US20190294374A1 (en) * 2018-03-26 2019-09-26 SK Hynix Inc. Memory system including memory device and memory controller, and operating method thereof
US11062788B2 (en) * 2017-03-17 2021-07-13 Industry-University Cooperation Foundation Hanyang University STT-MRAM failed address bypass circuit and STT-MRAM device including same
US20220261624A1 (en) * 2017-11-29 2022-08-18 Anaflash Inc. Neural network circuits having non-volatile synapse arrays
WO2023071144A1 (zh) * 2021-10-29 2023-05-04 长鑫存储技术有限公司 存储器结构以及存储器

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004063023A (ja) * 2002-07-30 2004-02-26 Renesas Technology Corp 半導体記憶装置
JP4689973B2 (ja) * 2004-06-09 2011-06-01 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7209383B2 (en) * 2004-06-16 2007-04-24 Stmicroelectronics, Inc. Magnetic random access memory array having bit/word lines for shared write select and read operations
US7372728B2 (en) * 2004-06-16 2008-05-13 Stmicroelectronics, Inc. Magnetic random access memory array having bit/word lines for shared write select and read operations
JP2006049780A (ja) * 2004-08-09 2006-02-16 Elpida Memory Inc 半導体集積回路装置
JP2006210718A (ja) 2005-01-28 2006-08-10 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US7324366B2 (en) * 2006-04-21 2008-01-29 International Business Machines Corporation Non-volatile memory architecture employing bipolar programmable resistance storage elements
JP2007299485A (ja) * 2006-05-01 2007-11-15 Toshiba Corp 半導体メモリ
DE102006028483B4 (de) * 2006-06-21 2010-04-08 Qimonda Ag Verfahren zum Zugreifen auf einen Speicher
US7996710B2 (en) * 2007-04-25 2011-08-09 Hewlett-Packard Development Company, L.P. Defect management for a semiconductor memory system
TWI404076B (zh) * 2008-01-07 2013-08-01 Powerchip Technology Corp 記憶體裝置以及資料讀取方法
US7897954B2 (en) * 2008-10-10 2011-03-01 Macronix International Co., Ltd. Dielectric-sandwiched pillar memory device
JP2010225236A (ja) * 2009-03-24 2010-10-07 Toshiba Corp 半導体記憶装置
KR101057724B1 (ko) * 2009-05-13 2011-08-18 주식회사 하이닉스반도체 반도체 메모리 장치와 그의 구동 방법
JP5359798B2 (ja) * 2009-11-10 2013-12-04 ソニー株式会社 メモリデバイスおよびその読み出し方法
CN101833992B (zh) * 2010-05-11 2013-03-13 中国科学院上海微系统与信息技术研究所 具有冗余存储单元的相变随机存储器系统
US8755215B2 (en) * 2012-07-31 2014-06-17 SK Hynix Inc. Resistive memory device
US9343162B2 (en) * 2013-10-11 2016-05-17 Winbond Electronics Corporation Protection against side-channel attacks on non-volatile memory
US10366774B2 (en) * 2016-09-27 2019-07-30 Spin Memory, Inc. Device with dynamic redundancy registers
JP6886850B2 (ja) * 2017-04-04 2021-06-16 ラピスセミコンダクタ株式会社 半導体記憶装置および半導体記憶装置の試験方法
US11282558B2 (en) * 2020-05-21 2022-03-22 Wuxi Petabyte Technologies Co., Ltd. Ferroelectric random-access memory with ROMFUSE area having redundant configuration wordlines

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0498679A (ja) * 1990-08-16 1992-03-31 Nec Ic Microcomput Syst Ltd 半導体メモリ
US5469388A (en) * 1992-11-23 1995-11-21 Samsung Electronics Co., Ltd. Row redundancy circuit suitable for high density semiconductor memory devices
US5892718A (en) * 1996-09-20 1999-04-06 Nec Corporation Semiconductor memory device having a redundancy function
US5978290A (en) * 1997-08-11 1999-11-02 Nec Corporation Semiconductor memory device
US6304498B1 (en) * 1999-12-27 2001-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of suppressing degradation in operation speed after replacement with redundant memory cell
US20030099130A1 (en) * 2001-11-27 2003-05-29 Mitsubishi Denki Kabushiki Kaisha Thin film magnetic memory device having a redundant structure
US6639854B2 (en) * 2001-05-25 2003-10-28 Hynix Semiconductor Inc. Redundancy circuit of semiconductor memory device
US6661700B2 (en) * 2001-07-18 2003-12-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3023321B2 (ja) 1997-03-10 2000-03-21 株式会社東芝 不揮発性半導体記憶装置
TW548653B (en) * 1999-01-26 2003-08-21 Nec Electronics Corp Semiconductor memory device having redundancy memory circuit
JP4191355B2 (ja) * 2000-02-10 2008-12-03 株式会社ルネサステクノロジ 半導体集積回路装置
US6292383B1 (en) * 2000-04-27 2001-09-18 Stmicroelectronics, Inc. Redundant memory cell for dynamic random access memories having twisted bit line architectures
JP3594891B2 (ja) * 2000-09-12 2004-12-02 沖電気工業株式会社 半導体記憶装置およびその検査方法
JP2002279794A (ja) * 2001-03-21 2002-09-27 Mitsubishi Electric Corp 半導体記憶装置
JP2003022687A (ja) * 2001-07-09 2003-01-24 Mitsubishi Electric Corp 半導体記憶装置
JP2004103179A (ja) * 2002-09-12 2004-04-02 Renesas Technology Corp 薄膜磁性体記憶装置およびその製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0498679A (ja) * 1990-08-16 1992-03-31 Nec Ic Microcomput Syst Ltd 半導体メモリ
US5469388A (en) * 1992-11-23 1995-11-21 Samsung Electronics Co., Ltd. Row redundancy circuit suitable for high density semiconductor memory devices
US5892718A (en) * 1996-09-20 1999-04-06 Nec Corporation Semiconductor memory device having a redundancy function
US5978290A (en) * 1997-08-11 1999-11-02 Nec Corporation Semiconductor memory device
US6304498B1 (en) * 1999-12-27 2001-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of suppressing degradation in operation speed after replacement with redundant memory cell
US6639854B2 (en) * 2001-05-25 2003-10-28 Hynix Semiconductor Inc. Redundancy circuit of semiconductor memory device
US6661700B2 (en) * 2001-07-18 2003-12-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US20030099130A1 (en) * 2001-11-27 2003-05-29 Mitsubishi Denki Kabushiki Kaisha Thin film magnetic memory device having a redundant structure

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050024933A1 (en) * 2003-05-07 2005-02-03 Stmicroelectronics S.R.L. Process for manufacturing device having selector transistors for storage elements and memory device fabricated thereby
US6894923B2 (en) * 2003-05-21 2005-05-17 Kabushiki Kaisha Toshiba Magnetic memory device
US20050146926A1 (en) * 2003-05-21 2005-07-07 Tsuneo Inaba Magnetic memory device
US20040233711A1 (en) * 2003-05-21 2004-11-25 Tsuneo Inaba Magnetic memory device
US7110285B2 (en) 2003-05-21 2006-09-19 Kabushiki Kaisha Toshiba Magnetic memory device
US6987688B2 (en) * 2003-06-11 2006-01-17 Ovonyx, Inc. Die customization using programmable resistance memory elements
US20040252544A1 (en) * 2003-06-11 2004-12-16 Tyler Lowrey Die customization using programmable resistance memory elements
US20050213401A1 (en) * 2004-03-23 2005-09-29 Yuui Shimizu Semiconductor integrated circuit device
US7095649B2 (en) * 2004-03-23 2006-08-22 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US7319628B2 (en) * 2004-03-30 2008-01-15 Nec Electronics Corporation Semiconductor memory and method for manufacturing the same
US20050219920A1 (en) * 2004-03-30 2005-10-06 Nec Electronics Corporation Semiconductor memory and method for manufacturing the same
US20060023524A1 (en) * 2004-07-14 2006-02-02 Nec Electronics Corporation Nonvolatile semiconductor memory and method for setting replacement information in nonvolatile semiconductor memory
US7453727B2 (en) * 2004-07-14 2008-11-18 Nec Electronics Corporation Nonvolatile semiconductor memory and method for setting replacement information in nonvolatile semiconductor memory
US20070223696A1 (en) * 2004-11-08 2007-09-27 Junko Furuyama Secure Device and Relay Terminal
US8184810B2 (en) * 2004-11-08 2012-05-22 Panasonic Corporation Secure device and relay terminal
US20070242501A1 (en) * 2006-04-18 2007-10-18 Industrial Technology Research Institute Structure and access method for magnetic memory cell and circuit of magnetic memory
US7515458B2 (en) * 2006-04-18 2009-04-07 Industrial Technology Research Institute Structure and access method for magnetic memory cell and circuit of magnetic memory
US8495442B1 (en) 2006-05-30 2013-07-23 Marvell International Ltd. Circuits, architectures, apparatuses, systems, algorithms, software and firmware for using reserved cells to indicate defect positions
US7836364B1 (en) * 2006-05-30 2010-11-16 Marvell International Ltd. Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions
US8117510B1 (en) 2006-05-30 2012-02-14 Marvell International Ltd. Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions
US8745453B1 (en) 2006-05-30 2014-06-03 Marvell International Ltd. Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions
US8266484B1 (en) 2006-05-30 2012-09-11 Marvell International Ltd. Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions
US20090313424A1 (en) * 2008-06-13 2009-12-17 Em Microelectronics-Marin S.A. Memory device and method for secure readout of protected data
US8644056B2 (en) * 2010-12-20 2014-02-04 SK Hynix Inc. Magnetic random access memory apparatus, methods for programming and verifying reference cells therefor
US20140140127A1 (en) * 2010-12-20 2014-05-22 SK Hynix Inc. Magnetic random access memory apparatus, methods for programming and verifying reference cells therefor
US20120155157A1 (en) * 2010-12-20 2012-06-21 Hynix Semiconductor Inc. Magnetic random access memory apparatus, methods for programming and verifying reference cells therefor
US8842467B2 (en) * 2010-12-20 2014-09-23 SK Hynix Inc. Magnetic random access memory apparatus, methods for programming and verifying reference cells therefor
US11062788B2 (en) * 2017-03-17 2021-07-13 Industry-University Cooperation Foundation Hanyang University STT-MRAM failed address bypass circuit and STT-MRAM device including same
US20220261624A1 (en) * 2017-11-29 2022-08-18 Anaflash Inc. Neural network circuits having non-volatile synapse arrays
US11663457B2 (en) * 2017-11-29 2023-05-30 Anaflash Inc. Neural network circuits having non-volatile synapse arrays
US20190294374A1 (en) * 2018-03-26 2019-09-26 SK Hynix Inc. Memory system including memory device and memory controller, and operating method thereof
US10802759B2 (en) * 2018-03-26 2020-10-13 SK Hynix Inc. Memory system including memory device and memory controller, and operating method thereof
WO2023071144A1 (zh) * 2021-10-29 2023-05-04 长鑫存储技术有限公司 存储器结构以及存储器

Also Published As

Publication number Publication date
US20050270829A1 (en) 2005-12-08
US7277330B2 (en) 2007-10-02
US20060187723A1 (en) 2006-08-24
US7061800B2 (en) 2006-06-13
TW200403671A (en) 2004-03-01
CN100338686C (zh) 2007-09-19
JP2004079138A (ja) 2004-03-11
TWI277093B (en) 2007-03-21
CN1477645A (zh) 2004-02-25

Similar Documents

Publication Publication Date Title
US7277330B2 (en) Nonvolatile semiconductor memory device having improved redundancy relieving rate
KR101004910B1 (ko) 개선된 판독 및 기록 마진을 갖는 전류 구동되고 스위칭된자기 저장 셀들 및 이 셀들을 이용하는 자기 메모리들
US6791869B2 (en) Nonvolatile memory device with configuration switching the number of memory cells used for one-bit data storage
US7110290B2 (en) Thin film magnetic memory device storing program information efficiently and stably
KR100418160B1 (ko) 전기 저항치 변화에 따라 데이터를 기억하는 데이터 판독마진이 큰 기억 장치
US8189363B2 (en) Resistance change memory
US7126845B2 (en) Memory device capable of performing high speed reading while realizing redundancy replacement
US7170776B2 (en) Non-volatile memory device conducting comparison operation
US20070109840A1 (en) Memory write circuit
US20040008556A1 (en) Memory device reading data according to difference in electrical resistance between selected memory cell and reference cell
US20040047204A1 (en) High density magnetic random access memory
US6215707B1 (en) Charge conserving write method and system for an MRAM
JP2003017665A (ja) 薄膜磁性体記憶装置
KR101402205B1 (ko) 비휘발성 메모리의 계층적 교차 어레이
JP4084084B2 (ja) 薄膜磁性体記憶装置
US6778434B2 (en) Magnetic random access memory device with a reduced number of interconnections for selection of address
US6903965B2 (en) Thin film magnetic memory device permitting high precision data read
US7471549B2 (en) Semiconductor memory device
JP4388008B2 (ja) 半導体記憶装置
US6819585B2 (en) Magnetic random access memory
US9767863B2 (en) Redundancy memory device comprising a plurality of selecting circuits
JP2005032336A (ja) 半導体装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OOISHI, TSUKASA;REEL/FRAME:013726/0963

Effective date: 20030109

AS Assignment

Owner name: RENESAS TECHNOLOGY CORP., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:014502/0289

Effective date: 20030908

AS Assignment

Owner name: RENESAS TECHNOLOGY CORP., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:015185/0122

Effective date: 20030908

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION