US20040001151A1 - Electronic camera - Google Patents

Electronic camera Download PDF

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Publication number
US20040001151A1
US20040001151A1 US10/359,598 US35959803A US2004001151A1 US 20040001151 A1 US20040001151 A1 US 20040001151A1 US 35959803 A US35959803 A US 35959803A US 2004001151 A1 US2004001151 A1 US 2004001151A1
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United States
Prior art keywords
image
circuit
instruction
image processing
processing
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Abandoned
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US10/359,598
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English (en)
Inventor
Tsutomu Wakabayashi
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Nikon Corp
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Nikon Corp
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Assigned to NIKON CORPORATION reassignment NIKON CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WAKABAYASHI, TSUTOMU
Publication of US20040001151A1 publication Critical patent/US20040001151A1/en
Priority to US11/987,778 priority Critical patent/US7649553B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/667—Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes

Definitions

  • the present invention relates to an electronic camera that records image data obtained through an image capturing operation executed at an image-capturing element or the like.
  • a white balance (hereafter referred to as WB) adjustment through which a color adjustment is achieved by varying the reference for the color temperature adjustment on image data obtained by capturing an image is executed in an electronic camera.
  • WB white balance
  • image data obtained by capturing an image be recorded into a recording medium such as a memory card without undergoing image processing.
  • the WB adjustment Since the WB adjustment is part of the image processing, the WB adjustment, too, will be skipped if the image processing is skipped. Thus, if the setting for WB bracketing and the setting for skipping the image processing are both selected, two conflicting operations, i.e., an operation for recording data having undergone image processing and an operation for recording data that have not undergone image processing, are executed. If the two types of data, i.e., the data before and after image processing, are both recorded, storage space in the recording medium is quickly consumed.
  • the present invention provides an electronic camera that can selectively record either image data which have not undergone image processing or image data having undergone image processing.
  • the image-capturing device comprises: an image-capturing element that captures a subject image and outputs image data; an image processing circuit that executes image processing on the image data output by the image-capturing element; a recording circuit that records the image data that have not undergone the image processing or image data having undergone the image processing into a recording medium; a first instruction circuit that issues a first instruction for the image processing circuit and the recording circuit to change a parameter for the image processing in stages and records a plurality of sets of image data obtained through image processing executed by using a plurality of parameters resulting from the change made in stages; a second instruction circuit that issues a second instruction for the image processing circuit and the recording circuit to record the image data output from the image-capturing element without executing the image processing; and a switching circuit that alternatively switches to the first instruction and the second instruction.
  • the image processing may include white balance adjustment processing; and the first instruction may be an instruction for setting white balance bracketing.
  • the switching circuit may make a selection by giving priority to the first instruction over the second instruction.
  • the switching circuit may make a selection by giving priority to the second instruction over the first instruction.
  • the switching circuit may make a selection by giving priority to either the first instruction or the second instruction that has been issued earlier.
  • the switching circuit may make a selection by giving priority to either the first instruction or the second instruction that is issued later.
  • the image-capturing device comprises: an image-capturing element that captures a subject image and outputs image data; an image processing circuit that executes image processing on the image data output by the image-capturing element; a recording circuit that records the image data that have not undergone the image processing or image data having undergone the image processing into a recording medium; a first instruction circuit that issues a first instruction for the image processing circuit and the recording circuit to change a parameter for the image processing in stages and records a plurality of sets of image data obtained through image processing executed by using a plurality of parameters resulting from the change made in stages; a second instruction circuit that issues a second instruction for the image processing circuit and the recording circuit to record the image data output from the image-capturing element without executing the image processing; and a control circuit that controls the recording circuit to selectively record either the image data before the image processing or the image data after the image processing if both the first instruction and the second instruction are issued.
  • the image processing may include white balance adjustment processing; and the first instruction may be an instruction for setting white balance bracketing.
  • the switching circuit may make a selection by giving priority to the first instruction over the second instruction.
  • the switching circuit may make a selection by giving priority to the second instruction over the first instruction.
  • the switching circuit may make a selection by giving priority to either the first instruction or the second instruction that has been issued earlier.
  • the switching circuit may make a selection by giving priority to either the first instruction or the second instruction that is issued later.
  • FIG. 1 is a block diagram showing the structure of the electronic camera according to a first embodiment of the present invention
  • FIG. 2 presents a flowchart of the camera operation processing executed in the arithmetic operation circuit of the electronic camera
  • FIG. 3 presents a flowchart of the camera operation processing executed in the arithmetic operation circuit of the electronic camera
  • FIG. 4 presents a flowchart of the setting processing
  • FIG. 5 presents a flowchart of the display processing
  • FIG. 6 presents a flowchart of the setting processing executed in a second embodiment
  • FIG. 7 presents a flowchart of the setting processing executed in a third embodiment
  • FIG. 8 presents a flowchart of the setting processing executed in a fourth embodiment
  • FIG. 9 presents a flowchart of the setting processing executed in a fifth embodiment
  • FIG. 10 presents a flowchart of the setting processing executed in a sixth embodiment
  • FIG. 11 presents a flowchart of the setting processing executed in a seventh embodiment
  • FIG. 12 presents a flowchart of the setting processing executed in an eighth embodiment
  • FIG. 13 presents a flowchart of the setting processing executed in a ninth embodiment
  • FIG. 14 presents a flowchart of the setting processing executed in a tenth embodiment
  • FIG. 15 presents a flowchart of the setting processing executed in an eleventh embodiment.
  • FIG. 16 presents a flowchart of the setting processing executed in a twelfth embodiment.
  • FIG. 1 is a block diagram showing the structure adopted in the electronic camera according to the first embodiment of the present invention.
  • an image-capturing element 121 which may be a CCD, outputs image signals by capturing a subject image.
  • An A/D conversion circuit 122 converts the analog image signals input from the image-capturing element 121 to digital signals.
  • An image processing circuit 123 constituted of an ASIC or the like executes image processing such as a white balance (WB) adjustment on the digital image signals, compression processing for compressing image data obtained through the image processing into a predetermined format, decompression processing for decompressing compressed data and the like.
  • WB white balance
  • a timing circuit 124 generates a timing signal and outputs a drive signal to the image-capturing element 121 and the A/D conversion circuit 122 .
  • a buffer memory 125 is a memory in which image data to undergo various types of processing such as image processing, compression processing and decompression processing are temporarily stored. Image data having undergone compression processing are recorded into a recording medium 126 which may be a memory card detachably mounted in the electronic camera.
  • An arithmetic operation circuit 101 executes various arithmetic operations including a range-finding calculation for the electronic camera and an apex calculation during a photometering operation and also implements control on the camera operation sequence.
  • a photometering device 102 detects the brightness of the subject and outputs a detection signal to the arithmetic operation circuit 101 .
  • a focal point detection device 103 detects the state of the focusing position adjustment achieved through the photographic lens (not shown) and outputs a detection signal to the arithmetic operation circuit 101 .
  • a lens drive device 104 drives the focus lens constituting the photographic lens (not shown) to move it forward or backward along the optical axis in response to a command issued by the arithmetic operation circuit 101 , and thus adjusts the focusing position of the photographic lens.
  • a display device 112 displays information indicating the details of the settings selected for the electronic camera in the form of characters and icons. Photographing information including the shutter speed and the aperture is also displayed at the display device 112 .
  • a WB bracketing setting operation member 113 which may be constituted of, for instance, a dial switch, alternately outputs operation signals for setting/clearing the WB bracketing in response to a rotating operation of the dial.
  • the WB bracketing is selected so that a plurality of images resulting from WB adjustment executed at various WB adjustment values are obtained by changing the reference for the color temperature adjustment on image data obtained through an image capturing operation and thus varying the WB adjustment value in stages.
  • three sets of image data are obtained by changing the WB adjustment value in three stages.
  • three WB adjustments are executed on the image data output from the image-capturing element 121 .
  • the WB adjustment value may be varied by, for instance, adjusting the mired value.
  • An image quality mode selection operation member 114 which may be constituted of, for instance, a dial switch, issues one of the following instructions to the image processing circuit 123 in response to a rotating operation of the dial. Namely, it issues an instruction for the image processing circuit 123 , indicating whether or not the image processing is to be executed and also indicating the compression rate to be set for the compression processing, so as to adjust the image recording quality at which the image data are to be recorded into the recording medium 126 .
  • the image recording quality may be set at one of the following five levels, for instance.
  • a shutter drive circuit 105 implements control so that the front curtain and the rear curtain (not shown) of a shutter 106 are individually held/released.
  • An aperture position detection device 110 detects the aperture position corresponding to the aperture value and outputs a detection signal to the arithmetic operation circuit 101 .
  • An aperture holding device 111 stops the aperture being driven and holds the aperture at a specific aperture value.
  • a motor drive circuit 107 controls the drive of a sequence motor 108 in response to a command issued by the arithmetic operation circuit 101 .
  • the sequence motor 108 which constitutes a sequence drive device (not shown), moves a mirror (not shown) up/down, drives the aperture (not shown) and charges the shutter 106 .
  • a sequence switch 109 which constitutes the sequence drive device mentioned above, generates brake control timing and the like for the sequence motor 108 .
  • a shutter release switch 115 which is constituted of a shutter release button, outputs a release operation signal to the arithmetic operation circuit 101 .
  • the first embodiment is characterized in that; (1) if the image recording quality 1, i.e. “RAW”, is selected while the WB bracketing is set at the electronic camera, the WB bracketing is cleared and (2) setting and clearing of the WB bracketing are prohibited while the image recording quality at the electronic camera is set at image recording quality 1, i.e. “RAW”.
  • step S 1 in FIG. 2 the arithmetic operation circuit 101 selects the following initial settings. Namely, it sets 0 for a WB bracketing flag S, 2 for an image quality mode parameter Q and 1 for a bracketing recording number parameter n, and then the operation proceeds to step S 2 .
  • the WB bracketing flag S is set to 1 when the WB bracketing is selected, and is set to 0 when the WB bracketing is cleared.
  • the image quality mode parameter Q is set to one of five different values 5-1 in correspondence to the selected image recording quality 1-5.
  • the image recording quality is set to “NORMAL”.
  • the bracketing recording number parameter n indicates specifically which image among the plurality of images to be obtained through a plurality of image processing operations (WB adjustment processing operations) in the WB bracketing is undergoing image processing. Since the image processing is executed three times at varying WB adjustment values in the WB bracketing, this parameter n assumes one of the values, 1, 2 and 3 in the embodiment.
  • step S 2 the arithmetic operation circuit 101 executes setting processing and then the operation proceeds to step S 3 .
  • the setting processing is to be explained in detail later.
  • step S 3 the arithmetic operation circuit 101 executes a photometering operation to calculate the subject brightness by using the detection signal input from the photometering device 102 and then the operation proceeds to step S 4 .
  • step S 4 the arithmetic operation circuit 101 executes a specific type of exposure calculation processing and then the operation proceeds to step S 5 .
  • step S 5 the arithmetic operation circuit 101 executes display processing and then the operation proceeds to step S 6 .
  • the display processing is to be explained in detail later.
  • step S 6 the arithmetic operation circuit 101 issues a command for the focal point detection device 103 to detect the state of the focusing position adjustment achieved by the photographic lens (not shown) and then the operation proceeds to step S 7 .
  • step S 7 the arithmetic operation circuit 101 calculates the drive quantity for the focus lens based upon the results of the detection executed by the focal point detection device 103 , before the operation proceeds to step S 8 .
  • step S 8 the arithmetic operation circuit 101 issues a command for the lens drive circuit 104 to drive the focus lens to the focus-matching position and then the operation proceeds to step S 9 .
  • step S 9 the arithmetic operation circuit 101 makes a decision as to whether or not the shutter release switch 115 has been operated.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 9 if an operation signal has been input from the shutter release switch 115 to proceed to step S 10 , whereas it makes a negative decision in step S 9 if no operation signal has been input from the shutter release switch 115 to return to step S 2 .
  • step S 10 the arithmetic operation circuit 101 outputs a command for the shutter drive circuit 105 to supply power to magnets (not shown) at the shutter 106 to hold the front curtain and the rear curtain.
  • step S 11 the arithmetic operation circuit 101 outputs a command for the motor drive circuit 107 to start a forward rotation of the sequence motor 108 , before the operation proceeds to step S 12 .
  • the mirror (not shown) starts traveling upward and the aperture starts to adjust.
  • step S 12 the arithmetic operation circuit 101 counts the number of pulses Pk indicated in the detection signal input from the aperture position detection device 110 and makes a decision as to whether or not a relationship expressed as Pk ⁇ Pc is achieved between the pulse count Pk and the number of pulses Pc corresponding to a control aperture value AVc.
  • the control aperture AVc used in this step is obtained through the exposure calculation processing executed in step S 4 .
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 12 if the relationship Pk ⁇ Pc is achieved to proceed to step S 13 , whereas it makes a negative decision in step S 12 if the relationship Pk ⁇ Pc is not achieved. If a negative decision is made, the aperture is continuously adjusted and the decision making processing in step S 12 is repeatedly executed.
  • step S 13 the arithmetic operation circuit 101 outputs a command for the aperture holding device 111 to retain the aperture and then the operation proceeds to step S 14 .
  • step S 14 the arithmetic operation circuit 101 makes a decision as to whether or not the mirror-up operation has been completed.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 14 if an ON signal has been input from the sequence switch 109 to proceed to step S 15 , whereas it makes a negative decision in step S 14 if no ON signal has been input from the sequence switch 109 . If a negative decision is made in the step, the mirror-up operation is continuously executed and the decision making processing in step S 14 is repeatedly executed.
  • step S 15 the arithmetic operation circuit 101 outputs a command for the motor drive circuit 107 to stop the forward rotation of the sequence motor 108 and then the operation proceeds to step S 16 .
  • the sequence drive device (not shown) is configured by ensuring that the aperture becomes completely retained by the aperture holding device 111 before the mirror-up operation ends.
  • step S 16 the arithmetic operation circuit 101 starts a count of a time length ts before the operation proceeds to step S 17 .
  • the initial value of ts is 0.
  • step S 17 the arithmetic operation circuit 101 outputs a command for the shutter drive circuit 105 to stop the power supply to a magnet (not shown) at the shutter 106 to release the hold on the front curtain and then the operation proceeds to step S 18 .
  • the shutter front curtain starts a run.
  • step S 18 the arithmetic operation circuit 101 engages the timing circuit 104 to start generating a drive signal, thereby starting drive of the image-capturing element 121 and then the operation proceeds to step S 19 .
  • the image-capturing element 121 starts storing electrical charges in conformance to the intensity of the subject light entering its image capturing surface.
  • step S 19 the arithmetic operation circuit 101 makes a decision as to whether or not a relationship expressed as ts ⁇ Tc is achieved between the time count ts and a control shutter speed time Tc.
  • the control shutter speed time Tc is obtained through the exposure calculation processing executed in step S 4 .
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 19 if the relationship ts ⁇ Tc is achieved to proceed to step S 20 , whereas it makes a negative decision in step S 19 if the relationship ts ⁇ Tc is not achieved to repeat the decision making processing.
  • step S 20 the arithmetic operation circuit 101 outputs a command for the shutter drive circuit 105 to stop the power supply to a magnet (not shown) at the shutter 106 to release the hold on the rear curtain before the operation proceeds to step S 21 .
  • the shutter rear curtain starts a run, thereby blocking the subject light that would otherwise enter the image-capturing element 121 .
  • step S 21 the arithmetic operation circuit 101 allows a predetermined length of wait time to elapse and then the operation proceeds to step S 22 .
  • This wait time is set to the length of time required by the rear curtain to completely shield the image capturing area of the image-capturing element 121 from light and to complete its run.
  • the image capturing operation is continuously performed at the image-capturing element 121 .
  • step S 22 the arithmetic operation circuit 101 stops the count of the time length ts and stops the drive of the image-capturing element 121 by the timing circuit 124 before the operation proceeds to step S 23 . As a result, the image-capturing element 121 ends the charge storage operation.
  • step S 23 the arithmetic operation circuit 101 outputs a command for the motor drive circuit 107 to start a reverse rotation of the sequence motor 108 and then the operation proceeds to step S 24 .
  • the mirror (not shown) starts to move downward and an aperture reset to the open position starts.
  • step S 24 the arithmetic operation circuit 101 outputs a command for the timing circuit 124 to start reading out image signals from the image-capturing element 121 , and then the operation proceeds to step S 25 in FIG. 3.
  • the image signals constituted of the stored electrical charges are output from the image-capturing element 121 , and the image signals thus output are then converted to digital data at the A/D conversion circuit 122 .
  • step S 25 in FIG. 3 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode perimeter Q is set to 5.
  • the image recording quality 1 described earlier i.e., “RAW” at which image data are directly recorded without undergoing image processing, is currently selected.
  • the arithmetic operation circuit 101 makes a negative decision in step S 25 if parameter Q ⁇ 5 to proceed to step S 26 .
  • one of the image recording quality settings 2-5, at which image data having undergone image processing are recorded, is currently selected.
  • step S 26 the arithmetic operation circuit 101 makes a decision as to whether or not the bracketing recording number parameter n is set to 1.
  • the operation proceeds to step S 27 if the image processing to be executed is for the first image being produced through the WB bracketing or if the WB bracketing has been cleared.
  • step S 38 if the image processing to be executed is for the second or third image being produced through the WB bracketing.
  • step S 27 the arithmetic operation circuit 101 provides the digital image signals to the image processing circuit 123 and issues an instruction for the image processing before the operation proceeds to step S 28 .
  • step S 28 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 4.
  • the operation proceeds to step S 30 if the image recording quality 2, i.e., “TIFF” at which the image data are recorded without undergoing the compression processing, is currently selected.
  • step S 29 if one of the image recording quality settings 3-5, at which compressed image data are recorded, is currently selected.
  • step S 29 the arithmetic operation circuit 101 issues an instruction for the image processing circuit 123 to execute compression processing before the operation proceeds to step S 30 .
  • step S 30 the arithmetic operation circuit 101 records the image data into the recording medium 126 and then the operation proceeds to step S 31 .
  • step S 31 the arithmetic operation circuit 101 makes a decision as to whether or not the bracketing recording number parameter n is set to 1.
  • the image processing to be executed is for the first image being produced through the WB bracketing or if the WB bracketing has been cleared.
  • the image processing to be executed is for the second or third image being produced through the WB bracketing.
  • step S 32 the arithmetic operation circuit 101 makes a decision as to whether or not the mirror-down operation has been completed.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 32 if an ON signal has been input from the sequence switch 109 to proceed to step S 33 , whereas it makes a negative decision in step S 32 if no ON signal has been input from the sequence switch 109 to repeat the decision making processing in step S 32 .
  • step S 33 the arithmetic operation circuit 101 outputs a command for the motor drive circuit 107 to stop the reverse rotation of the sequence motor 108 and then the operation proceeds to step S 34 .
  • step S 34 the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing flag S is set to 1.
  • the operation returns to step S 2 if the sequence of the photographing processing has been completed.
  • step S 35 the arithmetic operation circuit 101 makes a decision as to whether or not the bracketing recording number parameter n is set to 3.
  • the operation proceeds to step S 36 if the image processing for the three images produced through the WB bracketing has been completed.
  • step S 36 the arithmetic operation circuit 101 sets 1 for the bracketing recording number parameter n, before the operation returns to step S 2 in FIG. 2.
  • the sequence of photographing processing ends.
  • step S 37 if the image processing to be executed is for the second or third image being produced through the WB bracketing.
  • step S 37 the arithmetic operation circuit 101 adds 1 to the value of the bracketing recording number parameter n and then the operation proceeds to step S 38 .
  • step S 38 the arithmetic operation circuit 101 makes a decision as to whether or not the bracketing recording number parameter n is set to 2.
  • the image processing to be executed is for the second image produced through the WB bracketing.
  • step S 39 the arithmetic operation circuit 101 outputs a command for the image processing circuit 123 to execute image processing by adjusting the mired value by a predetermined extent along the—direction relative to the reference value and then the operation returns to step S 28 .
  • the image processing is executed at a lowered WB reference color temperature.
  • step S 38 the arithmetic operation circuit 101 makes a negative decision in step S 38 to proceed to step S 40 .
  • the image processing to be executed is for the third image being produced through the WB bracketing.
  • step S 40 the arithmetic operation circuit 101 outputs a command for the image processing circuit 123 to execute image processing by adjusting the mired value by a predetermined extent along the+direction relative to the reference value and then the operation returns to step S 28 .
  • the image processing is executed at a raised WB reference color temperature.
  • step S 101 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode selection operation member 114 has been operated.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 101 if an operation signal has been input from the image quality mode selection operation member 114 to proceed to step S 102 , whereas it makes a negative decision in step S 101 if no operation signal has been input to proceed to step S 111 .
  • step S 102 the arithmetic operation circuit 101 makes a decision as to whether or not the operation signal indicates an operation for raising the image recording quality.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 102 if the signal input from the image quality mode setting operation member 114 indicates an upward rotation to proceed to step S 103 , whereas it makes a negative decision in step S 102 if the input signal does not indicate an upward rotation to proceed to step S 108 .
  • the upward rotation may be, for instance, a clockwise rotation.
  • step S 103 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 5.
  • step S 104 the arithmetic operation circuit 101 adds 1 to the value of Q before the operation proceeds to step S 105 . As a result, the image recording quality is raised by one stage.
  • step S 108 the arithmetic operation circuit 101 makes a decision as to whether or not the operation signal indicates an operation for lowering the image recording quality.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 108 if the signal input from the image quality setting operation member 114 indicates a downward rotation to proceed to step S 109 , whereas it makes a negative decision in step S 108 if the input signal does not indicate a downward rotation to proceed to step S 105 .
  • the downward rotation may be, for instance, a counter-clockwise rotation.
  • step S 109 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 1.
  • step S 110 the arithmetic operation circuit 101 subtracts 1 from the value of Q before the operation proceeds to step S 105 . As a result, the image recording quality is lowered by one stage.
  • step S 105 the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing flag S is set to 1.
  • step S 106 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 5.
  • step S 107 the arithmetic operation circuit 101 clears the WB bracketing and sets 0 for the WB bracketing flag S before ending the processing shown in FIG. 4 and proceeding to step S 3 in FIG. 2.
  • the image recording quality 1, i.e., “RAW” is selected while the electronic camera is set at for the WB bracketing, the WB bracketing is automatically cleared.
  • step S 111 to which the operation proceeds after making a negative decision in step S 101 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 5.
  • the arithmetic operation circuit 101 makes a negative decision in step S 111 if Q ⁇ 5 to proceed to step S 112 .
  • step S 112 the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing setting operation member 113 has been operated.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 112 if an operation signal has been input from the WB bracketing setting operation member 113 to proceed to step S 113 , whereas it makes a negative decision in step S 112 if no operation signal has been input to end the processing shown in FIG. 4 and proceed to step S 3 in FIG. 2.
  • step S 113 the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing flag 3 is set to 0.
  • step S 114 the arithmetic operation circuit 101 sets the WB bracketing and also sets 1 for the WB bracketing flag S, before the processing shown in FIG. 4 ends and the operation proceeds to step S 3 in FIG. 2.
  • step S 115 the arithmetic operation circuit 101 clears the WB bracketing and also sets 0 for the WB bracketing flag S, before the processing shown in FIG. 4 ends and the operation proceeds to step S 3 in FIG. 2.
  • the image recording quality 1 i.e. “RAW”
  • step S 201 the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing flag S is set to 1.
  • step S 202 the arithmetic operation circuit 101 engages the display device 112 to display values indicating the shutter speed and the aperture value, an icon indicating the image quality mode (image recording quality), an icon indicating that WB bracketing is on and the like, before the processing shown in FIG. 5 ends and the operation proceeds to step S 6 in FIG. 2.
  • step S 203 the arithmetic operation circuit 101 engages the display device 112 to display the values indicating the shutter speed and the aperture value, and an icon indicating the image quality mode (image recording quality), before the processing shown in FIG. 5 ends and the operation proceeds to step S 6 in FIG. 2.
  • step S 106 If the image recording quality 1, i.e., “RAW”, is selected (if an affirmative decision is made in step S 106 ) while the WB bracketing is currently set at the electronic camera (when an affirmative decision is made in step S 105 ), the WB bracketing is cleared (step S 107 ).
  • the operation during which the image processing is executed (WB bracketing) or the operation during which no image processing is executed (the image recording quality 1 “RAW”) is selectively performed and thus, a conflict of the two operations does not occur. Consequently, the image data before the image processing and the plurality of sets of image data obtained by executing the image processing through the WB bracketing are not recorded into the recording medium 126 together, to ensure that the recording medium 126 does not become used up quickly.
  • FIG. 6 presents a detailed flowchart of the setting processing executed in the second embodiment in place of the processing executed in the first embodiment, as shown in FIG. 4.
  • step S 301 and S 302 are executed between step S 103 and step S 104 and also in that additional steps S 303 and S 304 are executed following step S 114 .
  • steps S 105 ⁇ S 107 and step S 111 in the processing shown in FIG. 4 are eliminated. It is to be noted that the same step numbers are assigned to steps in which processing identical to that shown in FIG. 4 is executed to preclude the necessity for a repeated explanation thereof.
  • step S 301 the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing flag S is set to 1.
  • step S 302 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 4.
  • the WB bracketing is set at the electronic camera, an operation for switching from the image recording quality 2, i.e., “TIFF” to the image recording quality 1, i.e., “RAW” is disabled.
  • Q ⁇ 4 the arithmetic operation circuit 101 makes a negative decision in step S 302 to proceed to step S 104 . In this case, the image recording quality is raised by one stage.
  • step S 303 to which the operation proceeds after setting WB bracketing in step S 114 , the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 5.
  • step S 304 the arithmetic operation circuit 101 selects the image recording quality 2, i.e., “TIFF”, and also sets 4 for the value of Q before the processing shown in FIG.
  • step S 3 in FIG. 2 if the WB bracketing is set when the current image recording quality set at the electronic camera is the image recording quality 1 “RAW”, the image recording quality 1 “RAW” is automatically switched to the image recording quality 2 “TIFF”.
  • step S 114 If the WB bracketing is set at the electronic camera (step S 114 ) when the current image recording quality setting is the image recording quality 1 “RAW” (when an affirmative decision is made in step S 303 ), the image recording quality 1 “RAW” is switched to the image recording quality 2 “TIFF” (step S 304 ).
  • the image recording quality 1 “RAW” is switched to the image recording quality 2 “TIFF” (step S 304 ).
  • FIG. 7 presents a detailed flowchart of the setting processing executed in the third embodiment in place of the processing executed in the first embodiment, as shown in FIG. 4.
  • FIG. 7 differs from that shown in FIG. 4 in that additional steps S 301 and S 302 are executed between step S 103 and step S 104 and that steps S 105 -S 107 are eliminated. Processing identical to that executed in the additional steps in the second embodiment, as shown in FIG. 6, is executed in step S 301 and step S 302 . It is to be noted that the same step numbers are assigned to steps in which processing identical to that shown in FIG. 4 is executed to preclude the necessity for a repeated explanation thereof.
  • the operation for switching from the image recording quality 2, i.e., “TIFF”, to the image recording quality 1, i.e., “RAW”, is prohibited (an affirmative decision is made in step S 302 and the processing shown in FIG. 7 ends) if the WB bracketing is set at the electronic camera (if an affirmative decision is made in step S 301 ), whereas the operation for setting and clearing the WB bracketing is prohibited (the processing shown in FIG. 7 ends) if the current image recording quality set at the electronic camera is the image recording quality 1 “RAW” (if an affirmative decision is made in step S 111 ).
  • the operation during which the image processing is executed (WB bracketing) or the processing during which no image processing is executed (the image recording quality 1 “RAW”) is selectively performed, thereby preventing a conflict of these operations. Consequently, since the image data before the image processing and the image data after the image processing are not recorded into the recording medium 126 together, the recording medium 126 does not become used up quickly, as in the first embodiment. Furthermore, since the setting is not changed from the image recording quality 1 “RAW” to the image recording quality 2 “TIFF” or from the WB bracketing ON to WB bracketing OFF until the photographer performs a setting change, no change in settings that does not reflect the photographer's wishes occurs.
  • FIG. 8 presents a detailed flowchart of the setting processing executed in the fourth embodiment in place of the processing executed in the first embodiment, as shown in FIG. 4.
  • step S 501 ⁇ S 503 are executed instead of steps S 105 -S 107 and in that step S 111 is eliminated.
  • the operation proceeds to step S 501 after ending the processing in step S 114 or step S 115 .
  • step numbers are assigned to steps in which processing identical to that shown in FIG. 4 is executed to preclude the necessity for a repeated explanation thereof.
  • step S 501 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 5.
  • step S 502 the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing flag S is set to 1.
  • step S 503 the arithmetic operation circuit 101 clears the WB bracketing and also sets 0 for the WB bracketing flag S before the processing shown in FIG. 8 ends and the operation proceeds to step S 3 in FIG. 2.
  • the arithmetic operation circuit 101 clears the WB bracketing and also sets 0 for the WB bracketing flag S before the processing shown in FIG. 8 ends and the operation proceeds to step S 3 in FIG. 2.
  • step S 114 The WB bracketing set at the electronic camera (step S 114 ) is invalidated (step S 503 ) if the current image recording quality setting is the image recording quality 1 “RAW” (if an affirmative decision is made in step S 501 ), and thus, a conflict of the operation during which the image processing is executed (WB bracketing) and the operation during which no image processing is executed (the image recording quality 1 “RAW”) is prevented.
  • the image data before the image processing and the image data after the image processing are not recorded into the recording medium 126 together and the recording medium 126 does not become used up quickly, as in the first embodiment.
  • step S 502 If the WB bracketing is set (if an affirmative decision is made in step S 502 ) when the current image recording quality set at the electronic camera is the image recording quality 1 “RAW” (an affirmative decision is made in step S 501 ), the WB bracketing is cleared up (step S 503 ).
  • the operation during which the image processing is executed (WB bracketing) or the operation during which no image processing is executed (the image recording quality 1 “RAW”) is selectively performed, thereby preventing a conflict of these operations.
  • the image data before the image processing and the image data after the image processing are not recorded into the recording medium 126 together and the image recording medium 126 does not become used up quickly, as in the first embodiment.
  • FIG. 9 presents a detailed flowchart of the setting processing executed in the fifth embodiment in place of the processing executed in the first embodiment, as shown in FIG. 4.
  • step S 601 The processing shown in FIG. 9 differs from that shown in FIG. 4 in that steps S 601 -S 603 are executed instead of steps S 105 -S 107 and in that step S 111 is eliminated.
  • the operation proceeds to step S 601 after ending the processing in step S 114 or step S 115 .
  • step S 601 the same step numbers are assigned to steps in which processing identical to that shown in FIG. 4 is executed to preclude the necessity for a repeated explanation thereof. 5
  • step S 601 the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing flag S is set to 1.
  • step S 602 the arithmetic operation circuit 101 makes a decision as to whether or not the image quality mode parameter Q is set to 5.
  • step S 603 the arithmetic operation circuit 101 sets the image recording quality 2, i.e., “TIFF”, and also sets 4 for the value of Q before the processing shown in FIG. 9 ends and the operation proceeds to step S 3 in FIG. 2.
  • the photographer attempts to set both the image recording quality 1 “RAW” and the WB bracketing for the electronic camera, an automatic switch is made from the image recording quality 1 “RAW” to the image recording quality 2 “TIFF”.
  • the image recording quality setting 1 “RAW” set for the electronic camera (an affirmative decision is made in step S 103 ) is invalidated (step S 603 ) if the WB bracketing is set at the electronic camera (if an affirmative decision is made in step S 601 ) and, as a result, a conflict of the operation during which the image processing is executed (WB bracketing) and the operation during which no image processing is executed (the image recording quality 1 “RAW”) is prevented. Consequently, the image data before the image processing and the image data after the image processing are not recorded into the recording medium 126 together and the recording medium 126 does not become used up quickly, as in the first embodiment.
  • step S 114 If the WB bracketing is selected for the electronic camera (step S 114 ) when the current image recording quality set at the electronic camera is the image recording quality 1 “RAW”, (if an affirmative decision is made in step S 602 ), the image recording quality 1 “RAW” is switched to the image recording quality 2 “TIFF” (step S 603 ), and thus, either the operation during which the image processing is executed (WB bracketing) or the operation during which no image processing is executed (the image recording quality 1 “RAW”) is selectively performed to prevent a conflict of these operations. Consequently, the image data before the image processing and the image data after the image processing are not recorded into the recording medium 126 together and the recording medium 126 does not become used up quickly, as in the first embodiment.
  • FIG. 10 presents a flowchart of a variation of the setting processing executed in the first embodiment described earlier.
  • the same step numbers are assigned to steps in which processing identical to that shown in FIG. 4 is executed to preclude the necessity for a repeated explanation thereof.
  • An explanation of step S 303 and step S 304 is also omitted, since processing identical to that executed in steps S 303 and S 304 in FIG. 6 is executed in these steps.
  • the setting is switched from the image recording quality 1 “RAW” to the image recording quality 2 “TIFF”. Instead, the setting may be switched from the image recording quality 1 “RAW” to the image recording quality 3 “FINE”, the image recording quality 4 “NORMAL” or the image recording quality 5 “BASIC”.
  • This principle applies to the processing executed in steps S 303 and S 304 in FIG. 6 and the processing in steps S 602 and S 603 in FIG. 9.
  • FIG. 11 presents a flowchart of a variation of the setting processing shown in FIG. 10. It differs from the processing shown in FIG. 10 in that additional steps S 1051 and S 1052 are executed and, accordingly, the following explanation focuses on the difference.
  • step S 1051 to which the operation proceeds after step S 107 the arithmetic operation circuit 101 engages the display device 112 to blink the display segment such as an icon indicating the WB bracketing ON setting over a predetermined length of time and then to turn off the display when the predetermined length of time elapses.
  • the predetermined length of time is set in advance to 10 seconds or less, for instance, so as to ensure that the photographer does not miss the blinking display.
  • step S 1052 to which the operation proceeds after step S 304 , the arithmetic operation circuit 101 engages the display device 112 to blink the display segment such as an icon indicating the image recording quality 1 “RAW” over a predetermined length of time and then to turn on the display segment such as an icon indicating the image recording quality 2 “TIFF” when the blinking display ends.
  • the arithmetic operation circuit 101 ends the processing shown in FIG. 11 once the processing in step S 1052 is completed. It is to be noted that the display segment which is set in a steady ON state after the blinking display ends in step S 1052 corresponds to the image recording quality to which the switch is made from the image recording quality 1 “RAW”.
  • step S 1051 when clearing the setting for either the WB bracketing or the image recording quality 1 “RAW” that has been selected earlier, the display segment corresponding to the setting to be cleared blinks over a predetermined length of time (step S 1051 , step S 1052 ). Thus, a warning is provided to alert the photographer to the setting change.
  • FIG. 12 presents a flowchart of a variation of the setting processing shown in FIG. 4. It differs from the processing shown in FIG. 4 in that additional steps S 1001 and S 1002 are executed and, accordingly, the following explanation focuses on the difference.
  • step S 1001 to which the operation proceeds after step S 107 the arithmetic operation circuit 101 engages the display device 112 to blink the display segment such as an icon indicating the WB bracketing ON setting over a predetermined length of time and then to turn off the display when the predetermined length of time elapses.
  • the arithmetic operation circuit 101 ends the processing shown in FIG. 12.
  • step S 1002 to which the operation proceeds after making an affirmative decision in step S 111 , the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing setting operation member 113 has been operated.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 1002 if an operation signal has been input from the WB bracketing setting operation member 113 to proceed to step S 1001 , whereas it makes a negative decision in step S 1002 if no operation signal has been input to end the processing shown in FIG. 12.
  • step S 107 the display segment such as an icon indicating the WB bracketing ON setting blinks over the predetermined length of time (step S 1001 ).
  • step S 1001 the operation for setting and clearing the WB bracketing is prohibited (the processing shown in FIG. 12 ends) when the current image recording quality set at the electronic camera is the image recording quality 1 “RAW” (when an affirmative decision is made in step S 111 ).
  • the display segment such as an icon indicating the WB bracketing ON setting is made to blink over the predetermined length of time (step S 1001 ).
  • a warning is provided to alert the photographer to a setting change or to notify the photographer that an operation for changing the setting status is prohibited.
  • FIG. 13 presents a flowchart of a variation of the setting processing shown in FIG. 6. It differs from the processing shown in FIG. 6 in that an additional step S 1011 is executed and, accordingly, the following explanation focuses on the difference.
  • step S 1011 the arithmetic operation circuit 101 engages the display device 112 to blink the display segment such as an icon indicating the image recording quality 1 “RAW” over a predetermined length of time and then to turn on the display segment such as an icon indicating the image recording quality 2 “TIFF” when the blinking display ends.
  • the arithmetic operation circuit 101 ends the processing shown in FIG. 13 once the processing in step S 1011 is completed. It is to be noted that the display segment which is set in a steady ON state after the blinking display ends in step S 1011 corresponds to the image recording quality that is actually selected.
  • the arithmetic operation circuit 101 also proceeds to step S 1011 after ending the processing in step S 304 .
  • step S 114 if the WB bracketing is set (step S 114 ) for the electronic camera at which the image recording quality 1 “RAW” is currently set (an affirmative decision is made in step S 303 ), the setting is switched from the image recording quality 1 “RAW” to the image recording quality 2 “TIFF” (step S 304 ). At this time, the display segment such as an icon indicating the image recording quality 1 “RAW” is made to blink at the display device 112 over the predetermined length of time (step S 1011 ).
  • step S 301 the operation for switching the image quality setting to the image recording quality 1 “RAW” is prohibited (an affirmative decision is made in step S 302 ).
  • the display segment such as an icon indicating the image recording quality 1 “RAW” is made it to blink over the predetermined lens of time (step S 1011 ).
  • a warning is provided to alert the photographer to the setting change or to notify the photographer that an operation for switching the setting is prohibited.
  • FIG. 14 presents a flowchart of a variation of the setting processing shown in FIG. 7. It differs from the processing shown in FIG. 7 in that additional steps S 1021 -S 1023 are executed and, accordingly, the following explanation focuses on the difference.
  • step S 1021 the arithmetic operation circuit 101 engages the display device 112 to blink the display segment such as an icon indicating the image recording quality 1 “RAW” over a predetermined length of time and then to turn on the display segment such as an icon indicating the image recording quality 2 “TIFF” when the blinking display ends.
  • the arithmetic operation circuit 101 ends the processing shown in FIG. 14 once the processing in step S 1021 is completed. It is to be noted that the display segment which is set in a steady ON state after the blinking display ends in step S 1021 corresponds to the image recording quality that is actually selected.
  • step S 1022 to which the operation proceeds after making an affirmative decision in step S 111 , the arithmetic operation circuit 101 makes a decision as to whether or not the WB bracketing setting operation member 113 has been operated.
  • the arithmetic operation circuit 101 makes an affirmative decision in step S 1022 if an operation signal has been input from the WB bracketing setting operation member 113 to proceed to step S 1023 , whereas it makes a negative decision in step S 1022 if no operation signal has been input to end the processing shown in FIG. 14.
  • step S 1023 the arithmetic operation circuit 101 engages the display device 112 to blink the display segment such as an icon indicating the WB bracketing ON setting over a predetermined length of time and then to turn off the display when the predetermined length of time elapses.
  • the arithmetic operation circuit 101 ends the processing shown in FIG. 14.
  • the operation for switching the image quality setting to the image recording quality 1 “RAW” is prohibited (an affirmative decision is made in step S 302 ) if the electronic camera is currently set for the WB bracketing (if an affirmative decision is made in step S 301 ).
  • the display segment such as an icon indicating the image recording quality 1 “RAW” is made to blink over the predetermined length of time at the display device 112 (step S 1021 ).
  • the operation for setting and clearing the WB bracketing is prohibited (the processing shown in FIG. 14 ends).
  • the display segment such as an icon indicating the WB bracketing ON setting is made to blink over the predetermined length of time (step S 1023 ).
  • a warning is provided to notify the photographer that an operation for switching the setting is prohibited.
  • FIG. 15 presents a flowchart of a variation of the setting processing shown in FIG. 8. It differs from the processing shown in FIG. 8 in that an additional step S 1031 is executed and, accordingly, the following explanation focuses on the difference.
  • step S 1031 to which the operation proceeds after step S 503 the arithmetic operation circuit 101 engages the display device 112 to blink the display segment such as an icon indicating the WB bracketing ON setting over a predetermined length of time and then to turn off the display when the predetermined length of time elapses.
  • the arithmetic operation circuit 101 ends the processing shown in FIG. 14.
  • the WB bracketing ON setting selected (step S 114 ) for the electronic camera at which the image recording quality 1 “RAW” is already set (an affirmative decision is made in step S 501 ) is invalidated (step S 503 ).
  • the display segment such as an icon indicating the WB bracketing ON setting is made to blink over the predetermined length of time (step S 1031 ).
  • the WB bracketing is set (if an affirmative decision is made in step S 502 ) for the electronic camera at which the image recording quality 1 “RAW” is already set (an affirmative decision is made in step S 501 )
  • the WB bracketing is cleared (step S 503 ).
  • the display segment such as an icon indicating the WB bracketing ON setting is made to blink over the predetermined length of time (step S 1031 ).
  • a warning is provided to alert the photographer that the setting has been cleared.
  • FIG. 16 presents a flowchart of a variation of the setting processing shown in FIG. 9. It differs from the processing shown in FIG. 9 in that an additional step S 1041 is executed and, accordingly, the following explanation focuses on the difference.
  • step S 1041 to which the operation proceeds after step S 603 , the arithmetic operation circuit 101 engages the display device 112 to blink the display segment such as an icon indicating the image recording quality 1 “RAW” over a predetermined length of time and then turn on the display segment such as an icon indicating the image recording quality 2 “TIFF” when the blinking display ends.
  • the arithmetic operation circuit 101 ends the processing shown in FIG. 16 once the processing in step S 1041 is completed. It is to be noted that the display segment which is set in a steady ON state after the blinking display ends in step S 1041 corresponds to the image recording quality that is actually selected.
  • the image recording quality 1 “RAW” selected (an affirmative decision is made in step S 103 ) at the electronic camera for which the WB bracketing is already set (an affirmative decision is made in step S 601 ) is invalidated (step S 603 )
  • the display segment such as an icon indicating the image recording quality 1 “RAW” is made to blink at the display device 112 over the predetermined length of time (step S 1041 ).
  • step S 114 the WB bracketing is set (step S 114 ) for the electronic camera at which the image recording quality 1 “RAW” is already set (an affirmative decision is made in step S 602 )
  • the image recording quality 1 “RAW” is switched to the image recording quality 2 “TIFF” (step S 603 ).
  • the display segment such as an icon indicating the image recording quality 1 “RAW” is made to blink over the predetermined length of time (step S 1041 ).
  • a warning is provided to notify the photographer that the operation for setting the image recording quality 1 “RAW” is prohibited or to alert the photographer to a setting switch.
  • the display segment indicating the WB bracketing ON setting and the display segment indicating the image recording quality may both be made to blink over a predetermined length of time. Since the display segments corresponding to the two relevant settings are both made to blink, the photographer is able to ascertain with ease the specific setting which is invalidated by the other setting selection in this case.
  • the WB bracketing ON setting and the image recording quality 1 “RAW” setting may be selected at the same time and a selection may be made when recording image data into the recording medium 126 to specify whether the image data having undergone the WB adjustment through the WB bracketing are to be recorded into the recording medium 126 or the image data that have not undergone the image processing are to be recorded into the recording medium 126 at the image recording quality 1 “RAW”.
  • the recording medium 126 does not become used up quickly.
  • circuit is used in the explanation given above, as in the arithmetic operation circuit 101 and the image processing circuit 123 , the term “circuit” may be replaced with the term “device”.
  • the arithmetic operation circuit 101 and the image processing circuit 123 may be referred to as an arithmetic operation device 101 and an image processing device 123 instead.

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