US20030209760A1 - Semiconductor integrated circuit and method of fabricating the same - Google Patents

Semiconductor integrated circuit and method of fabricating the same Download PDF

Info

Publication number
US20030209760A1
US20030209760A1 US10/424,938 US42493803A US2003209760A1 US 20030209760 A1 US20030209760 A1 US 20030209760A1 US 42493803 A US42493803 A US 42493803A US 2003209760 A1 US2003209760 A1 US 2003209760A1
Authority
US
United States
Prior art keywords
forming
semiconductor layer
grooves
groove
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/424,938
Other languages
English (en)
Inventor
Shinya Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MARUYAMA, SHINYA
Publication of US20030209760A1 publication Critical patent/US20030209760A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates to a semiconductor integrated circuit which is formed in an SOI (Silicon On Insulator) layer and a method of fabricating the same, and, more particularly, to a method of forming a device isolation region without degrading the performance of a transistor.
  • SOI Silicon On Insulator
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • SOI layer a semiconductor integrated circuit including devices, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) in an SOI layer by forming a BOX (Buried Oxide) layer on a silicon substrate and forming the SOI layer on the BOX layer.
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • the SOI layer is insulated from the silicon substrate by the BOX layer. This can reduce the source-drain capacitance of transistors formed in the SOI layer, thereby improving the speed of the transistors.
  • the threshold voltage of the transistors can be decreased by increasing the voltage of a body which is formed directly under the gate electrode of each transistor. It is also possible to prevent the transistors from being influenced by a variation in the voltage of the substrate.
  • an STI Shallow Trench Isolation region is formed in the SOI layer in order to electrically isolate the individual devices from one another.
  • the STI region is formed deep so as to reach the BOX layer.
  • FIGS. 1A through 1C and FIGS. 2A through 2C are cross-sectional views illustrating a conventional method of forming a semiconductor integrated circuit step by step.
  • an SOI wafer 101 is prepared.
  • a silicon substrate 102 is provided, a BOX layer 103 is formed on the silicon substrate 102 and an SOI layer 104 is formed on the BOX layer 103 .
  • the SOI layer 104 has a thickness of, for example, 150 nm.
  • a silicon oxide film (SiO 2 film) 105 is formed on the surface of the SOI layer 104 by thermal oxidizing the SOI wafer 101 , as shown in FIG. 1B.
  • a silicon nitride film (Si 3 N 4 film) 106 is deposited on the silicon oxide film 105 , as shown in FIG. 1C.
  • a photoresist (not shown) is formed on the silicon nitride film 106 by photolithography. An opening is formed in that region of this photoresist which is reserved for the formation of an STI region in a later process.
  • the photoresist as a mask, the silicon nitride film 106 , the silicon oxide film 105 and the SOI layer 104 are selectively etched out by dry etching, thereby forming trenches 107 .
  • the trenches 107 are formed in such a way as to reach the BOX layer.
  • the SOI wafer 101 is subjected to thermal oxidation.
  • a silicon oxide film 109 is formed in that region of the inner surface of each trench 107 where the SOI layer 104 is exposed.
  • This process is called “round oxidation”.
  • the round oxidation is carried out in order to recover from a damage made on the SOI layer 104 by the aforementioned dry etching and round the shape of the trench 107 so as to prevent the formation of pointed portions which would cause concentration of an electric field in the trenches 107 .
  • a silicon oxide film is deposited on the entire surface of the resultant structure by plasma CVD (Chemical vapor Deposition). Then, that silicon oxide film, which is formed in other regions than the inside of the trenches 107 , is removed by CMP (Chemical Mechanical Polishing). Thereby, an STI region 112 , which is formed of the silicon oxide film, is formed in the trenches 107 . Then, devices, such as MOSFETs, are formed in that region in the SOI layer 104 which is defined by the STI region 112 , thereby forming a semiconductor integrated circuit.
  • plasma CVD Chemical vapor Deposition
  • CMP Chemical Mechanical Polishing
  • FIG. 3 is a more-detailed cross-sectional view showing the process in FIG. 2B in the conventional fabrication method.
  • an oxide 113 is actually formed between the BOX layer 103 and the SOI layer 104 near the trench 107 by round oxidation. This occurs as oxygen goes around to the interface between the BOX layer 103 and the SOI layer 104 from the bottom of the trench 107 .
  • a projection 114 is formed on the center portion of the bottom of the trench 107 . This occurs as oxygen penetrates the BOX layer 103 at the bottom of the trench 107 and reaches the silicon substrate 102 to oxide the surface of the silicon substrate 102 at the time round oxidation is carried out.
  • the oxide 113 and the projection 114 are not shown in FIG. 2.
  • the SOI layer 104 is bent.
  • the bending of the SOI layer 104 deforms the shape of the portion underlying the channel region of the transistor formed in the SOI layer 104 . This results in lower mobility of carriers, which degrade the characteristics of the transistor.
  • a semiconductor integrated circuit comprises a semiconductor substrate; an insulation film formed on the semiconductor substrate; and a semiconductor layer formed on the insulation film and having first grooves in which an insulator is buried and on sides of which an oxide film of the semiconductor layer is formed in such a way as not to reach the insulation film, and a second groove in which an insulator is buried, which reaches the insulation film and which is formed in a bottom of at least one of the first grooves.
  • the first grooves which do not reach the insulation film are formed in the semiconductor layer
  • the second groove which reaches the insulation film is formed in the bottom of at least one of the first grooves
  • an insulator is buried in the first and second grooves. Accordingly, an STI region which reaches the insulation film can be formed.
  • the oxide film of the semiconductor layer is formed on the sides of the first grooves, a damage made on the semiconductor layer can be recovered and the formation of pointed portions can be prevented.
  • the first grooves do not reach the insulation film it is possible to prevent oxygen from going around and entering between the insulation film and the semiconductor layer at the time of forming the oxide film of the semiconductor layer on the sides of the first grooves.
  • a method of fabricating a semiconductor integrated circuit comprises the steps of forming an insulation film on a semiconductor substrate; forming a semiconductor layer on the insulation film; forming first grooves, which do not to reach the insulation film, in a surface layer of the semiconductor layer; oxidizing inner surfaces of the first grooves in the semiconductor layer; forming a second groove, which reaches the insulation film, in a bottom of at least one of the first grooves; and forming a device isolation region by burying an insulator in the first and second grooves.
  • the first grooves are formed in such a way as not to reach the insulation film, after which the inner surfaces of the first grooves are oxidized. Thereafter, the second groove which reaches the insulation film is formed in the bottom of at least one of the first grooves.
  • the structure makes it possible to prevent oxygen from going around and entering between the insulation film and the semiconductor layer at the time of oxidizing the inner surfaces of the first grooves. This can prevent an oxide from being formed between the insulation film and the semiconductor layer. It is also possible to restrain oxygen from penetrating the insulation film and reaching the semiconductor substrate. This can suppress oxidation of the surface of the semiconductor substrate, thereby suppressing expansion of the semiconductor substrate, so that the formation of projections on the bottoms of the first grooves can be repressed. Accordingly, it is possible to prevent the semiconductor layer from being bent by the formation of the oxide film. This makes it possible to prevent the mobility of carriers in the semiconductor layer from dropping, thereby prohibiting the characteristics of transistors to be formed in the semiconductor layer from being degraded.
  • the second groove may be formed only in bottoms of some of the first grooves and may not be formed in bottoms of the remaining first grooves. This makes it possible to form the device isolation region that reaches the insulation film in said some of the first grooves and form the device isolation region that does not reach the insulation film in the remaining first grooves. That is, the device isolation region that reaches the insulation film and the device isolation region that does not reach the insulation film can be formed separately in the same process.
  • the step of forming the second groove may include the step of: forming a photoresist, having an opening at a region corresponding to the bottom of the at least one first groove, on the semiconductor layer; and etching the semiconductor layer using the photoresist as a mask to thereby selectively remove the semiconductor layer located at the bottom of the at least one first groove. Accordingly, the second groove can be formed without damaging other portions of the first grooves than the bottoms. At this time, those of the first grooves, in whose bottoms the second groove is to be formed, can be selected by forming an opening only in that area of the photoresist which corresponds to some of the first grooves. Accordingly, the device isolation region that reaches the insulation film and the device isolation region that does not reach the insulation film can be formed separately.
  • the step of forming the first grooves may include the steps of forming a first photoresist on the semiconductor layer, etching the semiconductor layer using the first photoresist as a mask to thereby selectively remove the semiconductor layer, and removing the first photoresist; and the step of forming the second groove may include the steps of forming a second photoresist patterned in a same pattern as the first photoresist, and etching the semiconductor layer using the second photoresist as a mask to thereby selectively remove the semiconductor layer located at the bottom of the at least one first groove. This can allow the first photoresist and the second photoresist to be formed using the same mask, and can thus contribute to reducing the fabrication cost for a semiconductor integrated circuit.
  • the step of forming the second groove may include the steps of forming side walls covering sides of the at least one first groove, and etching the semiconductor layer using the side walls as a mask to thereby selectively remove the semiconductor layer located at the bottom of the at least one first groove, and the step of forming the side walls may include the steps of forming a nitride film on an entire surface of the semiconductor layer, and performing etch-back of the nitride film to leave the nitride film formed on the sides of the at least one first groove and remove the nitride film formed on a region excluding the sides of the at least one first groove.
  • the first grooves are formed in such a way as not to reach the insulation film, after which the inner surfaces of the first grooves are oxidized, so that it is possible to prevent oxygen from going around and entering between the insulation film and the semiconductor layer at the time of forming the oxide film, and to restrain oxygen from penetrating the insulation film and reaching the semiconductor substrate. It is therefore possible to prohibit the formation of an oxide between the insulation film and the semiconductor layer and prohibit projections from being formed on the bottoms of the first grooves. This makes it possible to form a device isolation region without degrading the characteristics of transistors formed in the semiconductor layer.
  • FIGS. 1A through 1C are cross-sectional views illustrating the conventional method of forming a semiconductor integrated circuit step by step
  • FIGS. 2A through 2C are cross-sectional views illustrating the conventional method of forming the semiconductor integrated circuit step by step and show the next process to the process in FIG. 1C;
  • FIG. 3 is a more-detailed cross-sectional view showing the process in FIG. 2B in the conventional fabrication method
  • FIGS. 4A through 4C are step-by-step cross-sectional views illustrating a method of forming a semiconductor integrated circuit according to a first embodiment of the invention
  • FIGS. 5A through 5C are step-by-step cross-sectional views illustrating the method of forming the semiconductor integrated circuit according to the embodiment and show the next process to the process in FIG. 4C;
  • FIG. 6 is a cross-sectional view illustrating a method of forming a semiconductor integrated circuit according to a second embodiment of the invention.
  • FIGS. 7A through 7C are step-by-step cross-sectional views illustrating a method of forming a semiconductor integrated circuit according to a third embodiment of the invention.
  • FIG. 5C is a cross-sectional view illustrating a semiconductor integrated circuit according to the embodiment.
  • a BOX layer 3 is provided on a silicon substrate 2 and an SOI layer 4 is provided on the BOX layer 3 .
  • a silicon oxide film 5 and a silicon nitride film 6 are provided on the SOI layer 4 .
  • Trenches 7 which do not reach the BOX layer 3 are formed in the silicon nitride film 6 , the silicon oxide film 5 and the SOI layer 4 .
  • An STI region 12 is buried in each trench 7 and a silicon oxide film 9 is formed on the sides of the trench 7 . Further, a trench 11 which reaches the BOX layer 3 is formed in the bottom of the trench 7 , and the STI region 12 is buried in the trench 11 . The silicon oxide film 9 is not formed on the sides of the trench 11 .
  • a device (not shown), such as an MOSFET, is formed in a region in the SOI layer 4 which is defined by the STI region 12 .
  • the trench 7 and 11 are kinds of grooves.
  • FIGS. 4A through 4C and FIGS. 5A through 5C are step-by-step cross-sectional views illustrating a method of forming the semiconductor integrated circuit according to the embodiment.
  • a SOI wafer 1 which has the BOX layer 3 and the SOI layer 4 formed on the silicon substrate 2 is prepared.
  • the silicon oxide film (SiO 2 film) 5 is formed on the surface of the SOI layer 4 by thermal oxidation, and then the silicon nitride film (Si 3 N 4 film) 6 is deposited by CVD.
  • the thickness of the SOI layer 4 is, for example, 50 to 300 nm
  • the thickness of the silicon oxide film 5 is, for example, 3 to 20 nm
  • the thickness of the silicon nitride film 6 is, for example, 50 to 200 nm.
  • a photoresist 8 is formed on the silicon nitride film 6 by photolithography. Then, an opening 8 a is formed in that region of this photoresist 8 which is reserved for the formation of an STI region in a later process. With the photoresist 8 as a mask, the silicon nitride film 6 , the silicon oxide film 5 and the SOI layer 4 are selectively etched out by dry etching, thereby forming the trenches 7 .
  • CF 4 for example, is used as an etching gas under a gas pressure of, for example, 0.7 to 6.7 Pa in dry-etching the silicon nitride film 6 and the silicon oxide film 5
  • a mixed gas of Cl 2 and O 2 for example, is used as an etching gas under a gas pressure of, for example, 1 to 10 Pa in dry-etching the SOI layer 4 .
  • the dry-etching is stopped in a middle of the SOI layer 4 so that the trenches 7 do not reach the BOX layer 3 .
  • the thickness of the SOI layer 4 on the bottoms of the trenches 7 is, for example, 30 to 250 nm.
  • the photoresist 8 is removed.
  • round oxidation is executed by performing thermal oxidation on the SOI wafer 1 .
  • the thermal oxidation is carried out by placing the SOI wafer 1 in the atmosphere where, for example, the gas composition is H 2 —O 2 , the pressure is normal and the temperature is in a range of 800 to 1100° C., for 5 to 30 minutes. This oxidizes that region of the SOI layer 4 which corresponds to the bottom and sides of each trench 7 to thereby form the silicon oxide film 9 in that region.
  • the thickness of the silicon oxide film 9 is, for example, to 5 to 30 nm in both the sides and bottom of the trench 7 .
  • a photoresist 10 is formed on the silicon nitride film 6 .
  • an opening 10 a is formed in that region of the photoresist 10 which corresponds to the bottom of at least one trench 7 by photolithography. That is, the opening 10 a is formed in such a way as to be positioned inside the trench 7 as seen from a direction perpendicular to the surface of the BOX layer 3 .
  • the SOI layer 4 which is positioned on the bottom of the trench 7 is selectively etched out, thereby forming the trench 11 that reaches the BOX layer 3 .
  • this dry etching for example, HBrO 2 is used as an etching gas and the gas pressure is, for example, 0.5 to 30 Pa. Thereafter, the photoresist 10 is removed.
  • a silicon oxide film (not shown) is deposited on the entire surface of-the SOI wafer 1 by plasma CVD. At this time, the silicon oxide film is also buried inside the trenches 7 and 11 . Then, the silicon oxide film that is formed in other regions than inside the trenches 7 and 11 is removed by CMP, thereby forming the STI region 12 , comprised of a silicon oxide film, inside the trenches 7 and 11 . The bottom surface of the STI region 12 contacts the top surface of the BOX layer 3 .
  • a device, such as the MOSFET, is formed in that area of the SOI layer 4 which is defined by the STI region 12 , thereby completing a semiconductor integrated circuit.
  • round oxidation need not be performed but such may be carried out to form a silicon oxide film with a thickness of, for example, about 1 to 15 nm.
  • Cleaning may be carried out by, for example, a cleaning device (ammoniated water) made by Branson after the trench 11 is formed.
  • the opening 10 a in the photoresist 10 may be formed in-the region which corresponds to the bottoms of all the trenches 7 in the process shown in FIG. 5A, the opening 10 a may be formed only in the region which corresponds to the bottoms of some of the trenches 7 . Accordingly, it is possible to form the trenches 11 only in the bottoms of those some trenches 7 , not in the bottoms of the remaining trenches 7 , in the process shown in FIG. 5B.
  • the trenches that reach the BOX layer 3 and the trenches that do not reach the BOX-layer 3 can both be formed, so that the STI region that reaches the BOX layer 3 and the STI region that does not reach the BOX layer 3 can be formed separately in the same process.
  • the trenches 7 are formed in such a way as not to reach the BOX layer 3 in the process shown in FIG. 4B. Accordingly, oxygen does not go around and enter the interface between the BOX layer 3 and the SOI layer 4 at the time round oxidation is performed in the process shown in FIG. 4C. Therefore, the oxide 113 as shown in FIG. 3 is not produced.
  • the SOI layer 4 remains on the bottom of the trench 7 at the time of performing round oxidation, it is possible to restrain oxygen from penetrating the BOX layer 3 and reaching the silicon substrate 2 . This makes it possible to suppress the production of the oxide film 102 a as shown in FIG. 3, thereby suppressing the formation of the projections 114 . It is therefore possible to prevent the SOI layer 4 from being bent by round oxidation and thus prevent the mobility of carriers in the transistor to be formed in the SOI layer 4 from dropping. As a result, the characteristics of the transistor can be prohibited from being degraded.
  • FIG. 6 is a cross-sectional view illustrating a method of fabricating a semiconductor integrated circuit according to the embodiment.
  • the structure of the semiconductor integrated circuit according to the second embodiment is similar to the structure of the semiconductor integrated circuit according to the first embodiment.
  • a silicon oxide film 5 and a silicon nitride film 6 are formed on a SOI wafer 1 , trenches 7 are formed with a photoresist 8 used as a mask, then round oxidation is performed to oxidize the inner surfaces of the trenches 7 to form a silicon oxide film 9 through the same processes as those in the first embodiment shown in FIGS. 4A to 4 C.
  • a photoresist 15 which is patterned in the same pattern as the photoresist 8 (see FIG. 4B) is formed on the silicon nitride film 6 . That is, an opening 15 a is formed in the photoresist 15 at the same position as the opening 8 a (see FIG. 4B) formed in the photoresist 8 .
  • etching is performed. As a result, the silicon oxide film 9 and the SOI layer 4 which are positioned on the bottoms of the trenches 7 are selectively etched out, thereby forming trenches 11 .
  • CF 4 for example, is used as an etching gas under a gas pressure of, for example, 0.5 to 10 Pa in dry-etching the silicon oxide film 9
  • a mixed gas of Cl 2 and O 2 for example, is used as an etching gas under a gas pressure of, for example, 1 to 10 Pa in dry-etching the SOI layer 4 .
  • this etching that portion which is formed on the bottom of the trench 7 is selectively etched, so that those portions which are formed on the sides of the trench 7 are not completely removed by this etching. Thereafter, the photoresist 15 is removed.
  • an STI region 12 is formed by the same scheme as used in the first embodiment. Then, a device, such as an MOSFET, is formed in that area of the SOI layer 4 which is defined by the STI region 12 , thereby completing a semiconductor integrated circuit.
  • a device such as an MOSFET
  • the second embodiment has an advantage such that the photoresist 15 which is used in the second etching can be formed with the same mask as used for the photoresist 8 which is used in the first etching.
  • This advantage can allow the STI region 12 to be formed with a single mask and can thus contribute to lowering the fabrication cost for the semiconductor integrated circuit.
  • FIGS. 7A to 7 C are step-by-step cross-sectional views illustrating a method of fabricating a semiconductor integrated circuit according to the third embodiment.
  • the structure of the semiconductor integrated circuit according to this embodiment is similar to the structure of the semiconductor integrated circuit according to the first embodiment.
  • a silicon oxide film 5 and a silicon nitride film 6 are formed on a SOI wafer 1
  • trenches 7 are formed with a photoresist 8 used as a mask
  • round oxidation is performed to oxidize the inner surfaces of the trenches 7 to form a silicon oxide film 9 through the same processes as those in the first embodiment shown in FIGS. 4A to 4 C.
  • a silicon nitride film (SiN film) 16 a is deposited on the entire surface of the resultant structure by CVD.
  • the deposition conditions for the silicon nitride film 16 a are, for example, the temperature of 650 to 750° C., a source gas of NH 3 —SiH 2 Cl 2 , the pressure of 10 to 140 Pa and the film thickness of about 10 to 100 nm.
  • etch-back is carried out under the conditions that the etching gas is, for example, CF 4 and the pressure is, for example, 0.5 to 10 Pa to remove those portions of the silicon nitride film 16 a which are formed on other regions than the sides of the trenches 7 and leave the portions formed on the sides of the trenches 7 . Accordingly, side walls 16 of SiN are formed on the sides of each trench 7 . At this time, the thickness of the side walls 16 is, for example, 10 to 50 nm.
  • etching is performed under the conditions such that HBrO 2 , for example, is used as the etching gas and the pressure is, for example, 0.5 to 30 Pa.
  • This etching selectively removes the silicon oxide film 9 and the SOI layer 4 which are positioned on the bottoms of the trenches 7 to thereby form trenches 11 which reach the BOX layer 3 .
  • the side walls 16 are removed by wet etching. At this time, phosphoric acid is used as an etchant. The process of removing the side walls 16 may be omitted.
  • an STI region 12 is formed in the same scheme as used in the first embodiment. Then, a device, such as an MOSFET, is formed in that area of the SOI layer 4 which is defined by the STI region 12 , thereby completing a semiconductor integrated circuit.
  • a device such as an MOSFET
  • the photoresist (not shown) may be formed and patterned to expose some of the trenches 7 and cover the remaining trenches 7 before etching to form the trenches 11 is performed. This can allow the trenches 11 to be formed only in the bottoms of some exposed trenches 7 and prevent the trenches 11 from being formed in the bottoms of the remaining trenches 7 . As a result, the trenches that reach the BOX layer 3 and the trenches that do not reach the BOX layer 3 can both be formed, so that the STI region that reaches the BOX layer 3 and the STI region that does not reach the BOX layer 3 can be formed separately in the same process.
  • the third embodiment has an advantage such that in the second etching, a new photoresist is not formed but the side walls 16 are used as a mask. At this time, as the side walls 16 are formed on the sides of the trenches 7 , the second etching can be performed in a self-aligned manner with respect to the first etching. It is therefore possible to form a device isolation region small enough that a photoresist cannot be patterned and thus cope with the micro-fabrication of semiconductor integrated circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
US10/424,938 2002-05-10 2003-04-29 Semiconductor integrated circuit and method of fabricating the same Abandoned US20030209760A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002135186A JP2003332416A (ja) 2002-05-10 2002-05-10 半導体集積回路及びその製造方法
JP2002-135186 2002-05-10

Publications (1)

Publication Number Publication Date
US20030209760A1 true US20030209760A1 (en) 2003-11-13

Family

ID=29397485

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/424,938 Abandoned US20030209760A1 (en) 2002-05-10 2003-04-29 Semiconductor integrated circuit and method of fabricating the same

Country Status (3)

Country Link
US (1) US20030209760A1 (ja)
JP (1) JP2003332416A (ja)
TW (1) TW200401406A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050116312A1 (en) * 2003-11-28 2005-06-02 Jae-Eun Lim Semiconductor device with trench isolation structure and method for fabricating the same
WO2006124241A2 (en) * 2005-05-19 2006-11-23 Freescale Semiconductor Electronic device including a trench field isolation having combination shallow and deep depth and a process for forming the same
US20090155980A1 (en) * 2007-12-18 2009-06-18 Hill Christopher W Methods of Forming Trench Isolation and Methods of Forming Floating Gate Transistors
US7670895B2 (en) 2006-04-24 2010-03-02 Freescale Semiconductor, Inc Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
US20110117719A1 (en) * 2009-11-19 2011-05-19 Brown William R Methods of processing semiconductor substrates in forming scribe line alignment marks
US20130049162A1 (en) * 2011-08-24 2013-02-28 Semiconductor Manufacturing International (Beijing) Corporation Semiconductor device and manufacturing method thereof
US8642441B1 (en) * 2006-12-15 2014-02-04 Spansion Llc Self-aligned STI with single poly for manufacturing a flash memory device
US20150050792A1 (en) * 2013-08-13 2015-02-19 Globalfoundries Inc. Extra narrow diffusion break for 3d finfet technologies
CN104370266A (zh) * 2013-08-12 2015-02-25 上海华虹宏力半导体制造有限公司 深沟槽中感应材料的成膜方法
CN105826233A (zh) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 一种soi器件及其制备方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810409B1 (ko) * 2006-10-31 2008-03-04 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
JP5959350B2 (ja) * 2012-07-19 2016-08-02 三菱電機株式会社 半導体装置の製造方法
CN109994537B (zh) * 2017-12-29 2022-09-06 联华电子股份有限公司 半导体元件及其制作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5395789A (en) * 1993-08-06 1995-03-07 At&T Corp. Integrated circuit with self-aligned isolation
US6562694B2 (en) * 1999-12-24 2003-05-13 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5395789A (en) * 1993-08-06 1995-03-07 At&T Corp. Integrated circuit with self-aligned isolation
US6562694B2 (en) * 1999-12-24 2003-05-13 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7528052B2 (en) * 2003-11-28 2009-05-05 Hynix Semiconductor Inc. Method for fabricating semiconductor device with trench isolation structure
US7902628B2 (en) 2003-11-28 2011-03-08 Hynix Semiconductor Inc. Semiconductor device with trench isolation structure
US20050116312A1 (en) * 2003-11-28 2005-06-02 Jae-Eun Lim Semiconductor device with trench isolation structure and method for fabricating the same
WO2006124241A2 (en) * 2005-05-19 2006-11-23 Freescale Semiconductor Electronic device including a trench field isolation having combination shallow and deep depth and a process for forming the same
US20060261436A1 (en) * 2005-05-19 2006-11-23 Freescale Semiconductor, Inc. Electronic device including a trench field isolation region and a process for forming the same
WO2006124241A3 (en) * 2005-05-19 2009-05-14 Freescale Semiconductor Inc Electronic device including a trench field isolation having combination shallow and deep depth and a process for forming the same
US7670895B2 (en) 2006-04-24 2010-03-02 Freescale Semiconductor, Inc Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
US8642441B1 (en) * 2006-12-15 2014-02-04 Spansion Llc Self-aligned STI with single poly for manufacturing a flash memory device
US10622370B1 (en) 2006-12-15 2020-04-14 Monterey Research, Llc System and method for manufacturing self-aligned STI with single poly
US9276007B2 (en) 2006-12-15 2016-03-01 Cypress Semiconductor Corporation System and method for manufacturing self-aligned STI with single poly
US20090155980A1 (en) * 2007-12-18 2009-06-18 Hill Christopher W Methods of Forming Trench Isolation and Methods of Forming Floating Gate Transistors
US7846812B2 (en) 2007-12-18 2010-12-07 Micron Technology, Inc. Methods of forming trench isolation and methods of forming floating gate transistors
US8003482B2 (en) 2009-11-19 2011-08-23 Micron Technology, Inc. Methods of processing semiconductor substrates in forming scribe line alignment marks
US8673780B2 (en) 2009-11-19 2014-03-18 Micron Technology, Inc. Methods of processing semiconductor substrates in forming scribe line alignment marks
US8956976B2 (en) 2009-11-19 2015-02-17 Micron Technology, Inc. Methods of processing semiconductor substrates in forming scribe line alignment marks
US20110117719A1 (en) * 2009-11-19 2011-05-19 Brown William R Methods of processing semiconductor substrates in forming scribe line alignment marks
US8951883B2 (en) * 2011-08-24 2015-02-10 Semiconductor Manufacturing International (Beijing) Corporation Semiconductor device and manufacturing method thereof
US20130049162A1 (en) * 2011-08-24 2013-02-28 Semiconductor Manufacturing International (Beijing) Corporation Semiconductor device and manufacturing method thereof
CN104370266A (zh) * 2013-08-12 2015-02-25 上海华虹宏力半导体制造有限公司 深沟槽中感应材料的成膜方法
US20150050792A1 (en) * 2013-08-13 2015-02-19 Globalfoundries Inc. Extra narrow diffusion break for 3d finfet technologies
CN105826233A (zh) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 一种soi器件及其制备方法

Also Published As

Publication number Publication date
TW200401406A (en) 2004-01-16
JP2003332416A (ja) 2003-11-21

Similar Documents

Publication Publication Date Title
US7759215B2 (en) Semiconductor device having STI without divot and its manufacture
US7132349B2 (en) Methods of forming integrated circuits structures including epitaxial silicon layers in active regions
KR100394517B1 (ko) 집적회로에트렌치격리구조를형성하는방법
US6737706B2 (en) Silicon on insulator device having trench isolation layer and method for manufacturing the same
US7611950B2 (en) Method for forming shallow trench isolation in semiconductor device
KR19990084786A (ko) 트렌치 소자분리 방법
US5963819A (en) Method of fabricating shallow trench isolation
US20030209760A1 (en) Semiconductor integrated circuit and method of fabricating the same
US6372606B1 (en) Method of forming isolation trenches in a semiconductor device
KR100683490B1 (ko) 수직 채널을 갖는 전계 효과 트랜지스터의 제조방법
US20060008962A1 (en) Manufacturing method of semiconductor integrated circuit device
US7316979B2 (en) Method and apparatus for providing an integrated active region on silicon-on-insulator devices
KR100839894B1 (ko) 반도체 장치 및 그 제조 방법
US20040082141A1 (en) Method of fabricating a semiconductor device having trenches
KR20040059445A (ko) 반도체 소자의 트렌치형 소자분리막 형성방법
KR100734088B1 (ko) 트랜지스터의 제조방법
JP4982919B2 (ja) 半導体装置の製造方法
KR100524916B1 (ko) 반도체 집적회로의 트렌치 소자분리방법
JP3523244B1 (ja) 半導体装置の製造方法
KR100629694B1 (ko) 반도체 소자 제조 방법
JP2002100670A (ja) 半導体装置及びその製造方法
JP2000188325A (ja) 半導体装置の製造方法
KR20070106167A (ko) 반도체 소자의 제조방법
KR20060057162A (ko) 반도체 소자의 제조방법
JP2002222956A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: NEC ELECTRONICS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARUYAMA, SHINYA;REEL/FRAME:014018/0936

Effective date: 20030421

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION