US20030201536A1 - Semiconductor device and manufacturing process therefor as well as plating solution - Google Patents

Semiconductor device and manufacturing process therefor as well as plating solution Download PDF

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US20030201536A1
US20030201536A1 US10/423,077 US42307703A US2003201536A1 US 20030201536 A1 US20030201536 A1 US 20030201536A1 US 42307703 A US42307703 A US 42307703A US 2003201536 A1 US2003201536 A1 US 2003201536A1
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silver
metal region
copper
semiconductor device
interconnection
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Kazuyoshi Ueno
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NEC Electronics Corp
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NEC Electronics Corp
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Publication of US20030201536A1 publication Critical patent/US20030201536A1/en
Priority to US11/065,998 priority Critical patent/US7259095B2/en
Priority to US11/124,804 priority patent/US7821135B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to a semiconductor device comprising a silver-containing metal region and a process for manufacturing the device.
  • a copper film as a copper interconnection is usually formed by plating, which gives the copper film as an aggregate of a number of polycrystalline copper grains.
  • mass transfer occurs via a copper grain boundary, leading to electromigration.
  • a copper grain size is smaller and thus the problem of migration due to mass transfer via such a grain boundary becomes more significant.
  • Japanese Laid-open Patent Publication 2000-349085 has disclosed an interconnection made of a silver-containing copper alloy, and described that the interconnection has a silver content within a range of at least 0.1 wt % to less than its maximum solid solution limit, and if more than the maximum solid solution limit, the metal may form a compound with Cu, leading to a rupture or crack in the interconnection.
  • Japanese Laid-open Patent Publication 1999-204524 has disclosed an interconnection made of a silver-containing copper alloy and described that a silver content in the interconnection is preferably 1 wt % or less and illustrates forming an interconnection made of a copper alloy containing silver at 0.1 wt % as a specific example.
  • FIG. 2 shows a schematic cross section of a copper multilayer interconnection formed by a damascene method, where an upper interconnection 121 b is connected with a lower interconnection 121 a and the upper interconnection 121 b consists of a connecting plug and an interconnection formed thereon.
  • a void 122 is formed on the side of the upper interconnection 121 b . That is, the void is formed in a via region in the upper interconnection 121 b .
  • a void 122 is formed on the upper surface of the lower interconnection 121 a .
  • Such a void 122 may be caused by an internal stress generated in the copper interconnection due to, for example, a heat history during a semiconductor process.
  • the void 122 may be formed by upward migration of copper in the via due to copper “pull-up” in the upper interconnection 121 b .
  • copper may horizontally migrate in the lower interconnection 121 a , leading to formation of the void 122 .
  • a void thus formed may cause connection defect between a connecting plug and an interconnection, a reduced yield of a semiconductor device and instability in a semiconductor device after a long period use.
  • an objective of this invention is to improve stress migration resistance in a semiconductor device comprising a metal region, and thus to improve reliability of the device.
  • Another objective of this invention is to provide a process for consistently manufacturing such a semiconductor device.
  • This invention provides a semiconductor device comprising a metal region on a semiconductor substrate, wherein a silver content is more than 1 wt % to the total amount of component metals in the metal region.
  • This invention also provides on a semiconductor device comprising a metal region on a semiconductor substrate, wherein the metal region comprises copper and silver; and a silver content to the total amount of component metals in the metal region is more than a solid solution limit of silver to copper.
  • the metal region in the above semiconductor device a larger amount of silver than that in a conventional interconnection structure made of a copper-silver alloy, and thus can effectively prevent stress migration when being exposed to a heat history during, for example, a process for manufacturing a semiconductor.
  • This invention also provides a semiconductor device comprising a metal region on a semiconductor substrate wherein a maximum hysteresis error in a temperature-stress curve in the metal region is 150 MPa or less.
  • a temperature-stress curve for a metal region When a semiconductor device is exposed to a heat history, a temperature-stress curve for a metal region generally exhibits different patterns in a warming and a cooling processes. An indicator for the difference is defined as a “maximum hysteresis error”.
  • a maximum hysteresis error is the maximum separation width between the curves showing the warming and the cooling processes. For example, in FIG. 8, the maximum width between a warming process a and a cooling process b is a maximum hysteresis error.
  • an irreversible loss is reduced when being exposed to a heat history during a process for manufacturing a semiconductor, and thus stress migration is effectively prevented.
  • This invention further provides a semiconductor device comprising a metal region on a semiconductor substrate wherein a recrystallization temperature of a component metal in the metal region is 200° C. or higher.
  • a recrystallization temperature is a temperature at which transformation of crystal grains or grain growth occurs due to atomic diffusion. Since recrystallization may result in a void or distortion in a metal region, a higher recrystallization temperature is an important condition for providing a reliable metal region.
  • the above semiconductor device has a recrystallization temperature higher than 200° C., so that irreversible loss can be minimized when being exposed to a heat history and thus stress migration can be effectively prevented.
  • a recrystallization temperature can be determined by, for example, measuring a hysteresis curve. FIG.
  • a recrystallization temperature is 220° C.
  • the metal region may be made of a silver-containing metal with a shape of an interconnection plug or pad.
  • This invention also provides a process for manufacturing a semiconductor device comprising the steps of forming a metal region on a semiconductor substrate; contacting the surface of the metal region with a silver-containing liquid; and heating the metal region.
  • contacting the surface of the metal region with a silver-containing liquid results in precipitation of silver and then heating allows silver to diffuse in the metal region.
  • a silver-containing metal region may be suitably formed.
  • a metal region made of a copper-silver alloy may be consistently formed by a convenient process. Since a plating solution itself does not have to contain silver, the plating solution may be selected more freely.
  • This invention also provides a process for manufacturing a semiconductor device comprising the steps of contacting a semiconductor substrate or a film formed thereon with a silver-containing solution to precipitate silver; forming a metal region on the precipitated silver; and heating the metal region.
  • the precipitated silver after contacting with the silver-containing solution diffuses in a metal region formed thereon.
  • a silver-containing metal region may be suitably formed.
  • a metal region made of a copper-silver alloy may be consistently formed by a convenient process.
  • a metal composition in a metal region may be made homogeneous.
  • This invention also provides a process for manufacturing a semiconductor device comprising the steps of contacting a device-forming surface of a semiconductor substrate with a silver-containing plating solution; and forming a silver-containing metal region on the semiconductor substrate.
  • the silver-containing plating solution may be contacted with all or a part of the device-forming surface.
  • a plating solution is contacted with either of a semiconductor substrate surface, a metal film, an insulating film or a semiconductor film or a surface comprising these in any combination.
  • Contacting with a silver-containing plating solution may be conducted after forming a plating film using a silver-free plating solution.
  • the process may comprise, for example, the steps of forming a copper film such that it partially fills a concave formed in an insulating film on a semiconductor substrate; then contacting the surface of the copper film with a silver-containing plating solution to form a silver-containing film on the copper film; and then polishing the whole surface of the substrate to leave the copper film and the silver-containing film only in the concave.
  • this process may comprises the steps of forming a silver-containing film; forming a copper film on the silver-containing film; and polishing the substrate surface as described above.
  • a metal region made of a copper-silver alloy may be consistently formed by a convenient process.
  • a homogeneous metal composition may be provided in the metal region.
  • the metal region may contain copper. Furthermore, in a process for manufacturing a semiconductor device according to this invention, a silver content may be more than 1 wt % to the total amount of component metals in the metal region after heating. Thus, a metal region highly resistant to stress migration may be consistently formed.
  • a metal region in this invention is made of a copper-silver alloy
  • other components may be further added.
  • components such as Zr, In, Al, Ti and Sn may be added up to 1 wt % to the total amount of the metals.
  • Zr and/or In may be added to improve adhesiveness between the metal region and an insulating film and/or between the metal region and a barrier metal film.
  • Al, Ti and Sn may diffuse in the surface of the reactive copper-silver alloy film to be bound to the material atoms constituting the interlayer insulating film, resulting in improved adhesiveness.
  • a metal region in this invention may be formed by a single or dual damascene process.
  • a single damascene process comprises the steps of:
  • the first and the second interconnections and the whole connecting hole or a part thereof may be a “metal region” to which a semiconductor device or process according to this invention can be applied. Some of the above steps of (a) to (i) may be omitted as appropriate.
  • a dual damascene process comprises the steps of:
  • the first and the second interconnections and the whole connecting hole or a part thereof may be a “metal region” to which a semiconductor device or process according to this invention can be applied. Some of the above steps of (a) to (e) may be omitted as appropriate.
  • the interconnection structure formed by the above damascene process comprises the semiconductor substrate; the first interconnection formed on the semiconductor substrate; the connecting plug connected to the first interconnection; and the second interconnection connected to connecting plug.
  • the first and the second interconnections and the whole connecting hole or a part thereof may be a “metal region” to which this invention may be applied.
  • FIG. 1 shows a cross section illustrating an embodiment of a semiconductor device according to this invention.
  • FIG. 2 shows a cross section illustrating an interconnection structure in which a void is formed due to stress migration.
  • FIGS. 3 to 6 are process diagrams illustrating a process for manufacturing an interconnection structure shown in FIG. 1( a ).
  • FIG. 7 is a graph showing an example of a hysteresis curve.
  • FIG. 8 is a graph showing an example of a hysteresis curve.
  • FIG. 9 shows a method for determining a recrystallization temperature.
  • FIG. 10 is a drawing illustrating a principle of determination of a via chain resistance.
  • FIGS. 11 to 15 are graphs illustrating exemplary results of determination for a hysteresis curve.
  • FIG. 16 is a state diagram for an Ag—Cu two-component eutectic compound.
  • FIG. 17 shows a relationship between a silver content and an interconnection resistance.
  • 22 a is a first interconnection
  • 22 b is a second interconnection
  • 28 is a connecting plug
  • 101 is an insulating film
  • 102 is a barrier metal film
  • 103 is a copper-silver alloy film
  • 104 is an interlayer insulating film
  • 105 is an interconnection groove
  • 106 , 106 a and 106 b are barrier metal films
  • 107 is a seed metal film
  • 108 is a silver-containing film
  • 110 is a copper plating film
  • 111 is a copper-silver alloy film
  • 111 a is an interlayer connecting plug
  • 111 b is a copper-silver alloy film
  • 114 is a copper-silver alloy plating film
  • 117 is a copper plating film
  • 121 a is a lower interconnection
  • 121 b is an upper interconnection
  • 122 is a void.
  • FIG. 1 is a schematic cross section illustrating an embodiment of semiconductor device according to this invention.
  • FIG. 1( a ) shows an embodiment in which this invention is applied to a copper multilayer interconnection structure formed by a so-called dual damascene process.
  • a lower interconnection is formed, which consists of a barrier metal film 102 and a copper-silver alloy film 103 .
  • an interlayer insulating film 104 is formed on the insulating film, in which an upper interconnection consisting of a barrier metal film 106 and a copper-silver alloy film 111 is formed.
  • the upper interconnection has a T-shaped cross section.
  • the lower part of the T-shape is an interconnection connecting plug while the upper part of the T-shape is an upper interconnection.
  • alloy means a product obtained by melting and coagulating two or more metal elements, and is intended to also include one containing a non-metal or semi-metal element in addition to metal elements. Depending on a mixing style of component elements, an alloy may have a state of a solid solution or intermetallic compound or a mixture thereof. Thus, the term “alloy” as used herein also includes such a product containing a component to its solid solution limit or more.
  • a silver content to the whole alloy film may be preferably 1 wt % or more, more preferably 2 wt % or more to more consistently prevent stress migration.
  • the silver content to the whole alloy film is 3 wt % or more may effectively reduce a maximum hysteresis error, resulting in more stable prevention of stress migration.
  • a silver content described above may allow a predetermined amount of silver to be consistently introduced in each interconnection, resulting in effective prevention of stress migration.
  • a silver content to the whole alloy film may be preferably 99 wt % or less, more preferably 80 wt % or less, further preferably 50 wt % or less.
  • a silver content to the whole alloy film is preferably 90 wt % or more, more preferably 95 wt % or more, further preferably 98 wt % or more.
  • a silver content is preferably more than a solid solution limit of silver to copper.
  • a silver content more than a solid solution limit of silver to copper would considerably reduce influence of hysteresis when the copper-silver alloy is exposed to a heat history. This will be described in Examples.
  • a solid solution limit of silver to copper will be described with reference to FIG. 16.
  • an Ag—Cu two-component eutectic compound has an eutectic point Y of 39.9 wt % (converted to a silver wt % to copper), an eutectic temperature of 779° C., and a maximum solid solution limit of Ag to Cu (Z; a point at which a solid solution limit of Ag to Cu is maximum) of 4.9 wt %.
  • a solid solution limit is plotted on Curve X at a temperature and the solid solution limit is maximum at Point Z (maximum solid solution limit).
  • a maximum process temperature is about 400° C.
  • a silver content to the total amount of component metals in a metal region is preferably more than a solid solution limit of silver to copper.
  • This solid solution limit is preferably a maximum of a solid solution limit within a temperature range of, for example, 0° C. to 400° C.
  • FIG. 1( b ) shows an example of application of this invention to a copper multilayer interconnection structure formed by a single damascene method.
  • the structure shown in FIG. 1( a ) has an advantage that the number of production steps may be reduced by simultaneously forming an interlayer connecting plug and an interconnection.
  • influence of stress migration may become significant, leading to higher tendency to formation of a void in a mode shown in FIG. 2( a ).
  • FIG. 1( b ) shows an example of application of this invention to a copper multilayer interconnection structure formed by a single damascene method.
  • the structure shown in FIG. 1( a ) has an advantage that the number of production steps may be reduced by simultaneously forming an interlayer connecting plug and an interconnection.
  • influence of stress migration may become significant, leading to higher tendency to formation of a void in a mode shown in FIG. 2( a ).
  • FIG. 1( b ) shows an example of application of this invention to a copper multilayer interconnection structure formed by a single
  • the copper-silver alloy film is separated into two parts, i.e., the interlayer connecting plug and the interconnection via an intervening barrier metal film 106 b so that stress migration can be much more reduced.
  • FIG. 1( b ) there is formed a lower interconnection consisting of a barrier metal film 102 and a copper-silver alloy film 103 in an insulating film 101 .
  • an interlayer insulating film 104 in which are formed a via plug consisting of an interlayer connecting plug 111 a as a copper-silver alloy and a barrier metal film 106 a as well as an upper interconnection consisting of a copper-silver alloy film 111 b and a barrier metal film 106 b .
  • a silver content to the whole alloy film may be preferably 1 wt % or more, more preferably 2 wt % or more to more consistently prevent stress migration.
  • the silver content to the whole alloy film is 3 wt % or more may effectively reduce a maximum hysteresis error, resulting in more stable prevention of stress migration.
  • a silver content described above may allow a predetermined amount of silver to be consistently introduced in each interconnection, resulting in effective prevention of stress migration.
  • a silver content is preferably more than a solid solution limit of silver to copper. Thus, even when a production process is changed, stress migration may be more consistently prevented.
  • the insulating film 101 and the interlayer insulating film 104 may be made of a material selected from polyorganosiloxanes such as HSQ (hydrogensilsesquioxane), MSQ (methylsilsesquioxane) and MHSQ (methylated hydrogensilsesquioxane); aromatic organic materials such as polyaryl ethers (PAEs), divinylsiloxane-bis-benzocyclobutene (BCB) and Silk®; and materials having a low dielectric constant such as SOG (spin on glass), FOX (flowable oxide), Parylene, Saitop and BCB (BenzoCycloButene).
  • An HSQ may have any of various structures such as a so-called ladder type and a cage type. Such an insulating film with a low dielectric constant may be used to minimize problems such as crosstalk, resulting in improved reliability in a device.
  • the insulating film 101 or the interlayer insulating film 104 is preferably made of a material having a substantially equal coefficient of thermal expansion to that for a component metal of the interconnection.
  • stress migration can be effectively minimize in the connecting plug and the interconnection.
  • an interlayer insulating film is preferably made of HSQ (hydrogensilsesquioxane).
  • the barrier metal films 102 and 106 may contain a high melting metal such as Ti, W and Ta.
  • a preferable metal for a barrier metal film include Ti, TiN, W, WN, Ta and TaN.
  • a tantalum barrier metal in which Ta and TaN are sequentially laminated is preferably used.
  • the barrier metal film may be formed by an appropriate process such as sputtering and CVD.
  • a thickness of the barrier metal film may be appropriately determined depending on some conditions such as the type of a material and an interconnection structure; for example, about 1 to 30 nm.
  • a diffusion barrier may be disposed between the insulating film 101 and the interlayer insulating film 104 as appropriate.
  • the diffusion barrier can prevent a component metal of the interconnection or plug from being diffused in the insulating film. Furthermore, it may play a role of an etching stopper when forming an interlayer connecting hole in a process for forming an interconnection structure.
  • a metal for the diffusion barrier include SiC, SiCN, SiN, SiOF and SiON.
  • FIG. 7 shows variation in an internal stress when a copper interconnection is exposed to a heat history consisting of a warming and a cooling processes.
  • the horizontal axis is a temperature while the vertical axis is an internal stress in a copper interconnection.
  • hysteresis occurs between a warming process (a) and a cooling process (b).
  • hysteresis between the warming and the cooling processes causes migration of a component metal in the copper interconnection. That is, a larger hysteresis leads to a larger migration or deformation, which may cause disconnection due to a void which leads to a less reliable device.
  • FIG. 8 schematically shows a temperature-stress curve when using different interconnection materials.
  • a horizontal axis is a temperature while the vertical axis is an internal stress in an interconnection.
  • FIG. 8( a ) shows usual behavior of a copper interconnection
  • FIG. 8( b ) shows behavior of a copper-silver interconnection as a copper-silver alloy film formed according to this invention.
  • a maximum width between Processes (a) and (b) is defined as a maximum hysteresis error.
  • An interconnection material defined in this invention may be used to significantly reduce the maximum hysteresis error.
  • a maximum hysteresis error is preferably 150 MPa or less, more preferably 100 MPa or less.
  • stress migration can be consistently prevented.
  • a maximum hysteresis error is 80 MPa, stress migration may be effectively prevented even during forming a fine interconnection with a size of about 0.1 ⁇ m.
  • a recrystallization temperature of a metal region such as an interconnection is preferably 200° C. or higher, more preferably 300° C. or higher.
  • stress migration can be consistently prevented.
  • a recrystallization temperature may be 350° C. or higher to further consistently prevent stress migration during the process.
  • a silicon substrate (not shown) is formed an insulating film 101 , on which is then a lower interconnection consisting of a barrier metal film 102 and a copper-silver alloy 103 .
  • the lower interconnection can be formed by a procedure described below.
  • FIG. 3( a ) shows the state at the end of the step.
  • a barrier metal film 106 is formed over the whole surface of the substrate (FIG. 3( b )).
  • a component material of the barrier metal film 106 may contain a high melting metal such as titanium, tungsten and tantalum; for example, titanium, titanium nitride, tungsten, tungsten nitride, tantalum and tantalum nitride. It may be a multilayer film in which two or more of these are laminated.
  • the barrier metal film 106 may be formed by an appropriate process such as sputtering and CVD.
  • a seed metal film 107 is formed on the barrier metal film 106 (FIG. 3( c )).
  • the seed metal film 107 plays a role as a seed for plating growth in the upper surface and may be made of copper or a copper-silver alloy.
  • the seed metal film 107 may be usually formed by sputtering.
  • a silver-containing solution is an aqueous solution of silver sulfate.
  • a concentration of the aqueous silver sulfate solution may be 50 ppm by weight to 30 wt % both inclusive. It is particularly desirable that the solution is saturated or supersaturated. Thus, dissolution of copper can be minimized to prevent deformation of the metal region.
  • Such contact with a silver-containing solution deposits silver on the seed metal film 107 to form the silver-containing film 108 .
  • a redox reaction occurs on the surface of the seed metal film 107 , resulting in deposition of silver to form the silver-containing film 108 .
  • a plating solution may be, but not limited to, an aqueous solution of copper sulfate.
  • the product is annealed at a temperature within a range of 200° C. to 450° C.
  • the annealing can increase the size of copper grains constituting the copper plating film 110 , resulting in stable reduction of a resistance.
  • silver is diffused from the silver-containing film 108 to the copper plating film 110 to form a film made of a copper-silver alloy in the interconnection groove.
  • the copper plating film 110 formed outside the interconnection groove is removed by CMP (chemical mechanical polishing) to form an interconnection structure made of a copper-silver alloy (FIG. 4( c )).
  • a convenient method can be used to consistently form an interconnection structure made of a copper-silver alloy. Furthermore, since a plating solution itself does not have to contain silver, the plating solution may be selected more freely. For example, the above process may be conducted using a plating solution having good filling properties into a narrow groove or hole to consistently form a silver-containing interconnection with a smaller width.
  • a silver-containing plating solution is used to form an interconnection structure made as a copper-silver alloy film.
  • a copper-silver alloy plating film 114 is formed on a seed metal film 107 by plating (FIG. 5( a )).
  • the plating solution used preferably contains copper and silver such that a proportion of silver to copper is 0.1% to 80% by weight.
  • This plating solution is preferably chloride-ion free. If chloride ions are present in the plating solution, silver is significantly deposited from the plating solution; specifically, deposition occurs before incorporation of silver into the film. An alloy film cannot be, therefore, consistently formed.
  • Examples of such a plating solution are as follows.
  • Silver ions can be added to a common copper pyrophosphate plating solution to prepare a pyrophosphate plating solution containing copper and silver.
  • Silver may be added using, for example, a silver nitrate solution, a silver sulfate solution.
  • a specific composition of this plating solution is, for example,
  • Silver ions can be added to a common copper ethylenediamine plating solution to prepare an ethylenediamine plating solution containing copper and silver.
  • Silver may be added using, for example, a silver nitrate solution, a silver sulfate solution.
  • a specific composition of this plating solution is, for example,
  • Ethylenediamine 0.01 to 5 mol/L: 0.01 to 5 mol/L;
  • Each of these plating solutions may contain one or more additives as appropriate.
  • it can contain a surfactant such as polyethylene glycol, polypropylene glycol, quaternary ammonium salts and gelatin.
  • a surfactant such as polyethylene glycol, polypropylene glycol, quaternary ammonium salts and gelatin.
  • These additives may equalize a copper crystal size and give a plating film with a uniform thickness.
  • the surfactant may be generally added in an amount of, but not limited to, 1 to 1000 ppm by weight to the total amount of the plating solution.
  • the plating solution is preferably substantially chloride-free. Specifically, it is preferable that a chloride concentration is 0.01 mg/L or less. Thus, deposition of silver due to a reaction with chloride may be effectively prevented so that a metal film made of a copper-silver alloy may be consistently formed.
  • Plating conditions may be appropriately determined. They may be, for example, as follows.
  • Solution temperature 10 to 80° C.
  • a current applied during plating may be either direct current or pulse current.
  • the substrate surface is polished by CMP to form an upper interconnection consisting of a barrier metal film 106 and a copper-silver alloy film 111 .
  • a convenient method can be used to consistently form an interconnection structure made of a copper-silver alloy.
  • a metal composition in the interconnection structure may be made uniform.
  • a copper plating film 114 is formed on a seed film 107 by plating (FIG. 6( a )).
  • a plating solution used may be a common copper plating solution, but preferably a chloride-free plating solution.
  • it may be preferably a common copper sulfate plating solution from which chloride ions have been removed, a copper pyrophosphate plating solution or a copper ethylenediamine plating solution. It can prevent silver from reacting with chloride ions in a copper plating film 117 in the subsequent step, to consistently give a metal film made of a copper-silver alloy.
  • a copper-silver alloy plating film 114 is formed on the copper plating film 117 by plating (FIG. 6( b )).
  • a chloride-ion free plating solution specifically, a pyrophosphate plating solution or an ethylenediamine solution described in embodiment 2.
  • the product is annealed at a temperature within a range of 200° C. to 450° C.
  • silver is diffused from the copper-silver alloy plating film 114 to the copper plating film 117 to form a film made of a copper-silver alloy with a relatively uniform composition in the interconnection groove.
  • the size of metal grains constituting these films can be increased, resulting in stable reduction of a resistance.
  • the whole substrate surface is made flat by CMP to form an interconnection structure consisting of the barrier metal film 106 and the copper-silver alloy film 111 (FIG. 6( c )).
  • a convenient method can be used to consistently form an interconnection structure made of a copper-silver alloy.
  • a metal composition in the interconnection structure may be made uniform.
  • a plating solution having good filling properties may be used to fill a narrow concave and then a silver-containing plating solution may be used to consistently form a copper-silver alloy film in an interconnection groove with a narrow width and thus to suitably form a reliable interconnection structure.
  • Metal interconnections in FIG. 17 were formed by a damascene process. All of these interconnections had dimensions of 0.1 to 0.5 ⁇ m (width) ⁇ 0.3 ⁇ m (thickness) ⁇ 49 mm (length), and silver contents in an interconnection metal were 0, 1.5 and 2.0 wt %.
  • the interconnection was formed by plating using a chloride-ion free plating solution.
  • an interconnection resistance was determined and the results shown in FIG. 17 were obtained. This figure shows that resistance increase was inhibited in the interconnection structures in which a silver content to the total amount of the component metals in an interconnection is 1.5 wt % or more.
  • a relationship between atom % and wt % is such that, for example, a silver content of 0.9 atom % corresponds to 1.5 wt %.
  • a two-layer interconnection structure shown in FIG. 10 was formed to test an yield.
  • This two-layer interconnection structure is called a via chain, in which first interconnections 22 a are formed in parallel and second interconnections 22 b perpendicular to them are formed.
  • the width of the interconnections should be wide such as 5 micron to test the stress-migration reliability effectively.
  • These interconnections are connected to each other via 20,000 connecting plugs 28 .
  • a semiconductor substrate and an interlayer insulating film are omitted.
  • a given voltage can be applied to the ends of the via chain to measure an electric resistance through 10,000 first interconnections 22 a , 10,000 second interconnections 22 b and 20,000 connecting plugs 28 .
  • the resistance is called a chain resistance, which is an effective indicator to determine the quality of the via connection. While the interconnection structure is placed under given thermal environment, variation in a chain resistance may be determined to suitably evaluate its stress-migration resistance.
  • TABLE 1 Cu/Ag Yield ratio Interconnection (relative Sample (by weight) forming process value) b0 100/0 Plating in a copper 100 sulfate bath b1 100/0 Plating in a copper 42 to 60 sulfate bath b2 99.95/0.05 Plating in a silver- 60 to 81 containing ethylenediamine bath b3 98/2 Plating in a silver- 88 to 100 containing ethylenediamine bath
  • Table 1 shows relative resistances for samples b1 to b3 when a resistance for the reference sample b0 is 100%.
  • a resistance is described as a range from the results obtained by evaluating a plurality of the samples prepared. A higher value indicates higher stress-migration resistance.
  • Samples were prepared as follows. On a silicon substrate was deposited a silicon oxide film to 500 nm by plasma CVD, on which was then deposited a Ta film to 50 nm. Then, on the upper surface was deposited a copper plating seed film to 100 to 200 nm by sputtering, on which was then deposited a copper or copper-silver alloy film to 600 to 700 nm using a given plating solution.
  • a composition of the copper or copper-silver alloy film was described in Table 2, in which plating solution 1 contains chloride ions while plating solution 2 does not.
  • Hysteresis properties were evaluated by calculating an internal stress in a plating film from a measured bending of a substrate. A substrate bending was calculated by determining a reflection angle of an irradiated laser beam on the substrate surface. A maximum hysteresis error and a recrystallization temperature were determined from the hysteresis properties thus obtained (a temperature-stress curve during the second thermal cycle). The results are shown in Table 2. Hysteresis curves for some samples are shown in FIGS. 11 to 15 , where samples c1, c2, c4, c5 and c6 correspond to FIGS. 11, 14, 12 , 13 and 15 , respectively.
  • a reliable semiconductor device having good properties such as stress-migration resistance can be provided because a metal region such as an interconnection structure is made of (i) a metal containing silver at a particular amount, (ii) a metal whose maximum hysteresis error in a temperature-stress curve for a metal region is within a particular range, or (iii) a metal whose recrystallization temperature is within a particular range.
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