US20030134479A1 - Eliminating substrate noise by an electrically isolated high-voltage I/O transistor - Google Patents

Eliminating substrate noise by an electrically isolated high-voltage I/O transistor Download PDF

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US20030134479A1
US20030134479A1 US10/051,962 US5196202A US2003134479A1 US 20030134479 A1 US20030134479 A1 US 20030134479A1 US 5196202 A US5196202 A US 5196202A US 2003134479 A1 US2003134479 A1 US 2003134479A1
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region
doping
type
transistor
semiconductor
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Craig Salling
Zhiqiang Wu
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Texas Instruments Inc
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Texas Instruments Inc
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Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SALLING, CRAIG T., WU, ZHIQIANG
Priority to JP2003562996A priority patent/JP2005516397A/ja
Priority to EP03705805A priority patent/EP1474827A4/en
Priority to PCT/US2003/001412 priority patent/WO2003063235A1/en
Publication of US20030134479A1 publication Critical patent/US20030134479A1/en
Priority to US10/684,948 priority patent/US6875650B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to structures and fabrication methods for an electrically isolated high-voltage transistor operable to eliminate substrate noise.
  • analog circuits are designed on the same semiconductor chip together with digital circuits. Consequently, since analog circuits share the same substrate with high-speed digital circuits, electrical noise created by the high-speed operation is coupled between the circuits and may affect the performance of the analog circuits. As the frequency of the operational digital circuit increases, and transistor dimensions are reduced, the effect of the noise coupling is becoming more and more serious.
  • a lateral MOS transistor On the surface of a semiconductor material of a first conductivity type, a lateral MOS transistor is described surrounded by a well of the opposite conductivity type and, nested within the well, an electrical isolation region.
  • the semiconductor region embedding this transistor has a resistivity higher than the remainder of the semiconductor material and further contains a buried layer of the opposite conductivity type. This layer extends laterally to the wells, thereby electrically isolating the near-surface portion of the semiconductor region from the remainder of the semiconductor material, and enabling the MOS transistor to operate as an electrically isolated high-voltage I/O transistor for circuit noise reduction, while having low drain junction capacitance.
  • the buried layer extends vertically deeper from the surface than the electrical isolation region, thereby enabling a separate contact to the electrically isolated near-surface portion of the semiconductor region.
  • the buried layer extends vertically from the surface not as deep as the electrical isolation region, thereby enabling contacts to the electrically isolated near-surface portion of the semiconductor region in the shape of a body-tied source.
  • This body-tied source is configured to provide a dual-function contact region to the MOS transistor source, and to the electrically isolated near-surface portion of the semiconductor region.
  • the buried layer extends vertically from the surface not as deep as the electrical isolation region, thereby enabling contacts to the electrically isolated near-surface portion of the semiconductor region in the shape of an angular-structured gate of the MOS transistor.
  • This angular-structured gate is configured to include an H-shape or a T-shape such that its directly adjacent regions provide contacts to the source, drain, and near-surface portion of the semiconductor region.
  • the high energy/high dose ion implant step transforms the electrically isolated region of the first conductivity type into a region of higher resistivity compared to the remainder of the semiconductor material of the first conductivity type.
  • the present invention is equally applicable to nMOS and pMOS transistors; the conductivity types of the semiconductor and the ion implant types are simply reversed.
  • FIG. 1 is a schematic cross section of an electrically isolated high voltage I/O nMOS transistor as provided by the first embodiment of the invention.
  • FIG. 2 is a schematic cross section of an electrically isolated high voltage I/O nMOS transistor as Provided by the second and third embodiments of the invention.
  • FIG. 3 is a schematic top view of the electrically isolated MOS transistor according to the second embodiment of the invention, depicting the source contact in the form of a body-tied-contact (alternating p-n-p-n doped regions).
  • FIG. 4 is a schematic top view of the electrically isolated nMOS transistor according to the third embodiment of the invention, depicting the gate in H-form in order to provide contact to the isolated p-well (body contact).
  • FIG. 5 is an example of a plot of the doping profiles under the gate of an nMOS transistor before and after the high-energy n-type implant according to the second and third embodiments of the invention.
  • FIG. 6A plots the computer-generated doping profiles under the gate of an nMOS transistor after a high-energy n-type and p-type implants according to the invention.
  • FIG. 6B plots the computer-generated doping profiles under source and drain of an nMOS transistor after a high-energy n-type and p-type implants according to the invention.
  • FIG. 7 shows the cross section of an nMOS transistor with the computer-generated conductivity regions after a high-energy n-type and p-type implants according to the invention.
  • the present invention is related to U.S. patent application Ser. No. 60/263,619, filed on Jan. 23, 2001 (Salling et al., “Structure and Method of MOS transistor having Increased Substrate Resistance”).
  • an output buffer drives the voltage on an output pad (I/O pad) by one or more pMOS transistors connected between pad and positive power supply voltage bus, and one or more nMOS transistors connected between pad and ground.
  • the large output nMOS transistors of an output switch When the large output nMOS transistors of an output switch are in operation, they generate substrate current pulses due to hole generation at the drain junction, and capacitive displacement currents at the drain junction's parasitic capacitance to the substrate. This substrate current constitutes noise for any sensitive, low-noise analog inputs integrated on the same chip.
  • the substrate hole current can also cause latch-up.
  • Another source of substrate current occurs when the pad of an output buffer transits to a negative voltage during some transient. For example, this may be caused by an undershot of the output buffer, or by a transient on incoming signals in a bi-directional pad (input+output pad). This substrate electron current can cause latch-up, and it may cause noise on analog inputs.
  • FIGS. 1, 2, 3 , and 4 show the resulting embodiments of IC structures according to the invention
  • FIG. 5 gives an example of a doping profile under the transistor gate illustrating the method to accomplish the desired electrical isolation of the nMOS transistor. While the examples depicted embody the experimental conditions for an nMOS transistor, analogous considerations hold for the conditions of a pMOS transistor.
  • FIG. 1 shows in simplified and schematic (not to scale) manner a small portion of an IC, generally designated 100 , having on its surface a high-voltage I/O MOS transistor isolated by a buried layer.
  • the invention applies to nMOS as well as pMOS transistors fabricated into semiconductor material 101 , often referred to as the substrate.
  • the substrate may comprise a p-type semiconductor wafer, onto which, for some devices, an epitaxial layer, also of p-type doping, has been deposited.
  • an epitaxial layer also of p-type doping
  • the semiconductor material may be silicon, silicon germanium, gallium arsenide or any other semiconductor material used in IC fabrication.
  • the resistivity of the semiconductor substrate 101 , into which the MOS transistor is fabricated ranges from about 1 to 50 ⁇ cm (this is also the resistivity of the epitaxial layer). Frequently, the material close to the MOS transistor may be generated as a well of the first conductivity type, in the example of FIG. 1 a p-well.
  • a silicon dioxide isolation trench 102 (preferably 350 nm deep) has been created to surround the lateral MOS transistor; it defines the active area of the lateral transistor.
  • the gate 103 of the MOS transistor polysilicon or another conductive material is usually chosen; its thickness 103 a is commonly between 140 and 180 nm, and the width 103 b between 0.2 and 1.0 ⁇ m.
  • the gate insulator 104 (silicon dioxide, nitrided SiO2, or others) has a physical thickness between 1 and 10 nm.
  • FIG. 1 shows an additional silicon dioxide isolation trench 170 , which defines the lateral extent of the deep well 171 on the surface.
  • This well is of the conductivity type opposite to the “first” conductivity type; in the example of FIG. 1, well 171 is an n-well; it is contacted by n+-region 172 .
  • the n-well completely surrounds the nMOS transistor, and it is reaches deep from the surface into the semiconductor material 101 of the first conductivity type (p-type in FIG. 1).
  • FIG. 1 shows a deep source 110 and an extended source 111 , further a deep drain 112 and an extended drain 113 .
  • the extended source and drain are prepared by low-energy, shallow implants (depth typically between 25 and 40 nm), the deep source and drain by medium-energy implants (depth typically between 100 and 140 nm) as part of the process flow discussed later.
  • a window 130 a in a photoresist layer 130 is used; window 130 a determines the lateral extent and active area of the MOS transistor.
  • the same photoresist and window are used for the high-energy and high dose implant 140 of the present invention.
  • This implant is performed for creating the buried layer 160 within the opening of window 130 a .
  • buried layer 160 is n-type.
  • the high energy ion implant 140 the p-type semiconductor material portion 101 a between surface and the buried layer 160 acquires a resistivity higher than the resistivity of the remainder 101 of the p-type semiconductor material.
  • buried layer 160 extends to the n-well 171 . Consequently, the buried layer electrically isolates the near-surface portion 101 a of the p-type material from the remainder 101 of the semiconductor material.
  • the nMOS transistor is completely positioned within this isolated portion 101 a and is thus an electrically isolated transistor, operable as a high-voltage I/O transistor which does not create substrate noise for the IC. Due to the partially counterdoped p-type regions under source and drain, the transistor has low drain junction capacitance.
  • the position of the buried layer 160 relative to the surface depends on the energy of the implanted ions.
  • the buried layer edge 160 a nearest the surface is deeper, i.e. farther away, from the surface than the bottom of the electrical isolation regions 102 .
  • This fact results in an electrically isolated p-type region 101 a continuous under one portion of isolation region 102 ; this connecting portion is marked 101 b in FIG. 1.
  • the thickness 101 c of the connecting portion is a function of the energy of the implanted n-type ions.
  • This continuity feature enables a separate p+-contact 106 to the electrically isolated near-surface portion 101 a of the p-type semiconductor region.
  • the geometrical extent of the contact region 106 is limited by an additional isolation region 107 , which simultaneously serves as one of the limiting “markers” for n-well 171 .
  • the thickness of the photoresist layer 130 is larger than the thickness solely required to block the lower energy implants.
  • the photoresist layer thickness is between 1.5 and 2.0 ⁇ m. If the high-energy implant accompanies the medium-energy implant, non-conductive sidewalls 150 are typically present as part of the gate structure.
  • the semiconductor of the first conductivity type (p-type) (including any epitaxial layer) has dopant species selected from a group consisting of boron, aluminum, gallium, and indium.
  • Source, drain, their extensions, and the buried layer within the semiconductor of the first conductivity type have a dopant species selected from a group consisting of arsenic, phosphorus, antimony, and bismuth.
  • the semiconductor of the first conductivity type has dopant species selected from a group consisting of arsenic, phosphorus, antimony, and bismuth.
  • Source, drain, their extensions, and the buried layer within the semiconductor of the first conductivity type have a dopant species selected from a group consisting of boron, aluminum, gallium, indium, and lithium.
  • the isolated p-type region 101 a is shallower under the poly gate 103 by a measurable distance 101 d .
  • the thickness of distance 101 c depends on the energy of the implanted n-type ions.
  • the net n-type doping of the buried layer 160 is slightly higher under the poly gate and can be measured by imaging the 2-dimensional profile of the buried n-type layer, for instance by using a 2-dimensional SIMS technique after cleaving and diode-etching the sample.
  • drain 112 is connected to the I/O pad as the high voltage contact
  • source 110 is connected to body contact 106 and both to Vss or ground
  • n-well contact 172 (and thus the buried layer 160 ) to Vdd.
  • FIG. 2 illustrates the buried layer for the second and third embodiments of the invention.
  • the main difference compared to the structure depicted in FIG. 1 is the reduced vertical depth of the buried layer 260 from the semiconductor surface, brought about by a reduced energy of the implanted n-type ions 240 . Since the depth 202 a of the isolation trench 202 is preferably 350 nm, the buried layer edge 260 a is less than 350 nm away from the surface. The buried layer 260 , however, still extends laterally to the n-well 271 (which is contacted by n+-region 272 ).
  • FIG. 2 does no longer exhibit a continuity of the isolated p-type region 201 a beyond the isolation trench 202 .
  • the constraint of isolated region 201 a necessitates specific means to establish the electrical contact to isolated region 201 a .
  • the specific means is provided by specific structures of source 210 of the MOS transistor.
  • the nMOS transistor consists of source 210 with 211 , drain 212 with 213 , gate 203 , and gate insulation 204 .
  • the electrical contact to the isolated region 201 a is provided by the design of source 210 as a “body-tied source”.
  • the structure of this body-tied-to-source is schematically illustrated in the top view of the transistor in FIG. 3.
  • Equal numbers refer to equal entities in FIGS. 2 and 3.
  • the n+ contact 272 to the n-well (and thus the buried n-type layer) completely surrounds the nMOS transistor; n+ contact 272 is electrically connected to Vdd. Nested within the n+ contact is the shallow trench isolation 202 .
  • Gate 203 of the nMOS transistor may be designed in a variety of different shapes convenient for layout and electrical connections.
  • N+-type drain contact region 212 is electrically connected to the I/O pad as the high voltage contact.
  • the (n+-type) source contact regions 210 alternate laterally with the (p+-type) body contact regions 306 (not shown in FIG. 2).
  • Overlaid metal contact layer 310 joins the electrical contacts to source and body and provides the electrical connection to Vss.
  • the electrical contact to the isolated region 201 a is provided by a design practiced in the silicon-on-insulator technology:
  • the gate is structured in an “H”-shape or a “T”-shape.
  • An example is illustrated in the schematic top view of FIG. 4 for an H-shaped gate of an nMOS transistor.
  • Equal numbers refer to equal entities in FIGS. 2 and 4.
  • the n+ contact 272 to the n-well (and thus the buried n-type layer) completely surrounds the nMOS transistor; n+ contact 272 is electrically connected to Vdd. Nested within the n+ contact is the shallow trench isolation 202 .
  • Gate 203 of the nMOS transistor may be designed in a variety of different shapes such as H-shape (as Shown in FIG. 4) or T-shape.
  • N+-type drain contact region 212 is electrically connected to the I/O pad as the high voltage contact.
  • N+-type source contact region 210 is connected to Vss.
  • P+-type body contacts 406 are also connected to Vss.
  • FIG. 5 depicts the computer-generated doping profiles under the gate, as resulting from the high-energy n-doping implant of the present invention.
  • the ordinate plots the doping concentrations on logarithmic scale, and the abscissa shows the penetration depths into the semiconductor surface, expressed in ⁇ m.
  • FIG. 5 shows the starting boron concentration (curve 502 ) and the implanted phosphorus concentration (curve 501 ). as needed for creating the buried n-type layer at a depth as illustrated in FIG. 2. Further, the resulting net doping is illustrated (curve 503 ).
  • the phosphorus implant is selected at the energy of 500 keV at the dose of 2.0 E13 cm-2. This creates the buried n-type layer as depicted in FIG. 2, with the peak penetration is somewhat less deep under the surface than in FIG. 1 (an energy of about 675 keV at the same dose of 2.0E13 cm-2 is needed for the penetration of FIG. 1).
  • the phosphorus doping overcompensates the boron doping (curve 502 ), leading to the buried n-type region embedded within the p-type semiconductor material.
  • a computer simulation of a similar preferred ion implant condition for creating the buried layer is displayed for the conditions of:
  • FIG. 6A plots the resulting doping concentrations under the gate
  • FIG. 6B plots the concentrations under source and drain.
  • a junction has been created where the phosphorus doping curves intersect with the boron implant curves.
  • phosphorus doping curve 601 intersects with boron doping curve 602 at points 603 and 604 .
  • the region 610 stretching approximately from 0.22 to 0.62 ⁇ m depth, the phosphorus doping overcompensates the boron doping, leading to the buried n-type region embedded within the p-type semiconductor material.
  • phosphorus doping curve 621 intersects with boron doping curve 622 at points 623 and 624 .
  • region 640 stretching approximately from 0.45 ⁇ m to 0.68 ⁇ m depth, the phosphorus doping overcompensates the boron doping, leading to the buried n-type region.
  • the buried layer continues from the region under the gate to the regions under source and drain, until the buried layer merges with the n-wells. There is a slight shift in depth, as indicated schematically in FIGS. 1 and 2 and more realistically by the computer simulations in FIG. 7.
  • the nMOS transistor cross section of FIG. 7 shows above the semiconductor surface 701 the gate 702 and the non-conductive side-walls 703 , and under the surface the buried p-type region 704 , the n-type source 705 and drain 706 , and the buried n-layer 707 .
  • Buried layer 707 has been created by the high-energy n-type ion implant according to the invention; it stretches closer to the surface (and is thicker) under the gate 702 , but is continuous from source to drain where it connects to the n-wells (not shown in FIG. 7).
  • the location, peak and depth of the buried layer can be precisely controlled by employing a high-energy, low-dose implant of p-doping ions in conjunction with the high-energy n-doping implant.
  • the ion energy is between 70 and 140 keV, and the dose between 5 ⁇ 10E12 to 5 ⁇ 10E13. The effect of such implant can readily be deduced from FIGS. 6A, 6B and 7 .
  • the method of fabricating a buried n-type layer connecting two n-wells in a p-type semiconductor surface region having an increased resistivity relative to a p-type semiconductor sub-surface region comprises the following process steps (analogous process steps apply for the fabrication of a buried p-type layer):
  • the method of fabricating an electrically isolated high-voltage I/O nMOS transistor in the surface of p-type semiconductor material comprises the following process steps (analogous process steps apply for the fabrication of a pMOS transistor):
  • n-doping ions implanting, at medium energy, n-doping ions into the exposed surface area, creating an n-doped region (peak concentration from about 5 ⁇ E19 to 5 ⁇ 10E20 cm-3) that extends to a medium depth (between 50 and 20 nm) under said surface, suitable as deep source and drain of the transistor;
  • an additional process step can be added after the high-energy n-type implant in order to control precisely the location, peak and depth of the buried layer:
  • the method of forming the electrical contact is selected from the following processes:
  • an angular-structured gate configured to include an H-shape or a T-shape such that its directly adjacent regions provide contacts to the source, drain and near-surface portion of the isolated p-type region.
  • the method may comprise steps of annealing the high and/or medium energy implants at elevated temperature.
  • the process steps may be modified by implanting the n-doping ions at high energy after the process step of implanting the n-doping ions at medium energy when the buried layer is shallow. It is therefore intended that the appended claims encompass any such modifications or embodiments.

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US10/051,962 US20030134479A1 (en) 2002-01-16 2002-01-16 Eliminating substrate noise by an electrically isolated high-voltage I/O transistor
JP2003562996A JP2005516397A (ja) 2002-01-16 2003-01-16 電気的に絶縁された高電圧ｉ／ｏトランジスタによる基板ノイズの除去
EP03705805A EP1474827A4 (en) 2002-01-16 2003-01-16 ELIMINATING SUBSTRATE NOISE BY AN ELECTRICALLY INSULATED HIGH VOLTAGE I / O TRANSISTOR
PCT/US2003/001412 WO2003063235A1 (en) 2002-01-16 2003-01-16 Eliminating substrate noise by an electrically isolated high-voltage i/o transistor
US10/684,948 US6875650B2 (en) 2002-01-16 2003-10-14 Eliminating substrate noise by an electrically isolated high-voltage I/O transistor

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