US10548222B1 - Embedded passive device structure - Google Patents

Embedded passive device structure Download PDF

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US10548222B1
US10548222B1 US16/292,625 US201916292625A US10548222B1 US 10548222 B1 US10548222 B1 US 10548222B1 US 201916292625 A US201916292625 A US 201916292625A US 10548222 B1 US10548222 B1 US 10548222B1
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layer
device structure
passive device
embedded passive
electrically conductive
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Tsung-Her Yeh
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FLEX TEK Co Ltd
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    • H—ELECTRICITY
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    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/01—Mounting; Supporting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/148—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals embracing or surrounding the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C13/00—Resistors not provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C13/00—Resistors not provided for elsewhere
    • H01C13/02—Structural combinations of resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
    • H01C17/075—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin film techniques
    • H01C17/12—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin film techniques by sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/006—Thin film resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/2847—Sheets; Strips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/29—Terminals; Tapping arrangements for signal inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/29—Terminals; Tapping arrangements for signal inductances
    • H01F27/292—Surface mounted devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F38/00—Adaptations of transformers or inductances for specific applications or functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
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    • H05K2201/0154—Polyimide
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0158—Polyalkene or polyolefin, e.g. polyethylene [PE], polypropylene [PP]
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Definitions

  • the present invention relates to the technology field of embedded passive components, and more particularly to an embedded passive device structure comprising embedded thin film resistors, embedded thin film inductors and embedded thin film capacitors.
  • one solution developed by the electronics manufacturing plants is to continuously reduce the size of passive electronic components for use in the portable electronic devices.
  • the passive electronic components having a specific size of 0805 (80 ⁇ 50 mil 2 ) are used in the manufacture of various mother boards, and the passive electronic components having a specific size of 0603 (60 ⁇ 30 mil 2 ) are used in the fabrication of conventionally-commercial laptop PCs.
  • the passive electronic components having a specific size of 0402 (40 ⁇ 20 mil 2 ) are used in the manufacture of smart phones, and the passive electronic components having a specific size of 0201 (20 ⁇ 10 mil 2 ) are used in the production of commercial tablet PCs.
  • technology for forming embedded passive components in a PCB is noticed again in recent years.
  • U.S. patent publication No. 2006/0286696 A1 has disclosed a passive electrical article.
  • FIG. 1 shows a schematic cross-sectional diagram of a passive electrical article disclosed by U.S. patent publication No. 2006/0286696 A1.
  • the passive electrical article PE′ mainly comprises: a first laminated copper layer 11 ′, a resistor layer 12 ′, an insulation layer 13 ′, and a second laminated copper layer 14 ′, wherein the resistor layer 12 ′ is made of a Ni—P compound, and the insulation layer 13 ′ is a polymer layer having thickness in a range from 6 ⁇ m to 20 ⁇ m.
  • the polymer layer is such as a polyimide (PI) layer.
  • the first laminated copper layer 11 ′ and the resistor layer 12 ′ constitute a thin film resistor V.
  • the said passive electrical article PE′ can be manufactured by using following process steps:
  • both the second laminated copper layer 14 ′ and the first laminated copper layer 11 ′ have a thickness of 36 ⁇ m, meaning that the passive electrical article PE′ has a total thickness in a range between 79 ⁇ m and 93 ⁇ m.
  • the thin film resistor 1 ′ is conventionally fabricated by letting a resistor layer 12 ′ be formed on a matt side of the first laminated copper layer 11 ′. Because the resistor layer 12 ′ is made of Ni—P compound by using electroplating process, the electroplating waste certainly contain high-concentration P ingredient and induce an important issue of electroplating waste treatment.
  • test results report that a stripping phenomenon starts to occur between the first laminated copper layer 11 ′ and the resistor layer 12 ′ after the passive electrical article PE′ is bent over 40 times. Therefore, related experimental results have proved that, there is room for improvement in joint strength between the first laminated copper layer 11 ′ and the resistor layer 12 ′.
  • the resistor layer 12 ′ made of Ni—P compound has poor etching resistance against to commercial Cu etchant, it must apply three times of etching processes to the passive electrical article PE′ in order to form necessary thin film resistors 1 ′ on the identical passive electrical article PE′. After completing the three times of etching processes, thin film resistor components have good reliability can be formed on the passive electrical article PE′ in the case of precisely meeting the requirements of a demanded line width and/or a length.
  • the electronic circuit having at least one resistor component made on the passive electrical article PE′ by using the photolithography process, commonly has a line width and a line pitch greater than 30 ⁇ m and 30 ⁇ m, respectively.
  • FIG. 2 shows a schematic cross-sectional diagram of the multilayered construction for resistor and capacitor formation disclosed by U.S. Pat. No. 7,192,654.
  • the multilayered construction MS′ comprises: a first laminated copper layer 21 ′, a resistor layer 22 ′, a first dielectric layer 23 ′, an insulation layer 24 ′, a second dielectric layer 25 ′, and a second laminated copper layer 26 ′, wherein the insulation layer 24 ′ is made of polyimide (PI) and has a thickness in a range from 6 ⁇ m to 20 ⁇ m.
  • the first laminated copper layer 21 ′ and the resistor layer 22 ′ constitute a thin film resistor 2 ′.
  • the multilayered construction MS′ can be manufactured by using following process steps:
  • the resistor layer 22 ′ of the thin film resistor 2 ′ is attached to the first dielectric layer 23 ′ of the dielectric insulator 2 a ′.
  • both the second laminated copper layer 26 ′ and the first laminated copper layer 21 ′ generally have a thickness of 36 ⁇ m
  • the insulation layer 24 ′ has a thickness in a range between 6 ⁇ m and 20 ⁇ m.
  • both the first dielectric layer 23 ′ and the second dielectric layer 25 ′ have a thickness of 8 ⁇ m.
  • the multilayered construction MS′ has a total thickness in a range between 94 ⁇ m and 108 ⁇ m.
  • the thin film resistor 2 ′ is conventionally fabricated by letting a resistor layer 22 ′ be formed on a matt side of the first laminated copper layer 21 ′.
  • the resistor layer 22 ′ is made of Ni—P compound by using electroplating process, the electroplating waste certainly contain high-concentration P ingredient and induce an important issue of electroplating waste treatment.
  • test results report that a stripping phenomenon starts to occur between the first laminated copper layer 21 ′ and the resistor layer 22 ′ after the passive electrical article PE′ is bent over 40 times. Therefore, related experimental results have proved that, there is room for improvement in joint strength between the first laminated copper layer 21 ′ and the resistor layer 22 ′.
  • the primary objective of the present invention is to provide an embedded passive device structure, comprising: a first electrically conductive layer, a resistor layer, a dielectric layer, a support layer, a joint layer, and a second electrically conductive layer.
  • a first electrically conductive layer comprising: a first electrically conductive layer, a resistor layer, a dielectric layer, a support layer, a joint layer, and a second electrically conductive layer.
  • it is able to form an electronic circuit topology comprising at least one thin film resistor, at least one thin film capacitor and at least one thin film inductor on the embedded passive device structure by applying two times of photolithography processes to the embedded passive device structure.
  • the resistor layer, formed on the first electrically conductive layer through sputter-coating process is made of Ni, Cr, W, or compound thereof so as to show the lowest resistance less than or equal to 5 ⁇ /sq because of having good film continuity and surface densification.
  • the use of sputter-coating technology
  • the inventor of the present invention provides an embodiment for the embedded passive device structure, comprising:
  • both the first electrically conductive layer and the second electrically conductive layer are made of an electrically conductive material selected from the group consisting of silver (Ag), cooper (Cu), gold (Au), aluminum (Al), Ag-based compound, Cu-based compound, Au-based compound, Al-based compound, and a combination of two or more of the foregoing materials.
  • the support layer is a flexible substrate or a solid substrate
  • a manufacturing material for the support layer is selected from the group consisting of epoxy resin, melamine, polyimine, polyvinylidene fluoride, cyanoethyl amylopectin, benzocyclobutene, polynorbornene, polytetrafluoroethylene, acrylate, polyphenylene ether, cyanate, bismaleimide triazine, allylated polyphenylene ether, and a combination of two or more of the foregoing materials.
  • judgment criteria for determining whether the support layer is one flexible substrate or one solid substrate is substrate thickness. Once the substrate thickness is greater than 200 ⁇ m, it is difficult for the support layer to show flexibility even if the support layer is made of any one of foregoing manufacturing material. In such case, the support layer is regarded as a solid substrate.
  • the resistor layer is formed on the first electrically conductive layer through a sputtering process.
  • the dielectric layer comprises a polymer matrix and a plurality of dielectric particles doped in or enclosed by the polymer matrix, and a manufacturing material for the dielectric particles be selected from the group consisting of high-dielectric material, medium-dielectric material and low-dielectric material.
  • the dielectric layer is made by using a sputtering process so as to have a perovskite structure or a spinel structure, and there is a trace element additive contained in the dielectric layer; wherein the trace element additive is selected from the group consisting of lanthanide element, actinide element, rare earth element, and alkaline earth element.
  • the use of the trace element additive is helpful for making the dielectric layer exhibit a specific property of low K, high K, or high Q through adjusting the number of donners and/or accepters in the dielectric layer.
  • the Ni-based alloy is selected from the group consisting of Ni 1-x Cr x , Ni 1-x-y Cr x M y , N 1-x W x , and Ni 1-x-y W x M y , wherein M is metal element.
  • Ni-based compound is selected from the group consisting of Ni 1-x-z Cr x N z and Ni 1-x-y W x N z , wherein N is nonmetallic element.
  • the Cr-based alloy is selected from the group consisting of Cr 1-x W x and Cr 1-x-y W x M y , wherein M is metal element.
  • the Cr-based compound is selected from the group consisting of Cr 1-x-z W x N z , wherein N is nonmetallic element.
  • the W-based alloy is selected from the group consisting of W 1-x Cr x and W 1-x-y Cr x M y , wherein M is metal element.
  • the W-based compound is selected from the group consisting of W 1-x-z Cr x N z , wherein N is nonmetallic element.
  • M is selected from the group consisting of cooper (Cu), molybdenum (Mo), vanadium (V), tungsten (W), iron (Fe), aluminum (Al), and titanium (Ti), and N is selected from the group consisting of boron (B), carbon (C), nitrogen (N), oxygen (O), and silicon (Si).
  • FIG. 1 shows a schematic cross-sectional diagram of a passive electrical article disclosed by U.S. patent publication No. 2006/0286696 A1;
  • FIG. 2 shows a schematic cross-sectional diagram of multilayered construction for resistor and capacitor formation disclosed by U.S. Pat. No. 7,192,654;
  • FIG. 3 shows a schematic stereo diagram of an embedded passive device structure according to the present invention
  • FIG. 4 shows a schematic manufacturing process flow of the embedded passive device structure
  • FIG. 5 shows a schematic manufacturing process flow of the embedded passive device structure
  • FIG. 6A shows a diagram for describing photolithography processes of the embedded passive device structure
  • FIG. 6B shows a diagram for describing photolithography processes of the embedded passive device structure
  • FIG. 6C shows a diagram for describing photolithography processes of the embedded passive device structure
  • FIG. 6D shows a diagram for describing photolithography processes of the embedded passive device structure
  • FIG. 7 shows an EBSD image of the passive electrical article disclosed by U.S. patent publication No. 2006/0286696 A1;
  • FIG. 8 shows an EBSD image of the embedded passive device structure
  • FIG. 9 shows a schematic diagram for depicting a process flow of a bending test applied to the embedded passive device structure.
  • the embedded passive device structure PSD comprises: a first electrically conductive layer 11 , a resistor layer 12 , a dielectric layer Ide, a support layer 21 , a joint layer 22 , and a second electrically conductive layer 23 .
  • Both the first electrically conductive layer 11 and the second electrically conductive layer 23 have a thickness in a range from 0.4 ⁇ m to 50 ⁇ m, and are made of an electrically conductive material selected from the group consisting of silver (Ag), cooper (Cu), gold (Au), aluminum (Al), Ag-based compound, Cu-based compound, Au-based compound, Al-based compound, and a combination of two or more of the foregoing materials.
  • the resistor layer 12 is formed on the first electrically conductive layer 11 and has a thickness thinner than 2 ⁇ m.
  • the first electrically conductive layer 11 is commonly made of copper (Cu), and the resistor layer 12 is formed on the first electrically conductive layer 11 through a sputtering process.
  • Cu copper
  • the resistor layer 12 is formed on the first electrically conductive layer 11 through a sputtering process.
  • it is able to form one portion of the resistor layer 12 on the copper layer (i.e., the first electrically conductive layer 11 ) via electroplating process, and then complete the fabrication of other portions of the resistor layer 12 through the sputter-coating process.
  • the resistor layer 12 formed on the copper layer through sputter-coating process shows the lowest resistance less than or equal to 5 ⁇ /sq because of having better film compactness and continuity.
  • a manufacturing material for the joint layer is selected from the group consisting of Ni, Cr, W, Ni-based compound, Cr-based compound, W-based compound, Ni-based alloy, Cr-based alloy, and W-based alloy.
  • exemplary materials for making the resistor layer 12 are listed in following Table (1).
  • Types of the Corresponding resistor layer exemplary material Ni-based compound Ni 1 ⁇ x ⁇ z Cr x N z or N 1 ⁇ x ⁇ y W x N z W-based compound W 1 ⁇ x ⁇ z Cr x N z Ni-based alloy Ni 1 ⁇ x Cr x , Ni 1 ⁇ x ⁇ y Cr x M y , N 1 ⁇ x W x , or Ni 1 ⁇ x ⁇ y W x M y W-based alloy W 1 ⁇ x Cr x or W 1 ⁇ x ⁇ y Cr x M y
  • M is metal element and selected from the group consisting of cooper (Cu), molybdenum (Mo), vanadium (V), tungsten (W), iron (Fe), aluminum (Al), and titanium (Ti).
  • N is nonmetallic element and selected from the group consisting of cooper (Cu), molybdenum (Mo), vanadium (V), tungsten (W), iron (Fe), aluminum (Al), and titanium (Ti).
  • the dielectric layer Ide is connected to the resistor layer 12 , and the support layer 21 is connected to the dielectric layer Ide.
  • the dielectric layer Ide has a thickness in a range from 0.01 ⁇ m to 50 ⁇ m, and the support layer 21 has a thickness in a range between 5 ⁇ m and 350 ⁇ m.
  • the dielectric layer Ide comprises a polymer matrix and a plurality of dielectric particles doped in or enclosed by the polymer matrix, and a manufacturing material for the dielectric particles be selected from the group consisting of high-dielectric material, medium-dielectric material and low-dielectric material.
  • the dielectric layer Ide is made by using a sputtering process so as to have a perovskite structure or a spinel structure, and there is a trace element additive contained in the dielectric layer Ide.
  • the trace element additive is selected from the group consisting of lanthanide element, actinide element, rare earth element, and alkaline earth element. It is worth explaining that, the use of the trace element additive is helpful for making the dielectric layer Ide exhibit a specific property of low K, high K, or high Q through adjusting the number of donners and/or accepters in the dielectric layer Ide.
  • exemplary materials for making dielectric layer Ide are listed in following Table (2).
  • High-K dielectric BaTiO 3 , BaZrO 3 , HfO 2 , Y 2 O 3 , doped particles BaTiO 3 e.g., La-doped BaTiO 3
  • Material having properties of high Q and low K (Ba 1 ⁇ x Al x )TiO 3 .
  • the support layer 21 is a flexible substrate or a solid substrate made of glass fiber.
  • a manufacturing material for the support layer 21 IS selected from the group consisting of epoxy resin, melamine, polyimine, polyvinylidene fluoride, cyanoethyl amylopectin, benzocyclobutene, polynorbornene, polytetrafluoroethylene, acrylate, polyphenylene ether, cyanate, bismaleimide triazine, allylated polyphenylene ether, and a combination of two or more of the foregoing materials. It needs to further explain that, judgment criteria for determining whether the support layer 21 is one flexible substrate or one solid substrate is substrate thickness.
  • the joint layer 22 is connected to the support layer 21 , and has a thickness thinner than 2 ⁇ m.
  • a manufacturing material for the joint layer 22 is selected from the group consisting of Ni, Cr, W, Ni-based compound, Cr-based compound, W-based compound, Ni-based alloy, Cr-based alloy, and W-based alloy. Exemplary materials for making the joint layer 22 can refer to above-presented Table (1).
  • the joint layer 22 can also be made of Ni—Cu alloy, Ni—Ti alloy, Cu—Ti alloy, or Cr—Ni alloy.
  • FIG. 4 illustrates a schematic manufacturing process flow of the embedded passive device structure.
  • the first method for making the embedded passive device structure PSD of the present invention comprises several process steps. First of all, as diagram (a) in FIG. 4 shows, a resistor layer 12 is formed on one surface of a dielectric layer Ide through sputtering process, and a first electrically dielectric conductive layer 11 is formed on the resistor layer 12 , such that a thin film resistor CR is obtained. Subsequently, as diagram (b) in FIG.
  • a joint layer 22 is formed on one surface of a support layer 21 through sputter-coating process, and a second electrically conductive layer 23 is formed on the joint layer 22 via through sputter-coating process, so as to obtain a thin film insulator CI. Consequently, as diagrams (c) and (d) in FIG. 4 show, the thin film insulator CI and the thin film resistor CR are combined together by making the support layer 21 be attached to the dielectric layer Ide, such that the embedded passive device structure PSD of the present invention is therefore obtained.
  • FIG. 5 illustrates a schematic manufacturing process flow of the embedded passive device structure.
  • the second method for making the embedded passive device structure PSD of the present invention comprises several process steps. First of all, as diagram (a) in FIG. 5 shows, a joint layer 22 is formed on one surface of a support layer 21 through sputtering process, and a second electrically dielectric conductive layer 23 is subsequently formed on the joint layer 22 , such that a thin film insulator CI is obtained. Subsequently, as diagram (b) in FIG. 5 shows, a dielectric layer Ide is formed on another one surface of a support layer 21 .
  • a resistor layer 12 is formed on one surface of a first electrically conductive layer 11 through sputtering process, so as to obtain a thin film resistor CR. Consequently, as diagram (d) in FIG. 5 shows, the thin film insulator CI and the thin film resistor CR are combined together by making the resistor layer 12 be attached to the dielectric layer Ide, such that the embedded passive device structure PSD of the present invention is therefore obtained.
  • FIG. 6A , FIG. 6B , FIG. 6C , and FIG. 6D show diagrams for describing photolithography processes of the embedded passive device structure. Particularly, it is able to form an electronic circuit topology comprising at least one thin film resistor, at least one thin film capacitor and at least one thin film inductor on the embedded passive device structure PSD by applying two times of photolithography processes to the embedded passive device structure PSD.
  • FIG. 6A , FIG. 6B , FIG. 6C , and FIG. 6D show diagrams for describing photolithography processes of the embedded passive device structure. Particularly, it is able to form an electronic circuit topology comprising at least one thin film resistor, at least one thin film capacitor and at least one thin film inductor on the embedded passive device structure PSD by applying two times of photolithography processes to the embedded passive device structure PSD.
  • FIG. 6A , FIG. 6B , FIG. 6C , and FIG. 6D show diagrams for describing photolithography processes of the embedded passive device structure. Particularly, it
  • FIG. 6A show, a first photoresistor PR 1 is formed on both the first electrically conductive layer 11 and the second electrically conductive 23 , and then a patterned first photoresistor pPR 1 is made on the first electrically conductive layer 11 and the second electrically conductive 23 showing as shown as diagrams (a′) and (b′) in FIG. 6A .
  • etching process is applied to remove a portion of the first electrically conductive layer 11 and a portion of the resistor layer 12 which are not covered by the first patterned photoresistor pPR 1 , and simultaneously remove a portion of the second electrically conductive layer 23 and a portion of the joint layer 22 which are not covered by the first patterned photoresistor pPR 1 . Consequently, as diagrams (a′) and (b′) in FIG. 6B show, a patterned first electrically conductive layer p 11 and a patterned second electrically conductive layer p 23 are respectively formed the dielectric layer Ide and the support layer 21 after the first patterned photoresistor pPR 1 is removed.
  • a second photoresistor PR 2 is formed on both the patterned first electrically conductive layer p 11 and the dielectric layer Ide, and the second photoresistor PR 2 is also formed on both the patterned second electrically conductive layer p 23 and the support layer 21 .
  • the second photoresistor PR 2 shown in FIG. 6C is presented by a transparent form in order to let the variations of the patterned first electrically conductive layer p 11 and the patterned second electrically conductive layer p 23 be seen during the execution of following process steps.
  • etching process is applied to remove a portion of the first patterned electrically conductive layer p 11 and a portion of the second patterned electrically conductive layer p 23 which are not covered by the second photoresistor PR 2 . Consequently, as diagrams (a) and (b) in FIG. 6D show, a first electronic circuit comprising the first patterned electrically conductive layer p 11 is formed on the dielectric layer Ide, and a second electronic circuit comprising the second patterned electrically conductive layer p 23 is formed on the support layer 21 .
  • the first electronic circuit contains one thin film resistor R, one thin film inductor L and an upper metal plate UM.
  • the second electronic circuit contains a lower metal plate LM, such that the upper metal plate UM, the lower metal plate LM, and the dielectric layer Ide and the support layer 21 clamped between the upper metal plate UM and the lower metal plate LM constituted a thin film capacitor C. Therefore, diagrams of FIG. 6A , FIG. 6B , FIG. 6C , and FIG.
  • 6D have exemplarily showed that, it is able to form an electronic circuit topology comprising at least one thin film resistor, at least one thin film capacitor and at least one thin film inductor on the embedded passive device structure PSD by applying two times of photolithography processes to the embedded passive device structure PSD.
  • FIG. 5 shows an embedded passive device structure PSD (as shown in FIG. 5 ) of the present invention can indeed exhibit outstanding properties superior than that of the passive electrical article PE′ (as shown in FIG. 1 ) disclosed by U.S. patent US2006/0286696 A1
  • inventors of the present invention have made related samples of the embedded passive device structure PSD and the passive electrical article PE′.
  • FIG. 7 shows an EBSD (electron back-scattered diffraction) image of the passive electrical article disclosed by U.S. patent publication No. 2006/0286696 A1
  • FIG. 8 shows an EBSD image of the embedded passive device structure.
  • the resistor layer 12 ′ made of Ni—P compound by using electroplating process commonly show the drawbacks of film discontinuity and high surface roughness, and these drawbacks further lead the thin film resistor 1 ′ made on the passive electrical article PE′ to exhibit higher surface resistance (electrical characteristics) and poor bending and stretching characteristics (mechanical characteristics). Moreover, from FIG. 7 , it is observed that the resistor layer 12 ′ made by using electroplating process indeed shows the drawbacks of film discontinuity and high surface roughness. On the contrary, from FIG.
  • the resistor layer 12 i.e., the Ni 0.97 Cr 0.03 layer
  • the copper foil i.e., the first electrically conductive layer 11
  • the Ni 0.97 Cr 0.03 layer shows the lowest resistance less than or equal to 5 ⁇ /sq because of having good film continuity and surface densification.
  • FIG. 9 shows a schematic diagram for depicting a process flow of a bending test applied to the embedded passive device structure.
  • a bending test machine is used to bend the thin film resistor CR of the embedded passive device structure PSD from 0 degree to 90 degree by using a ⁇ 4 mm roller.
  • diagrams (b) and (c) further depict that the bending test machine is continuously used to bend the thin film resistor CR from 90 degree to 180 degree by using the ⁇ 4 mm roller.
  • diagrams (a) and (b) depict that a bending test machine is used to bend the thin film resistor CR of the embedded passive device structure PSD from 0 degree to 90 degree by using a ⁇ 8 mm roller. Moreover, diagrams (b) and (c) further depict that the bending test machine is continuously used to bend the thin film resistor CR from 90 degree to 180 degree by using the ⁇ 8 mm roller. Experimental data of the two bending tests are integrated in following Table (3).
  • test results of Table (3) report that, by forming the resistor layer 12 onto the copper foil (i.e., the first electrically conductive 11 ) through sputter-coating process, the copper foil and the resistor layer 12 made of metal, metal alloy or metal compound certainly have strong joint strength between each other. Therefore, it is understood that the thin film resistor CR of the present invention should have an excellent reliability.
  • the present invention includes the advantages of:
  • an embedded passive device structure PSD comprising a first electrically conductive layer 11 , a resistor layer 12 , a dielectric layer Ide, a support layer 21 , a joint layer 22 , and a second electrically conductive layer 23 is proposed.
  • it is able to form an electronic circuit topology comprising at least one thin film resistor, at least one thin film capacitor and at least one thin film inductor on the embedded passive device structure PSD by applying two times of photolithography processes to the embedded passive device structure PSD.
  • the resistor layer 12 formed on the first electrically conductive layer 11 through sputter-coating process, is made of Ni, Cr, W, or compound thereof so as to show the lowest resistance less than or equal to 5 ⁇ /sq because of having good film continuity and surface densification. Moreover, the use of sputter-coating technology is helpful in reduction of industrial waste water.
  • the electronic circuit made on the embedded passive device structure PSD by using the photolithography process, can be easily controlled to has a line width and a line pitch smaller than 10 ⁇ m and 10 ⁇ m and, respectively.

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US20090071599A1 (en) * 2007-09-19 2009-03-19 Garo Miyamoto Method for manufacturing a printed-wiring board having a resistive element
US20090139756A1 (en) * 2007-12-03 2009-06-04 Subtron Technology Co. Ltd. Fabricating process of circuit board with embedded passive component

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US7474538B2 (en) * 2002-05-27 2009-01-06 Nec Corporation Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package
US7430128B2 (en) * 2004-10-18 2008-09-30 E.I. Du Pont De Nemours And Company Capacitive/resistive devices, organic dielectric laminates and printed wiring boards incorporating such devices, and methods of making thereof
US7596842B2 (en) * 2005-02-22 2009-10-06 Oak-Mitsui Inc. Method of making multilayered construction for use in resistors and capacitors
JP4725278B2 (ja) * 2005-10-11 2011-07-13 東レ株式会社 キャパシタ
JP2011171621A (ja) * 2010-02-22 2011-09-01 Jx Nippon Mining & Metals Corp 抵抗層付き銅箔並びに銅張積層板及びその製造方法
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US20090071599A1 (en) * 2007-09-19 2009-03-19 Garo Miyamoto Method for manufacturing a printed-wiring board having a resistive element
US20090139756A1 (en) * 2007-12-03 2009-06-04 Subtron Technology Co. Ltd. Fabricating process of circuit board with embedded passive component

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CN110265197A (zh) 2019-09-20

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