US10192754B2 - Epitaxial silicon wafer and method for producing the epitaxial silicon wafer - Google Patents

Epitaxial silicon wafer and method for producing the epitaxial silicon wafer Download PDF

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US10192754B2
US10192754B2 US15/311,307 US201515311307A US10192754B2 US 10192754 B2 US10192754 B2 US 10192754B2 US 201515311307 A US201515311307 A US 201515311307A US 10192754 B2 US10192754 B2 US 10192754B2
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silicon wafer
thermal treatment
atoms
oxygen
epitaxial
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Jun Fujise
Toshiaki Ono
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Sumco Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/53Physical imperfections the imperfections being within the semiconductor body 
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    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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    • C30B15/00Single-crystal growth by pulling from a melt, e.g. Czochralski method
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    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02Heat treatment
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections

Definitions

  • the present invention relates to an epitaxial silicon wafer and a method for producing the epitaxial silicon wafer, and more particularly relates to an epitaxial silicon wafer provided with a silicon wafer that contains no dislocation cluster and no COP (Crystal Originated Particle), and a method for producing the epitaxial silicon wafer.
  • COP Crystal Originated Particle
  • Oxygen precipitates (BMD; Bulk Micro Defect) in a silicon wafer are useful to capture impurities in a semiconductor device process.
  • the oxygen precipitates are formed in a growing stage of a silicon single crystal, which is a material for a wafer, for example.
  • a silicon single crystal which is a material for a wafer, for example.
  • an epitaxial silicon wafer it is known that the wafer is subjected to a high temperature at a time of epitaxial growth treatment, whereby the oxygen precipitates inside the wafer disappear, and an impurities capturing ability (a gettering ability) is reduced. Consequently, it is desired to provide an epitaxial wafer excellent in impurities capturing ability.
  • Patent Literature 1 A technique (a pre-annealing technique) has been known (refer to Patent Literature 1, for example) that performs thermal treatment of a wafer at a temperature of 600° C. or more before epitaxial growth treatment, in order to obtain such an epitaxial silicon wafer.
  • thermal treatment the oxygen precipitate density inside the water is increased in advance so that oxygen precipitates remain with a sufficient density after the epitaxial growth treatment, whereby the impurity capturing ability of the wafer after epitaxial growth is enhanced.
  • the defects causing epitaxial defects out of the defects included in a silicon wafer include a dislocation cluster and COP.
  • a dislocation cluster is an aggregate of interstitial silicon atoms that are excessively taken interstitially, and is a defect (a dislocation loop) of a large size of approximately 10 ⁇ m, for example.
  • a COP is an aggregate (a vacancy aggregate hollow defect) of vacancies where atoms that should compose a crystal lattice are lost. In order to prevent generation of an epitaxial defect, use of a wafer where neither a dislocation cluster nor COP is present is useful.
  • Pv region As a region where no COP and no dislocation cluster are present in a silicon wafer, there is an oxygen precipitation promotion region (hereinafter, also referred to as “Pv region”) and an oxygen precipitation suppression region (hereinafter, also referred to as “Pi region”).
  • the Pv region is a defect-free region where a vacancy type point defect is dominant
  • the Pi region is a defect-free region where an interstitial silicon type point defect is dominant.
  • a silicon wafer composed of a region where no COP and no dislocation cluster are present is useful as a substrate wafer for epitaxial growth.
  • a control process margin width more specifically, a range of allowable V/G is narrow. If it is allowed to grow a single crystal in a range of a growth condition in which both of the Pv region and the Pi region are obtained, the control process margin width increases, and it is possible to produce a crystal that contains no dislocation cluster and no COP stably.
  • An object of the present invention which has been made in the light of the above described problem, is to provide a wafer that is an epitaxial silicon wafer and is excellent in gettering ability throughout an entire surface of the wafer, and a method for producing the wafer.
  • a gist of the present invention is an epitaxial silicon wafer described in (I) as follows, and a method for producing the epitaxial silicon wafer in (II) as follows.
  • a density of oxygen precipitates in a central portion in a thickness direction of the silicon wafer is 5 ⁇ 10 4 /cm 2 or more throughout an entire region in a radial direction of the silicon wafer.
  • the production method further including a thermal treatment condition determining step of determining a thermal treatment condition in the preliminary thermal treatment step, based on a ratio of the oxygen precipitation suppression region of the silicon wafer before the preliminary thermal treatment step is carried out.
  • the thermal treatment condition determining step in the thermal treatment condition determining step, is preferably determined so as to satisfy any one of the following relational expressions (1) to (3):
  • the epitaxial silicon wafer of the present invention can have the oxygen precipitate density of 5 ⁇ 10 4 /cm 2 or more throughout the entire region in the radial direction in the central portion in the thickness direction.
  • Such an epitaxial silicon wafer having the oxygen precipitate density is excellent in gettering ability throughout the entire surface of the wafer.
  • the silicon wafer that is used in the production method of the present invention contains no dislocation cluster and no COP, and therefore, an epitaxial defect such as a stacking fault with a dislocation cluster or a COP as a starting point is prevented or restrained from being introduced into the epitaxial layer.
  • the condition of the thermal treatment (the thermal treatment for increasing the density of the oxygen precipitates) in the preliminary thermal treatment step is determined based on the ratio of the oxygen precipitation suppression region.
  • the ratio of the oxygen precipitation suppression region serves as an indicator of difficulty of occurrence and growth of the oxygen precipitates as the entire wafer. Accordingly, by determining the condition of the thermal treatment in the preliminary thermal treatment step based on the ratio of the oxygen precipitation suppression region, the epitaxial silicon wafer with a high oxygen precipitate density throughout the entire region in the radial direction can be obtained.
  • Such an epitaxial silicon wafer causes oxygen precipitates to grow by thermal treatment in a proper condition, and can have an excellent gettering ability. According to the production method of the present invention, the epitaxial silicon wafer of the present invention can be produced.
  • FIG. 1 is a diagram showing a characteristic of a wafer with an oxygen concentration of 9 ⁇ 10 17 atoms/cm 3 .
  • FIG. 2 is a diagram showing a characteristic of a wafer with an oxygen concentration of 11.5 ⁇ 10 17 atoms/cm 3 .
  • FIG. 3 is a diagram showing a characteristic of a wafer with an oxygen concentration of 12.5 ⁇ 10 17 atoms/cm 3 .
  • FIG. 4 is a diagram showing a characteristic of a wafer with an oxygen concentration of 13.5 ⁇ 10 17 atoms/cm 3 .
  • FIG. 5 is a diagram showing a characteristic of a wafer with an oxygen concentration of 16 ⁇ 10 17 atoms/cm 3 .
  • Presence or absence of a COP can be determined by an evaluation method as follows.
  • a silicon single crystal is grown by the Czochralski (CZ) method, and from the single crystal ingot, a silicon water is cut out.
  • the silicon water cut out from the single crystal ingot is cleaned by SC-1 (a mixed solution obtained by mixing ammonia water, a hydrogen peroxide and ultrapure water at 1:1:15 (volume ratio)).
  • SC-1 a mixed solution obtained by mixing ammonia water, a hydrogen peroxide and ultrapure water at 1:1:15 (volume ratio)
  • the cleaned silicon wafer surface is observed and evaluated by using Surfscan SP-2 manufactured by KLA-Tenchor corporation as a surface defect inspection device, and light point defects (LPD: Light Point Defect) assumed to be pits (recessed portions) formed on the surface are determined.
  • LPD Light Point Defect
  • an observation mode is set at an Oblique mode (an oblique incident mode), and assumption of whether or not the light point defects are pits is made based on a detection size ratio of a Wide Narrow channel.
  • Evaluation of whether a COP or not is performed for the LPD determined in this way by using an atomic force microscope (AFM: Atomic Force Microscope).
  • AFM Atomic Force Microscope
  • the shape of the pit forms a part of an octahedron
  • the pit is determined as a COP.
  • presence or absence of a COP can be determined. Accordingly, whether or not a silicon wafer is a silicon wafer “containing no COP” can be determined by the above described evaluation method.
  • the silicon wafer “containing no dislocation cluster” means that the silicon wafer does not contain a defect that becomes evident by etching such as secco etching or Cu decoration and can be recognized at a visual level.
  • the silicon water that contains no COP or no dislocation cluster includes an oxygen precipitation suppression region (Pi region) and an oxygen precipitation promotion region (Pv region).
  • the Pi region refers to a crystal region in which a density of oxygen precipitates observed in a center of a thickness direction by an optical microscope is less than 1 ⁇ 10 4 /cm 2 when thermal treatment that heats the silicon wafer at 1000° C. for 16 hours under oxidative gas atmosphere (hereinafter referred to as “oxygen precipitate evaluation thermal treatment”) is performed, thereafter, the silicon wafer is cleaved so that a section along the thickness direction becomes visible, and a surface layer portion of the section is removed by a thickness of 2 ⁇ m by Wright etching (with use of a chromic acid).
  • the Pv region refers to a crystal region in which the density of oxygen precipitates is 1 ⁇ 10 4 /cm 2 or more when observation similar to the observation at the time of evaluating whether or not the crystal region is a Pi region in accordance with the definition of the above described Pi region is performed.
  • An OSF (Oxidation induced Stacking Fault) region (a region containing plate-like oxygen precipitates (OSF nuclei) that become evident as OSF at 1000 to 1200° C. in an as-grown state) is also comprehended in the Pv region as long as the requirement is satisfied.
  • the epitaxial silicon wafer of the present invention has an epitaxial layer on the surface of a silicon water that contains no dislocation cluster and no COP.
  • a density of oxygen precipitates in a central portion in a thickness direction of the silicon wafer is 5 ⁇ 10 4 /cm 2 or more throughout an entire region in a radial direction of the silicon wafer.
  • the epitaxial silicon wafer of the present invention can have the oxygen precipitate density of 5 ⁇ 10 4 /cm 2 or more throughout the entire region in the radial direction in the central portion in the thickness direction.
  • Such an epitaxial silicon wafer having the oxygen precipitates with the density is excellent in gettering ability throughout the entire surface.
  • the method for producing an epitaxial silicon wafer of the present invention includes a preliminary thermal treatment step of performing thermal treatment for increasing a density of oxygen precipitates, for a silicon wafer that has an oxygen concentration in a range of 9 ⁇ 10 17 atoms/cm 3 to 16 ⁇ 10 17 atoms/cm 3 , contains no dislocation cluster and no COP, and contains an oxygen precipitation suppression region, and an epitaxial layer forming step of forming an epitaxial layer on a surface of the silicon wafer after the preliminary thermal treatment step.
  • the production method further includes a thermal treatment condition determining step of determining a thermal treatment condition in the preliminary thermal treatment step, based on a ratio of the oxygen precipitation suppression region of the silicon wafer before the preliminary thermal treatment step is carried out.
  • oxygen concentration is by ASTM F121-1979.
  • the silicon wafer for which thermal treatment is performed in the preliminary thermal treatment step may be a silicon wafer in which the oxygen precipitation suppression region and the oxygen precipitation promotion region coexist. Consequently, at the time of production of the silicon single crystal from which the silicon wafer should be cut out, the control process margin width can be made large.
  • the silicon wafer for which thermal treatment is performed in the preliminary thermal treatment step may be formed of only the oxygen precipitation suppression region.
  • the oxygen concentration of the silicon wafer before the preliminary thermal treatment step is carried out is 9 ⁇ 10 17 atoms/cm 3 or more, the density of the oxygen precipitates can be increased by the preliminary thermal treatment not only in the oxygen precipitation promotion region but also in the oxygen precipitation suppression region.
  • the oxygen concentration of the silicon wafer before the preliminary thermal treatment step is carried out is higher than 16 ⁇ 10 17 atoms/cm 3 , oxygen precipitation becomes excessive, and the oxygen precipitates are formed on the wafer surface side where the epitaxial layer is formed, so that there arises the fear of occurrence of epitaxial defects due to the oxygen precipitates.
  • oxygen precipitates do not disappear, even when the silicon wafer is heated in the epitaxial layer forming step, and by heating the silicon wafer in the proper condition after the epitaxial layer forming step is carried out, the oxygen precipitates are formed with the density of 5 ⁇ 10 4 /cm 2 or more throughout the entire region in the radial direction in the central portion in the thickness direction of the wafer. Consequently, according to the method of the present invention, the epitaxial silicon wafer excellent in gettering ability throughout the entire surface can be produced.
  • a time period (a time period in which a predetermined thermal treatment temperature is kept; hereinafter referred to as “a preliminary thermal treatment keeping time period”) of the thermal treatment in the preliminary thermal treatment step may be set in a range of substantially 0.5 to 16 hours, in accordance with the oxygen precipitate density which is a target.
  • the reason why the time period in this range is preferable as the preliminary thermal treatment keeping time period is as follows.
  • the preliminary thermal treatment keeping time period is less than 0.5 hours, growth of the oxygen precipitates in the oxygen precipitation suppression region is insufficient, and the oxygen precipitates disappear by the high-temperature thermal treatment in the epitaxial layer forming step.
  • oxygen precipitates become excessive, and epitaxial defects (stacking faults) with the oxygen precipitates present on the wafer surface as starting points easily occur.
  • a silicon epitaxial layer is cited.
  • the method for forming the epitaxial layer is not specially limited, and the epitaxial layer can be formed in an ordinary condition by a CVD method or the like, for example.
  • a source gas such as dichlorosilane and trichlorosilane
  • hydrogen gas as a carrier gas
  • the silicon epitaxial layer can be grown on the silicon wafer by the CVD method at a temperature (a growth temperature) in a range of substantially 1000 to 1200° C.
  • the growth temperature differs in accordance with the kind of the source gas to be used.
  • the thickness of the epitaxial layer is preferably within a range of 0.5 to 15 ⁇ m.
  • the thermal treatment condition in the preliminary thermal treatment step is preferably determined so as to satisfy any one of the following relational expressions (1) to (3).
  • T a temperature (° C.) of the thermal treatment in the preliminary thermal treatment step
  • X a ratio (%) of a width of the oxygen precipitation suppression region in a radial direction of the silicon wafer to a radius of the silicon wafer
  • Co an oxygen concentration (atoms/cm 3 ) of the silicon wafer
  • a plurality of silicon single crystals with diameters of approximately 300 mm that contain no COP and no dislocation cluster were produced by the Czochralski method, and silicon wafers were cut out from respective sites of these silicon single crystals.
  • growth conditions were changed so that ratios of oxygen concentrations and oxygen precipitation suppression regions differ variously.
  • Table 1 shows the ratios of the oxygen concentrations and the oxygen precipitation suppression regions of the obtained silicon wafers.
  • the ratio of the oxygen precipitation suppression region is shown by a ratio (%; hereinafter referred to as “a Pi ratio”) of a width of the oxygen precipitation suppression region in the radial direction of the silicon wafer to a radius of the silicon wafer.
  • a Pi ratio a ratio of a width of the oxygen precipitation suppression region in the radial direction of the silicon wafer to a radius of the silicon wafer.
  • Thermal treatment (preliminary thermal treatment) was performed for these silicon wafers for 16 hours with the temperatures being changed.
  • the temperatures of the thermal treatment are shown in Table 1.
  • the respective silicon wafers were transferred into a single-wafer epitaxial growth apparatus (made by Applied Materials, Inc.), hydrogen bake treatment for 30 seconds was performed at a temperature of 1120° C. in the apparatus, and thereafter, silicon epitaxial layers of a thickness of 4 ⁇ m were grown on the silicon wafers by a CVD method at 1150° C. with hydrogen as carrier gas and a trichlorosilane as source gas, whereby epitaxial silicon wafers were obtained.
  • oxygen precipitate evaluation thermal treatment for 16 hours was performed at 1000° C. for these epitaxial silicon wafers.
  • these epitaxial silicon wafers were cleaved at surfaces including centers of the wafers in the thickness directions of the wafers, the cleaved surfaces were etched by 2 ⁇ m with a light etching solution, and densities of pits that became evident on the etched surfaces were measured by an optical microscope with a 500-fold magnification, and were determined as oxygen precipitate densities. Measurement of the oxygen precipitate densities was performed at a plurality of sites along the radial directions of the wafers.
  • FIGS. 1 to 5 illustrate characteristics of the wafers according to the respective oxygen concentrations.
  • Each of the drawings illustrates a relation between an inverse number of the temperature T (i.e. 1/T (/° C.)) of the preliminary thermal treatment and a 100-Pi ratio, and whether or not the oxygen precipitate density after the oxygen precipitate evaluation thermal treatment is 5 ⁇ 10 4 /cm 2 or more throughout the wafer entire surface.
  • 1/T is plotted on a horizontal axis (values of T (a numeric value assigned with “° C.”) are shown in addition)
  • the 100-Pi ratio that is, the ratio of the region which is not a Pi region is plotted in a vertical axis.
  • hatching is applied to the condition region where the oxygen precipitate density is 5 ⁇ 10 4 /cm 2 or more throughout the entire surface of the wafer.
  • the condition region (hereinafter, referred to as “a high BMD concentration condition region”) where the oxygen precipitate density is 5 ⁇ 10 4 /cm 2 or more throughout the entire surface of the wafer is at a high temperature side from a curve sloping from right to left (a left side in each of the drawings), and is at a low temperature side (a right side in each of the drawings) from a straight line perpendicular to the horizontal axis. That is, at least parts of these lines form boundaries between the high BMD concentration condition region and the other regions.
  • a temperature range in which the oxygen precipitate density after the oxygen precipitate evaluation thermal treatment is 5 ⁇ 10 4 /cm 2 or more throughout the entire surface of the wafer with the temperature T (° C.) of the preliminary thermal treatment is as follows.
  • X represents the Pi ratio.
  • the temperature range is (Co ⁇ (100 ⁇ X)/5.3 ⁇ 10 51 ) ( ⁇ 1/11.29) ⁇ T ⁇ 800 (1).
  • the temperature range is (Co ⁇ (100 ⁇ X)/5.3 ⁇ 10 51 ) ( ⁇ 1/11.29) ⁇ T ⁇ 900 ⁇ (13.5 ⁇ 10 17 ⁇ Co) ⁇ 5 ⁇ 10 ⁇ 16 (2).
  • the temperature range is (Co ⁇ (100 ⁇ X)/5.3 ⁇ 10 51 ) ( ⁇ 1/11.29) ⁇ T ⁇ 900 (3).
  • the temperature T of the thermal treatment before epitaxial layer formation is determined in accordance with any expression of (1) to (3) described above according to the oxygen concentration Co of the wafer and the Pi ratio X, whereby the epitaxial silicon wafer in which the oxygen precipitate density after oxygen precipitate evaluation thermal treatment is 5 ⁇ 10 4 /cm 2 or more can be produced throughout the entire surface of the wafer.
  • Such an epitaxial silicon wafer has a high gettering ability.
  • the densities of the LPD Observed on the surface of the epitaxial layer were measured. More specifically, with respect to the epitaxial layer surfaces of the respective epitaxial silicon wafers, measurement of LPD was performed in a Normal mode by using Surfscan SP1 made by KLA-Tencor corporation as an LPD evaluation device, and defects that were counted as LPD-N out of defects counted as LPDs of 90 nm or more were detected as epitaxial defects. As a result, it has been confirmed that the number of epitaxial defects of each of the epitaxial silicon wafers is 10 or less per wafer, and the number of epitaxial defects is small.

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Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014141551A JP6241381B2 (ja) 2014-07-09 2014-07-09 エピタキシャルシリコンウェーハの製造方法
JP2014-141551 2014-07-09
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994761A (en) 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
WO2003009365A1 (fr) 2001-07-10 2003-01-30 Shin-Etsu Handotai Co.,Ltd. Procede de fabrication d'une plaquette en silicium, d'une plaquette epitaxiale en silicium, et plaquette epitaxiale en silicium
US20100078767A1 (en) 2008-09-29 2010-04-01 Park Jung-Goo Silicon wafer and fabrication method thereof
JP2010087512A (ja) 2008-09-29 2010-04-15 Magnachip Semiconductor Ltd シリコンウエハ及びその製造方法
US20100290971A1 (en) * 2009-05-15 2010-11-18 Wataru Itou Silicon wafer and method for producing the same
JP2011243923A (ja) 2010-05-21 2011-12-01 Sumco Corp シリコンウェーハの製造方法
US8890291B2 (en) 2009-03-25 2014-11-18 Sumco Corporation Silicon wafer and manufacturing method thereof
US20160247694A1 (en) 2015-02-25 2016-08-25 Sumco Corporation Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method
US9502266B2 (en) 2010-02-08 2016-11-22 Sumco Corporation Silicon wafer and method of manufacturing thereof, and method of manufacturing semiconductor device
US20160377554A1 (en) 2015-06-26 2016-12-29 Sumco Corporation Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4682508B2 (ja) * 2003-11-14 2011-05-11 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
JP2006054350A (ja) * 2004-08-12 2006-02-23 Komatsu Electronic Metals Co Ltd 窒素ドープシリコンウェーハとその製造方法
JP5163459B2 (ja) * 2008-12-05 2013-03-13 株式会社Sumco シリコン単結晶の育成方法及びシリコンウェーハの検査方法
DE102010034002B4 (de) * 2010-08-11 2013-02-21 Siltronic Ag Siliciumscheibe und Verfahren zu deren Herstellung

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030196586A1 (en) 1997-02-26 2003-10-23 Memc Electronic Materials, Inc. Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US5994761A (en) 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6204152B1 (en) 1997-02-26 2001-03-20 Memc Electronic Materials, Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
JP2001509319A (ja) 1997-02-26 2001-07-10 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 理想的な酸素析出シリコンウエハおよびそれのための酸素外方拡散の無い方法
US6306733B1 (en) 1997-02-26 2001-10-23 Memc Electronic Materials, Spa Ideal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
US20020026893A1 (en) 1997-02-26 2002-03-07 Robert Falster Ideal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
US6586068B1 (en) 1997-02-26 2003-07-01 Memc Electronic Materials, Inc. Ideal oxygen precipitating silicon wafer having an asymmetrical vacancy concentration profile and a process for the preparation thereof
US6180220B1 (en) 1997-02-26 2001-01-30 Memc Electronic Materials, Inc. Ideal Oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
WO2003009365A1 (fr) 2001-07-10 2003-01-30 Shin-Etsu Handotai Co.,Ltd. Procede de fabrication d'une plaquette en silicium, d'une plaquette epitaxiale en silicium, et plaquette epitaxiale en silicium
JP2010087512A (ja) 2008-09-29 2010-04-15 Magnachip Semiconductor Ltd シリコンウエハ及びその製造方法
US20100078767A1 (en) 2008-09-29 2010-04-01 Park Jung-Goo Silicon wafer and fabrication method thereof
US20110227202A1 (en) 2008-09-29 2011-09-22 Magnachip Semiconductor, Ltd. Silicon wafer and fabrication method thereof
US20130270681A1 (en) 2008-09-29 2013-10-17 Magnachip Semiconductor, Ltd. Silicon wafer and fabrication method thereof
US8890291B2 (en) 2009-03-25 2014-11-18 Sumco Corporation Silicon wafer and manufacturing method thereof
US20100290971A1 (en) * 2009-05-15 2010-11-18 Wataru Itou Silicon wafer and method for producing the same
US9502266B2 (en) 2010-02-08 2016-11-22 Sumco Corporation Silicon wafer and method of manufacturing thereof, and method of manufacturing semiconductor device
JP2011243923A (ja) 2010-05-21 2011-12-01 Sumco Corp シリコンウェーハの製造方法
US20160247694A1 (en) 2015-02-25 2016-08-25 Sumco Corporation Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method
US20160377554A1 (en) 2015-06-26 2016-12-29 Sumco Corporation Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Search Report issued in WIPO Patent Application No. PCT/JP2015/002157, dated Jul. 28, 2015.

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