US10186198B2 - Gate driving circuit - Google Patents

Gate driving circuit Download PDF

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Publication number
US10186198B2
US10186198B2 US14/834,015 US201514834015A US10186198B2 US 10186198 B2 US10186198 B2 US 10186198B2 US 201514834015 A US201514834015 A US 201514834015A US 10186198 B2 US10186198 B2 US 10186198B2
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signal
node
output
gate
control
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US20160203762A1 (en
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JongHee KIM
Youngwan Seo
Jaekeun Lim
Chongchul Chai
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAI, CHONGCHUL, KIM, JONGHEE, LIM, JAEKEUN, SEO, YOUNGWAN
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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Definitions

  • Exemplary embodiments relate to a gate driving circuit. More particularly, exemplary embodiments relate to a gate driving circuit integrated on a display panel.
  • a display device typically includes gate lines, data lines, and pixels. Each of the pixels is connected to a corresponding gate line of the gate lines and a corresponding data line of the data lines.
  • the display device includes a gate driving circuit to control the gate lines and a data driving circuit to control the data lines.
  • the gate driving circuit applies gate signals to the gate lines, respectively, and a data driving circuit applies data signals to the data lines, respectively.
  • the gate driving circuit may include a shift register configured to include driving stage circuits, e.g., driving stages. Each driving stage outputs the gate signal corresponding to the gate line. Each driving stage includes transistors connected to each other.
  • Exemplary embodiments provide a gate driving circuit having improved capability and reliability.
  • An exemplary embodiment discloses a gate driving circuit including a plurality of driving stages driving a plurality of gate lines included in a display panel.
  • a first driving stage which drives a first gate line of the gate lines, includes a first output transistor outputting a first carry signal on the basis of a first clock signal in response to a voltage of a first node, a second output transistor outputting a first gate signal on the basis of the first clock signal in response to the voltage of the first node, a first control transistor applying a second clock signal having a phase different from a phase of the first clock signal to a second node, a second control transistor applying a start signal to the first node in response to a voltage of the second node, and a third control transistor applying a first discharge voltage to the first node in response to the first carry signal.
  • An exemplary embodiment also discloses a gate driving circuit including a plurality of driving stages respectively driving a plurality of gate lines included in a display panel.
  • a first driving stage includes an output part outputting a first carry signal and a first gate signal, which are generated on the basis of a clock signal, in response to a voltage of a first node, an inverter part outputting a switching signal of a second node in response to the clock signal, a pull-down part decreasing the first carry signal and the first gate signal in response to a second carry signal, which is provided from a second driving stage applied with the first carry signal among the driving stages, and the switching signal, and a control part receiving a start signal from an external source and controlling the voltage of the first node in response to the start signal, the first carry signal, and the switching signal.
  • the control part charges the voltage of the first node in response to the switching signal and the start signal.
  • FIG. 1 is a plan view showing a display device according to an exemplary embodiment.
  • FIG. 2 is a timing diagram showing signals used in a display device according to an exemplary embodiment.
  • FIG. 3 is an equivalent circuit diagram showing one pixel of pixels shown in FIG. 1 .
  • FIG. 4 is a cross-sectional view showing one pixel of pixels shown in FIG. 1 .
  • FIG. 5 is a block diagram showing a gate driving circuit shown in FIG. 1 .
  • FIG. 6 is a circuit diagram showing a third driving stage of driving stages shown in FIG. 5 .
  • FIG. 7 is a waveform diagram showing input and output signals of the third driving stage shown in FIG. 6 .
  • FIG. 8 is a circuit diagram showing a first driving stage of driving stages shown in FIG. 5 .
  • FIG. 9 is a waveform diagram showing an operation of the first driving stage shown in FIG. 8 .
  • FIG. 10 is a circuit diagram showing a first driving stage according to another exemplary embodiment.
  • FIG. 11 is a block diagram showing a display device according to another exemplary embodiment.
  • an element or layer When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.
  • “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ.
  • Like numbers refer to like elements throughout.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • first, second, etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and/or section from another element, component, region, layer, and/or section. Thus, a first element, component, region, layer, and/or section discussed below could be termed a second element, component, region, layer, and/or section without departing from the teachings of the present disclosure.
  • Spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for descriptive purposes, and, thereby, to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the drawings.
  • Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features.
  • the exemplary term “below” can encompass both an orientation of above and below.
  • the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.
  • exemplary embodiments are described herein with reference to sectional illustrations that are schematic illustrations of idealized exemplary embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
  • the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting.
  • FIG. 1 is a plan view showing a display device according to an exemplary embodiment
  • FIG. 2 is a timing diagram showing signals used in a display device according to an exemplary embodiment.
  • the display device 100 includes a display panel DP, a gate driving circuit 110 , and a data driving circuit 120 .
  • the display panel DP may be one of various types of display panels, including but not limited to, a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, an electrowetting display panel, and the like.
  • a liquid crystal display panel will be described as the display panel DP, but the display panel DP is not limited to the liquid crystal display panel.
  • the liquid crystal display device including the liquid crystal display panel, may further include a polarizer (not shown) and a backlight unit (not shown).
  • the display panel DP includes a first substrate DS 1 , a second substrate DS 2 spaced apart from the first substrate DS 1 , and a liquid crystal layer (not shown) disposed between the first and second substrates DS 1 and DS 2 .
  • the display panel DP includes a display area DA, in which a plurality of pixels PX 11 to PXnm are disposed, and a non-display area NDA surrounding the display area DA.
  • the display panel DP includes a plurality of gate lines GL 1 to GLn and a plurality of data lines DL 1 to DLm, which are disposed on the first base substrate DS 1 .
  • the gate lines GL 1 to GLn cross the data lines DL 1 to DLm.
  • the gate lines GL 1 to GLn are connected to the gate driving circuit 110 .
  • the data lines DL 1 to DLm are connected to the data driving circuit 120 .
  • Each of the pixels PX 11 to PXnm is connected to a corresponding gate line of the gate lines GL 1 to GLn and a corresponding data line of the data lines DL 1 to DLm.
  • the pixels PX 11 to PXnm are grouped into a plurality of groups according to colors displayed thereby.
  • Each of the pixels PX 11 to PXnm displays one of primary colors.
  • the primary colors may include, but not limited to, a red color, a green color, a blue color, and a white color. That is, the primary colors may further include various colors, e.g., yellow, cyan, magenta, etc.
  • the display panel DP may further include a dummy gate line disposed in the non-display area NDA of the first substrate DS 1 .
  • the dummy gate line is not connected to the pixels PX 11 to PXnm and is connected to the gate driving circuit 110 .
  • the gate driving circuit 110 and the data driving circuit 120 receive control signals from a signal controller SC, e.g., a timing controller.
  • the signal controller SC is mounted on a main circuit board MCB.
  • the signal controller SC receives image signals and control signals from an external graphic controller (not shown).
  • the control signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal, and clock signals.
  • the vertical synchronization signal Vsync serves as a signal to indicate distinct frame periods Fn ⁇ 1, Fn, and Fn+1.
  • the horizontal synchronization signal Hsync serves as a row distinction signal to indicate distinct horizontal periods HP.
  • the data enable signal DE is maintained at a high level during a period, in which data are output, to indicate a data input period.
  • the clock signals serve as toggle signals at a predetermined period.
  • the gate driving circuit 110 generates gate signals GS 1 to GSn in response to the control signal (hereinafter, referred to as a gate control signal) provided from the signal controller SC during the frame periods Fn ⁇ 1, Fn, and Fn+1, and applies the gate signals GS 1 to GSn to the gate lines GL 1 to GLn.
  • the gate signals GS 1 to GSn are sequentially output to correspond to the horizontal periods HP.
  • the gate driving circuit 110 may be substantially simultaneously formed together with the pixels PX 11 to PXnm through a thin film process.
  • the gate driving circuit 110 may be mounted on the non-display area NDA in one of an amorphous silicon TFT gate driver circuit (ASG) form or an oxide semiconductor TFT gate driver circuit (OSG) form.
  • ASG amorphous silicon TFT gate driver circuit
  • OSG oxide semiconductor TFT gate driver circuit
  • the display device 100 may include two or more gate driving circuits.
  • One gate driving circuit of the two gate driving circuits is connected to one end of each of the gate lines GL 1 to GLn, and the other gate driving circuit of the two gate driving circuits is connected to the other end of each of the gate lines GL 1 to GLn.
  • one gate driving circuit of the two gate driving circuits may be connected to odd-numbered gate lines of the gate lines GL 1 to GLn and the other gate driving circuit of the two gate driving circuits may be connected to even-numbered gate lines of the gate lines GL 1 to GLn.
  • the data driving circuit 120 generates grayscale voltages corresponding to the image data provided from the signal controller SC in response to the control signal (hereinafter, referred to as a data signal) provided from the signal controller SC.
  • the data driving circuit 120 applies the grayscale voltages to the data lines DL 1 to DLm as data voltages DS.
  • the data voltages DS include positive (+) data voltages having a positive polarity with respect to a common voltage and/or negative ( ⁇ ) data voltage having a negative polarity with respect to the common voltage.
  • a portion of the data voltages applied to the data lines DL 1 to DLm during each horizontal period HP has a positive polarity
  • the other portion of the data voltages applied to the data lines DL 1 to DLm during each horizontal period HP has a negative polarity.
  • the polarity of the data voltages DS is inverted according to the frame periods Fn ⁇ 1, Fn, and Fn+1 to prevent liquid crystals from burning and deteriorating.
  • the data driving circuit 120 generates the data voltages inverted in the unit of frame period in response to an inversion signal.
  • the data driving circuit 120 includes a driving chip 121 and a flexible circuit board 122 on which the driving chip 121 is mounted. Each of the driving chip 121 and the flexible circuit board 122 may be provided in a plural number.
  • the flexible circuit board 122 electrically connects the main circuit board MCB and the first substrate DS 1 .
  • Each of the driving chips 121 drives a corresponding data line of the data lines DL 1 to DLm.
  • Each of the driving chips 121 applies a corresponding data voltage of the data voltages to a corresponding data line of the data lines DL 1 to DLm.
  • each driving chip 121 may drive at least two data lines of the data lines DL 1 to DLm.
  • the data driving circuit 120 may be provided in a tape carrier package (TCP) form, but it should not be limited thereto or thereby. That is, the data driving circuit 120 may be mounted on the first substrate DS 1 in a chip-on-glass (COG) form to correspond to the non-display area NDA.
  • TCP tape carrier package
  • COG chip-on-glass
  • FIG. 3 is an equivalent circuit diagram showing one pixel PXij of the pixels PX 11 to PXnm shown in FIG. 1
  • FIG. 4 is a cross-sectional view showing one pixel PXij of the pixels PX 11 to PXnm shown in FIG. 1 .
  • Each of the pixels PX 11 to PXnm shown in FIG. 1 may have substantially the same structure shown in FIGS. 3 and 4 .
  • the pixel PXij includes a pixel thin film transistor TR (hereinafter, referred to as a pixel transistor), a liquid crystal capacitor Clc, and a storage capacitor Cst.
  • a pixel transistor pixel thin film transistor
  • the term “transistor” as used herein means a thin film transistor
  • the storage capacitor Cst may be omitted.
  • the pixel transistor TR is electrically connected to an i-th gate line GLi and a j-th data line DLj.
  • the pixel transistor TR includes a control electrode electrically connected to the i-th gate line GLi and an input electrode electrically connected to the j-th data line DLj.
  • the pixel transistor TR outputs a pixel voltage corresponding to the data signal provided from the j-th data line DLj in response to the gate signal provided from the i-th gate line GLi.
  • the liquid crystal capacitor Clc is electrically connected to an output electrode of the pixel transistor TR and charged with the pixel voltage output from the pixel transistor TR.
  • An alignment of liquid crystal directors included in the liquid crystal layer LCL is changed in accordance with an amount of electric charges charged in the liquid crystal capacitor Clc. A light incident to the liquid crystal layer LCL transmits through or is blocked by the alignment of the liquid crystal directors.
  • the storage capacitor Cst is connected in parallel with the liquid crystal capacitor Clc.
  • the storage capacitor Cst maintains the alignment of the liquid crystal directors for a predetermined period.
  • the pixel transistor TR includes the control electrode GE connected to the i-th gate line GLi, an active part AL overlapped with the control electrode GE, the input electrode SE connected to the j-th data line DLj, and the output electrode DE spaced apart from the input electrode SE.
  • the liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE.
  • the storage capacitor Cst includes the pixel electrode PE and a portion of a storage line STL.
  • the i-th gate line GLi and the storage line STL are disposed on an upper surface of the first substrate DS 1 .
  • the control electrode GE is branched from the i-th gate line GLi.
  • the i-th gate line GLi and the storage line STL include a metal material, such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), or an alloy thereof.
  • Each of the i-th gate line GLi and the storage line STL has a multi-layer structure of a titanium layer and a copper layer.
  • a first insulating layer 10 is disposed on the first substrate DS 1 to cover the control electrode GE and the storage line STL.
  • the first insulating layer 10 includes at least one of an inorganic material and an organic material.
  • the first insulating layer 10 is an organic or inorganic layer.
  • the first insulating layer 10 has a multi-layer structure of a silicon nitride layer and a silicon oxide layer.
  • the active part AL is disposed on the first insulating layer 10 to overlap with the control electrode GE.
  • the active part AL includes a semiconductor layer and an ohmic contact layer.
  • the semiconductor layer is disposed on the first insulating layer 10
  • the ohmic contact layer is disposed on the semiconductor layer.
  • the semiconductor layer includes amorphous silicon or polysilicon.
  • the semiconductor layer may include a metal oxide semiconductor.
  • the ohmic contact layer is highly doped with a dopant than the semiconductor layer.
  • the ohmic contact layer may include two portions spaced apart from each other. In the present exemplary embodiment, the ohmic contact layer may be integrally formed in a single unitary and individual unit.
  • the output electrode DE and the input electrode SE are disposed on the active part AL.
  • the output electrode DE and the input electrode SE are spaced apart from each other.
  • Each of the output electrode DE and the input electrode SE is partially overlapped with the control electrode GE.
  • the output electrode DE and the input electrode SE are disposed on the active part AL.
  • the output electrode DE is completely overlapped with one portion of the active part AL and the input electrode SE is completely overlapped with the other portion of the active part AL.
  • a second insulating layer 20 is disposed on the first insulating layer 10 to cover the active part AL, the output electrode DE, and the input electrode SE.
  • the second insulating layer 20 includes an inorganic or organic material.
  • the second insulating layer 20 is an organic or inorganic layer.
  • the second insulating layer 20 has a multi-layer structure of a silicon nitride layer and a silicon oxide layer.
  • FIG. 4 shows the pixel transistor TR having a staggered structure, but the structure of the pixel transistor TR should not be limited to the staggered structure. That is, the pixel transistor TR may have a planar structure.
  • a third insulating layer 30 is disposed on the second insulating layer 20 .
  • the third insulating layer 30 provides a level surface.
  • the third insulating layer 30 includes an organic material.
  • the pixel electrode PE is disposed on the third insulating layer 30 .
  • the pixel electrode PE is connected to the output electrode DE through a contact hole CH formed through the second and third insulating layer 20 and 30 .
  • An alignment layer (not shown) may be disposed on the third insulating layer 20 to cover the pixel electrode PE.
  • a color filter layer CF is disposed on a surface of the second substrate DS 2 .
  • the common electrode CE is disposed on the color filter layer CF.
  • the common electrode CE is applied with a common voltage.
  • the common voltage has a level different from that of the pixel voltage.
  • An alignment layer (not shown) may be disposed on the common electrode CE to cover the common electrode CE.
  • Another insulating layer may be disposed between the color filter layer CF and the common electrode CE.
  • the pixel electrode PE and the common electrode CE which face each other such that the liquid crystal layer LCL is disposed between the pixel electrode PE and the common electrode CE, form the liquid crystal capacitor Clc.
  • the pixel electrode PE and the portion of the storage line STL which face each other such that the first, second, and third insulating layers 10 , 20 , and 30 are disposed between the pixel electrode PE and the portion of the storage line STL, form the storage capacitor Cst.
  • the storage line STL is applied with a storage voltage having a level different from that of the pixel voltage.
  • the storage voltage may have the same level as that of the common voltage.
  • the liquid crystal display panel may include a vertical alignment (VA) mode pixel, a patterned vertical alignment (PVA) mode pixel, an in-plane switching (IPS) mode pixel, a fringe-field switching (FFS) mode pixel, or a plane-to-line switching (PLS) mode pixel.
  • VA vertical alignment
  • PVA patterned vertical alignment
  • IPS in-plane switching
  • FFS fringe-field switching
  • PLS plane-to-line switching
  • FIG. 5 is a block diagram showing the gate driving circuit shown in FIG. 1 .
  • the gate driving circuit 110 includes a plurality of driving stages SRC 1 to SRCn connected to each other one after another.
  • a first driving stage SRC 1 corresponds to a first driving stage of the driving stages SRC 1 to SRCn, and the first to n-th driving stages are sequentially connected to each other in series, but they should not be limited thereto or thereby.
  • the driving stages SRC 1 to SRCn are respectively connected to the gate lines GL 1 to GLn.
  • the driving stages SRC 1 to SRCn apply the gate signals to the gate lines GL 1 to GLn, respectively.
  • the gate lines connected to the driving stages SRC 1 to SRCn may be odd-numbered gate lines and even-numbered gate lines among the gate lines GL 1 to GLn.
  • the gate driving circuit 110 may further include a dummy stage SRC-D 1 connected to a last driving stage SRCn among the driving stages SRC 1 to SRCn.
  • the dummy stage SRC-D 1 is connected to a dummy gate line GL-D 1 .
  • the number of the dummy stages SRC-D 1 may be increased or decreased. When the number of the dummy stages SRC-D 1 is changed, the number of the dummy gate lines GL-D 1 is changed.
  • the dummy stages SRC-D 1 may have substantially the same structure as or a different structure from the driving stages SRC 1 to SRCn.
  • Each of the driving stages SRC 1 to SRCn includes an output terminal OUT, a carry terminal CRT, an input terminal IN, a clock terminal CK, a first voltage input terminal V 1 , a second voltage input terminal V 2 , and a control terminal CT.
  • each of the driving stages SRC 1 to SRCn is connected to a corresponding gate line of the gate lines GL 1 to GLn.
  • the gate signals GS 1 to GSn generated by the driving stages SRC 1 to SRCn are applied to the gate lines GL 1 to GLn through the output terminals OUT.
  • the carry terminal CRT of each of the driving stages SRC 1 to SRCn is electrically connected to the input terminal IN of a next driving stage following the corresponding driving stage.
  • the carry terminal CRT of a third driving stage SRC 3 is electrically connected to the input terminal IN of a fourth driving stage SRC 4 right following the third driving stage SRC 3 .
  • the carry terminals CRT of the driving stages SRC 1 to SRCn outputs carry signals CRS 1 to CRSn, respectively.
  • the input terminal IN of each of the driving stages SRC 1 to SRCn receives the carry signal from a previous driving stage prior to the corresponding driving stage.
  • the input terminal IN of the third driving stage SRC 3 receives the carry signal CRS 2 output from a second driving stage SRC 2 .
  • the input terminal IN of the first driving stage SRC 1 receives a start signal STV that starts an operation of the gate driving circuit 110 .
  • the control terminal CT of each of the driving stages SRC 1 to SRCn receives the carry signal of the next driving stage following the corresponding driving stage.
  • the control terminal CT of the third driving stage SRC 3 receives a fourth carry signal CRS 4 output from the fourth driving stage SRC 4 .
  • the control terminal CT of the dummy stage SRC-D 1 receives the start signal STV.
  • the clock terminal CK of each of the driving stages SRC 1 to SRCn receives a first clock signal CKV or a second clock signal CKVB.
  • the clock terminals CK of the odd-numbered driving stages SRC 1 , SRC 3 , and SRC 5 among the driving stages SRC 1 to SRCn receive the first clock signal CKV.
  • the clock terminals CK of the even-numbered driving stages SRC 2 , SRC 4 , and SRCn among the driving stages SRC 1 to SRCn receive the second clock signal CKVB.
  • the first and second clock signals CKV and CKVB have different phases from each other.
  • the second clock signal CKVB is obtained by inverting the first clock signal CKV.
  • the first voltage input terminal V 1 of each of the driving stages SRC 1 to SRCn receives a first discharge voltage VSS 1 and the second voltage input terminal V 2 of each of the driving stages SRC 1 to SRCn receives a second discharge voltage VSS 2 .
  • the second discharge voltage VSS 2 may have the voltage level lower than that of the first discharge voltage VSS 1 .
  • each of the driving stages SRC 1 to SRCn one of the output terminal OUT, the input terminal IN, the carry terminal CRT, the control terminal CT, the clock terminal CK, the first voltage input terminal V 1 , and the second voltage input terminal V 2 may be omitted or another terminal may be added to each of the driving stages SRC 1 to SRCn.
  • one of the first and second voltage input terminals V 1 and V 2 may be omitted.
  • a connection relation between the driving stages SRC 1 to SRCn may be changed.
  • the first driving stage SRC 1 has a structure different from the other driving stages SRC 2 to SRCn.
  • each of the second to n-th driving stages SRC 2 to SRCn receives the carry signal from the previous driving stage through the input terminal thereof, but the first driving stage SRC 1 receives the start signal STV through the input terminal IN thereof.
  • each of the second to n-th driving stages SRC 2 to SRCn receives one of the first and second clock signals CKV and CKVB through the clock terminal CK thereof, but the first driving stage SRC 1 further includes a clock bar terminal CKB.
  • the first driving stage SRC 1 receives the first clock signal CKV and the second clock signal CKVB respectively through the clock terminal CK and the clock bar terminal CKB.
  • the start signal STV serves as a signal indicating the start of the operation of the gate driving circuit 110 and is provided from the signal controller SC.
  • the first driving stage SRC 1 generates the first carry signal CRS 1 and the first gate signal GS 1 in response to the first clock signal CKV and precharges a first node NQ with the second clock signal CKVB to generate the first carry signal CRS 1 and the first gate signal GS 1 .
  • the structure and function of the first driving stage SRC 1 will be described in detail later.
  • FIG. 6 is a circuit diagram showing the third driving stage SRC 3 of the driving stages SRC 1 to SRCn shown in FIG. 5 .
  • the third driving stage SRC 3 will be described in detail with reference to FIG. 6 as a representative example, but the other driving stages may have substantially the same circuit diagram as that of the third driving stage SRC 3 .
  • the third driving stage SRC 3 includes output parts 111 - 1 and 111 - 2 , a control part 112 , an inverter part 113 , and pull-down parts 114 - 1 and 114 - 2 .
  • the output parts 111 - 1 and 111 - 2 include a first output part 111 - 1 outputting a third gate signal GS 3 , and a second output part 111 - 2 outputting a third carry signal CRS 3 .
  • the pull-down parts 114 - 1 and 114 - 2 include a first pull-down part 114 - 1 lowering the output terminal OUT and a second pull-down part 114 - 2 lowering the carry terminal CRT.
  • the circuit configuration of the third driving stage SRC 3 should not be limited to the above-mentioned circuit configuration.
  • the first output part 111 - 1 includes a first output transistor TR_O 1 .
  • the first output transistor TR_O 1 includes an input electrode applied with the first clock signal CKV, a control electrode connected to a first node NQ (or control node), and an output electrode outputting the third gate signal GS 3 .
  • the second output part 111 - 2 includes a second output transistor TR 2 _O 2 .
  • the second output transistor TR_O 2 includes an input electrode applied with the first clock signal CKV, a control electrode connected to the first node NQ, and an output electrode outputting the third carry signal CRS 3 .
  • the second output transistor TR_O 2 outputs the third carry signal CRS 3 on the basis of the clock signal CKV in response to a voltage of the first node NQ.
  • the control part 112 controls an operation of the first and second output parts 111 - 1 and 111 - 2 .
  • the control part 112 receives the second carry signal CRS 2 output from the second driving stage SRC 2 , i.e., the previous driving stage, through the input terminal IN thereof.
  • the control part 112 turns on the first and second output parts 111 - 1 and 111 - 2 in response to the second carry signal CRS 2 provided through the control terminal IN.
  • the control part 112 turns off the first and second output parts 111 - 1 and 111 - 2 in response to the fourth carry signal CRS 4 output from the fourth driving stage SRC 4 , i.e., the next driving stage.
  • the control part 112 maintains the turned-off state of the first and second output parts 111 - 1 and 111 - 2 in response to the switching signal.
  • the control part 112 includes a first control transistor TR_C 1 , a second control transistor TR_C 2 , a third control transistor TR_C 3 , and a capacitor CAP.
  • the first control transistor TR_C 1 includes an output electrode connected to the first node NQ, and a control electrode and an input electrode, which are commonly connected to the input terminal IN.
  • the first control transistor TR_C 1 is diode-connected between the input terminal IN and the first node NQ such that a current path is formed between the input terminal IN and the first node NQ.
  • the first control transistor TR_C 1 applies a signal from the input terminal IN, i.e., the second carry signal CRS 2 , to the first node NQ.
  • the first node NQ has an electric potential increasing by the second carry signal CRS 2 provided from the first control transistor TR_C 1 .
  • the capacitor CAP is connected between the control electrode and the output electrode of the first output transistor TR_O 1 of the first output part 111 - 1 and provided between the output terminal OUT and the first node NQ.
  • the second control transistor TR_C 2 is provided between the second voltage input terminal V 2 and the first node NQ.
  • the second control transistor TR_C 2 includes a control electrode connected to the control terminal CT.
  • the second control transistor TR_C 2 applies the second discharge voltage VSS 2 to the first node NQ in response to the fourth carry signal CRS 4 provided from the control terminal CT.
  • the third control transistor TR_C 3 is connected between the second voltage input terminal V 2 and the first node NQ.
  • a control electrode of the third control transistor TR_C 3 is connected to a second node NB, i.e., an output node.
  • the second node NB is connected to an output terminal of the inverter part 130 .
  • the third control transistor TR_C 1 applies the second discharge voltage VSS 2 to the first node NQ in response to the switching signal provided from the inverter part 130 .
  • the number of each of the second and third control transistors TR_C 2 and TR_C 3 may be increased.
  • the second control transistors TR_C 2 are connected to each other in series and the third control transistors TR_C 3 are connected to each other in series.
  • one of the second and third control transistors TR_C 2 and TR_C 3 may be connected to the first voltage input terminal V 1 instead of the second voltage input terminal V 2 .
  • the inverter part 113 outputs the switching signal of the second node NB.
  • the inverter part 113 includes first, second, third, and fourth inverter transistors TR_I 1 , TR_I 2 , TR_I 3 , and TR_I 4 .
  • the first inverter transistor TR_I 1 includes an input electrode and a control electrode, which are commonly connected to the clock terminal CK, and an output electrode connected to a control electrode of the second inverter transistor TR_I 2 .
  • the second inverter transistor TR_I 2 includes an input electrode connected to the clock terminal CK and an output electrode connected to the second node NB.
  • the third inverter transistor TR_I 3 includes an output electrode connected to the output electrode of the first inverter transistor TR_I 1 , a control electrode connected to the carry terminal CRT, and an input electrode connected to the second voltage input terminal V 2 .
  • the fourth inverter transistor TR_I 4 includes an output electrode connected to a third node NC, i.e., a gate node, a control electrode connected to the carry terminal CRT, and an input electrode connected to the second voltage input terminal V 2 .
  • control electrodes of the third and fourth inverter transistors TR_I 3 and TR_I 4 may be connected to the output terminal OUT and the output electrodes of the third and fourth inverter transistors TR_I 3 and TR_I 4 may be connected to the first voltage input terminal V 1 .
  • the first pull-down part 114 - 1 includes a first pull-down transistor TR_D 1 and a second pull-down transistor TR_D 2 .
  • the first pull-down transistor TR_D 1 includes an input electrode connected to the first voltage input terminal V 1 , a control electrode connected to the second node NB, and an output electrode connected to the output terminal OUT.
  • the second pull-down transistor TR_D 2 includes an input electrode connected to the first voltage input terminal V 1 , a control electrode connected to the control terminal CT, and an output electrode connected to the output terminal OUT.
  • at least one of the input electrode of the first pull-down transistor TR_D 1 and the input electrode of the second pull-down transistor TR_D 2 may be connected to the second voltage input terminal V 2 .
  • the second pull-down part 114 - 2 includes a third pull-down transistor TR_D 3 and a fourth pull-down transistor TR_D 4 .
  • the third pull-down transistor TR_D 3 includes an input electrode connected to the second voltage input terminal V 2 , a control electrode connected to the second node NB, and an output electrode connected to the carry terminal CRT.
  • the fourth pull-down transistor TR_D 4 includes an input electrode connected to the second voltage input terminal V 2 , a control electrode connected to the control terminal CT, and an output electrode connected to the carry terminal CRT.
  • at least one of the input electrode of the third pull-down transistor TR_D 3 and the input electrode of the fourth pull-down transistor TR_D 4 may be connected to the first voltage input terminal V 1 .
  • FIG. 7 is a waveform diagram showing input and output signals of the third driving stage SRC 3 shown in FIG. 6 .
  • the third driving stage SRC 3 receives the second carry signal CRS 2 from the second driving stage SRC 2 through the input terminal IN.
  • the second carry signal CRS 2 may be a high voltage VH-C during a second horizontal period HP 2 .
  • the first control transistor TR_C 1 of the third driving stage SRC 3 applies the second carry signal CRS 2 having the high voltage VH-C to the first node NQ during the second horizontal period HP 2 .
  • the first node NQ is precharged to a first voltage VQ 1 .
  • the first voltage VQ 1 may be lower than the high voltage VH-C of the second carry signal CRS 2 by a predetermined level.
  • the high voltage VH-C is about 10 volts and a low voltage VL-C is about ⁇ 16 volts.
  • the low voltage VL-C has substantially the same level as that of the second discharge voltage VSS 2 .
  • the second carry signal CRS 2 decreases to the low voltage VL-C and the first clock signal CKV increases to the high voltage VH-C during the third horizontal period HP 3 . Since the first node NQ is precharged to the first voltage VQ 1 in the second horizontal period HP 2 , the first and second output transistors TR_O 1 and TR_O 2 of the third driving stage SRC 3 are in the turn-on state.
  • the first clock signal CKV decreases to the low voltage VL-C and the fourth carry signal CRS 4 increases to the high voltage VH-C during the fourth horizontal period HP 4 .
  • the inverter part 113 of the third driving stage SRC 3 outputs a signal obtained by inverting the first clock signal CKV as a switching signal of the second node NB during the fourth horizontal period HP 4 .
  • the first and second pull-down parts 114 - 1 and 114 - 2 of the third driving stage SRC 3 decreases the third gate signal GS 3 and the third carry signal CRS 3 to the low voltage VL-C during the fourth horizontal period HP 4 in response to the switching signal of the second node NB and the fourth carry signal CRS 4 .
  • the other driving stages SRC 2 and SRC 4 to SRCn output the gate signal and the carry signal.
  • FIG. 8 is a circuit diagram showing the first driving stage SRC 1 of the driving stages SRC 1 to SRCn shown in FIG. 5 .
  • the other driving stages SRC 2 to SRCn may have substantially the same structure of the third driving stage SRC 3 .
  • the first driving stage SRC 1 has a structure different from that of the third driving stage SRC 3 shown in FIG. 6 .
  • different features of the first driving stage SRC 1 from those of the third driving stage SRC 3 will be mainly described.
  • the first driving stage SRC 1 includes output parts 1110 - 1 and 1110 - 2 , a control part 1120 , an inverter part 1130 , and pull-down parts 1140 - 1 and 1140 - 2 .
  • the output parts 1110 - 1 and 1110 - 2 include first and second output transistors TR_O 1 and TR_O 2 .
  • the inverter part 1130 includes first to fourth inverter transistors TR_I 1 to TR_I 4 .
  • the pull-down parts 1140 - 1 and 1140 - 2 include first to fourth pull-down transistors TR_D 1 to TR_D 4 .
  • the output parts 1110 - 1 and 1110 - 2 , the inverter part 1130 , and the pull-down parts 1140 - 1 and 1140 - 2 have the same structure and function as those of the output parts 111 - 1 and 111 - 2 , the inverter part 113 , and the pull-down parts 114 - 1 and 114 - 2 of the third driving stage SRC 3 shown in FIG. 6 , and thus, details thereof will be omitted.
  • the control part 1120 includes first to fifth control transistors TR_C 1 to TR_C 5 .
  • the first control transistor TR_C 1 includes an input electrode connected to the input terminal IN, a control electrode connected to the third node NC, and an output electrode connected to the first node NQ.
  • the first control transistor TR_C 1 applies a signal provided from the input terminal IN to the first node NQ in response to a voltage of the third node NC.
  • the first node NQ is precharged to the first voltage VQ 1 by the signal provided through the first control transistor TR_C 1 .
  • the first driving stage SRC 1 receives the start signal STV through the input terminal thereof. That is, the first control transistor TR_C 1 applies the start signal STV to the first node NQ.
  • the second and third control transistors TR_C 2 and TR_C 3 are operated in the above-mentioned operation in FIG. 6 , and thus details thereof will be omitted.
  • the fourth control transistor TR_C 4 includes an output electrode connected to the second node NB and input and control electrodes commonly connected to the inverting clock terminal CKB.
  • the fourth control transistor TR_C 4 is diode-connected between the inverting clock terminal CKB and the third node NC such that a current path is formed between the inverting clock terminal CKB and the third node NC. Accordingly, the first control transistor TR_C 1 is operated in response to the second clock signal CKVB provided through the inverting clock terminal CKB.
  • the fifth control transistor TR_C 5 includes an input electrode connected to the second voltage input terminal V 2 , a control electrode connected to the carry terminal CRT, and an output electrode connected to the third node NC.
  • the fifth control transistor TR_C 5 applies the second discharge voltage VSS 2 provided from the second voltage input terminal V 2 to the third node NC in response to the first carry signal CRS 1 .
  • a first driving stage may be substantially the same structure as the third driving stage SRC 3 shown in FIG. 6 .
  • the start signal STV is delayed by a predetermined time
  • the first node NQ is not sufficiently precharged.
  • the precharging time of the first node NQ is reduced, so that the first node NQ is not precharged to the first voltage VQ 1 . Therefore, the characteristic of the first gate signal output from the output part is degraded.
  • the first control transistor TR_C 1 of the first driving stage SRC 1 included in the gate driving circuit 110 applies the start signal STV to the first node NQ in response to the second clock signal CKVB.
  • the voltage of the first node NQ may be increased to the first voltage VQ 1 .
  • FIG. 9 is a waveform diagram showing an operation of the first driving stage SRC 1 shown in FIG. 8 .
  • the start signal STV maintains the high voltage VH-C during the 0-th horizontal period HP 0 .
  • the start signal STV is delayed by a first time period t 1 . That is, the period in which the start signal STV maintains the high voltage VH-C overlaps with a portion of the 0-th horizontal period HP 0 and a portion of the first horizontal period HP 1 .
  • the horizontal periods are defined as viewed relative to one frame period, and the 0-th horizontal period corresponds to a first horizontal period of each frame period.
  • a first line L 01 indicates the voltage of the first node NQ in the first driving stage SRC 1 and a second line L 02 indicates the voltage of the first node of the first driving stage in the conventional gate driving circuit.
  • the precharging time of the first node NQ of the first driving stage SRC 1 corresponds to the 0-th horizontal period HP 0 in the ideal case.
  • the precharging time period of the first node of the first driving stage SRC 1 is shortened to a second time period t 2 . That is, when the start signal STV is delayed by the first time period t 1 , the precharging time of the first node NQ of the first driving stage SRC 1 is reduced.
  • the first driving stage of the conventional gate driving circuit may have substantially the same structure as that of the third driving stage SRC 3 shown in FIG. 6 .
  • the voltage of the first node may be precharged to a voltage VQ 1 ′ lower than the first voltage VQ 1 due to the control transistor diode-connected between the input terminal and the first node NQ in the first driving stage of the conventional gate driving circuit as represented by the second line L 02 .
  • the first control transistor TR_C 1 of the first driving stage SRC 1 since the first control transistor TR_C 1 of the first driving stage SRC 1 according to the present exemplary embodiment is operated in response to the second clock signal CKVB and applies the start signal STV to the first node NQ, the voltage of the first node NQ may be precharged to the first voltage VQ 1 during the second time period t 2 as represented by the first line L 01 . That is, the voltage of the first node NQ is sufficiently precharged to the first voltage VQ 1 , and thus the output waveform of the first gate signal GS 1 according to the clock signal CKV is improved.
  • the start signal STV decreases to the low voltage VL-C in the first horizontal period HP 1 .
  • the start signal STV may decrease to the low voltage VL-C in the first horizontal period HP 1 .
  • the control transistor of the first driving stage of the conventional gate driving circuit is diode-connected between the input terminal and the first node, the voltage of the first node NQ is decreased due to the start signal STV decreasing to the low voltage VL-C as represented by a first area A 1 shown in FIG. 9 .
  • the first control transistor TR_C 1 of the first driving stage SRC 1 is operated by the second clock signal CKVB, and thus the first control transistor TR_C 1 is maintained in the turned-off state during the second horizontal period HP 2 . That is, since the first control transistor TR_C 1 applying the start signal STV to the first node NQ is maintained in the turned-off state during the first horizontal period HP 1 , the voltage of the first node NQ is maintained at a constant level even though the start signal STV decreases to the low voltage VL-C. Thus, coupling between the start signal STV and the first node NQ is prevented from occurring.
  • the first driving stage SRC 1 of the gate driving circuit 110 may precharge the voltage of the first node NQ to the first voltage VQ 1 and prevent the coupling between the start signal STV and the first node NQ, which occurs at the time point at which the start signal STV decreases, from occurring. Accordingly, the capability and the reliability of the gate driving circuit 110 may be improved.
  • FIG. 10 is a circuit diagram showing a first driving stage SRC 1 - 1 according to another exemplary embodiment of the present disclosure.
  • the first driving stage SRC 1 - 1 includes output parts 1110 - 1 and 1110 - 2 , a control part 1120 ′, an inverter part 1130 , and pull-down parts 1140 - 1 and 1140 - 2 .
  • the output parts 1110 - 1 and 1110 - 2 include first and second output transistors TR_O 1 and TR_O 2 .
  • the control part 1120 ′ includes first to fifth control transistors TR_C 1 to TR_C 5 .
  • the inverter part 1130 includes first to fourth inverter transistor TR_I 1 to TR_I 4 .
  • the pull-down parts 1140 - 1 and 1140 - 2 include first to fourth pull-down transistors TR_D 1 to TR_D 4 .
  • the output parts 1110 - 1 and 1110 - 2 , the inverter part 1130 , and the pull-down parts 1140 - 1 and 1140 - 2 have the same structure and function as those of the output parts 111 - 1 and 111 - 2 , the inverter part 113 , and the pull-down parts 114 - 1 and 114 - 2 of the third driving stage SRC 3 shown in FIG. 6 , and thus details thereof will be omitted.
  • the first driving stage SRC 1 - 1 shown in FIG. 10 does not receive the second clock signal CKVB.
  • the input electrode of the fourth control transistor TR_C 4 of the first driving stage SRC 1 - 1 is connected to the second node NB. That is, the switching signal of the second node NB, which is output from the inverter part 1130 , may be synchronized with the first clock signal CKV and substantially the same as the first clock signal CKV except for the first horizontal period HP 1 .
  • the first driving stage SRC 1 - 1 is operated in response to the switching signal of the second node NB, i.e., the output signal of the inverter part 1130 , instead of the second clock signal CKVB.
  • FIG. 11 is a block diagram showing a display device 200 according to another exemplary embodiment of the present disclosure.
  • the display device 200 includes a display panel DP, gate driving circuits 210 - 1 and 210 - 2 , and a data driving circuit 220 .
  • a first substrate DS 1 , a second substrate DS 2 , a signal controller SC, a main circuit board MCB, gate lines GL 1 to GLn, data lines DL 1 to DLm, pixels PX 11 to PXnm, a display area DA, and a non-display area NDA, which are included in the display device 200 are the same as those described with reference to FIG. 1 .
  • the display device 200 shown in FIG. 11 includes first and second gate driving circuits 210 - 1 and 210 - 2 .
  • the first gate driving circuit 210 - 1 is disposed at one side of the display panel DP and connected to the gate lines GL 1 to GLn.
  • the second gate driving circuit 210 - 1 is disposed at another side of the display panel DP and connected to the gate lines GL 1 to GLn.
  • the first and second gate driving circuits 210 - 1 and 210 - 2 respectively drive the gate lines GL 1 to GLn in a display area DA.
  • the first and second gate driving circuits 210 - 1 and 210 - 2 are operated in response to control signals provided from the signal controller SC. Since the first and second gate driving circuits 210 - 1 and 210 - 2 substantially simultaneously drive the gate lines GL 1 to GLn, the control signals provided from the signal controller SC are required to have the same phase. However, the control signals applied to the first and second gate driving circuits 210 - 1 and 210 - 2 from the signal controller SC may have different phases from each other due to a distance between the signal controller SC and the first and second gate driving circuits 210 - 1 and 210 - 2 , inner wirings, and inner parasitic capacitances. As a result, defects described with reference to FIG. 9 may occur in first driving stages of the first and second gate driving circuits 210 - 1 and 210 - 2 .
  • the gate driving circuit applies the start signal STV to the first node NQ in response to the second clock signal CKVB or the first clock signal CKV having a phase opposite to the second clock signal CKVB. Accordingly, although the phases of the control signals are changed as described above, the gate signals are stably output, thereby improving the capability and the reliability of the gate driving circuit.
  • the precharging time is shortened due to the delay of the start signal
  • the voltage of the node used to control the output part is sufficiently precharged and stably maintained to improve the capability and the reliability of the gate driving circuit.

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US11120745B2 (en) 2019-01-07 2021-09-14 Samsung Display Co., Ltd. Scan driver

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KR102253623B1 (ko) 2021-05-21

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