TWM531053U - Wafer carrier with a 14-pocket configuration - Google Patents
Wafer carrier with a 14-pocket configuration Download PDFInfo
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- TWM531053U TWM531053U TW105205252U TW105205252U TWM531053U TW M531053 U TWM531053 U TW M531053U TW 105205252 U TW105205252 U TW 105205252U TW 105205252 U TW105205252 U TW 105205252U TW M531053 U TWM531053 U TW M531053U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68771—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting more than one semiconductor substrate
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
- C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
- C23C16/4584—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally the substrate being rotated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68764—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel
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Abstract
Description
本創作係關於半導體製造技術,並且尤其是關於化學氣相沉積(CVD)製程及相關設備,用於在製程期間保持半導體晶圓。 This creation relates to semiconductor fabrication techniques, and more particularly to chemical vapor deposition (CVD) processes and related equipment for holding semiconductor wafers during processing.
在發光二極體(LED)和諸如鐳射二極體、光探測器和場效應電晶體的其它高性能器件的製造中,典型地使用化學氣相沉積(CVD)製程在藍寶石或矽基板之上使用諸如氮化鎵的材料生長薄膜堆疊結構。CVD工具包括一處理艙體,該處理艙體是密封環境以允許注入的氣體在基板(通常為晶圓的形式)上反應以生長薄膜層。這種製造設備的現行生產線的實例是由Plainview,New York的Veeco Instruments Inc.製造的TurboDisc®和MOCVD系統的EPIK系列。 In the fabrication of light-emitting diodes (LEDs) and other high-performance devices such as laser diodes, photodetectors, and field effect transistors, chemical vapor deposition (CVD) processes are typically used on top of sapphire or germanium substrates. The thin film stack structure is grown using a material such as gallium nitride. The CVD tool includes a processing chamber that is a sealed environment to allow the injected gas to react on the substrate (typically in the form of a wafer) to grow a thin film layer. An example of a current production line for such manufacturing equipment is the EPIK series of TurboDisc® and MOCVD systems manufactured by Veeco Instruments Inc. of Plainview, New York.
控制諸如溫度、壓強和氣體流速的一些製程參數以獲得所希望的晶體生長。使用不同的材料和製程參數來生長不同層。例如,典型地,由諸如III-V族半導體的化合物半導體形成的器件是藉由使用金屬有機化學氣相沉積(MOCVD)生長連續的該化合物半導體層而形成的。在此製程中,晶圓被暴露於氣體的組合中,典型地,該氣體包括作為III族金屬的源的金屬有機化合物,並且更包括當晶圓保持在升高的溫度下時在晶圓表面上流動的V族元素的源。通常,金屬有機化合物和V族源與明顯不參與反應的載氣組合,該載氣例如是氮氣。III-V族半導體的一個實例是氮化鎵,可以在晶圓具有適當晶格間隙的基板(例如藍寶石晶圓)上 藉由有機鎵化合物和氨氣的反應來形成氮化鎵。在沉積氮化鎵和相關化合物期間一般將該晶圓保持在大約1000-1100℃的溫度下。 Some process parameters such as temperature, pressure, and gas flow rate are controlled to achieve the desired crystal growth. Different materials and process parameters are used to grow different layers. For example, a device formed of a compound semiconductor such as a group III-V semiconductor is typically formed by growing a continuous semiconductor compound layer using metal organic chemical vapor deposition (MOCVD). In this process, the wafer is exposed to a combination of gases, typically including a metal organic compound as a source of a Group III metal, and more including a wafer surface while the wafer is maintained at an elevated temperature. The source of the flowing V group elements. Typically, the organometallic compound and the Group V source are combined with a carrier gas that is not significantly involved in the reaction, such as nitrogen. An example of a III-V semiconductor is gallium nitride, which can be on a substrate with a suitable lattice gap on the wafer (eg, a sapphire wafer). Gallium nitride is formed by the reaction of an organogallium compound and ammonia gas. The wafer is typically maintained at a temperature of between about 1000 and 1100 ° C during the deposition of gallium nitride and related compounds.
在藉由基板表面上的化學反應而發生晶體生長的MOCVD製程中,必須特別小心地控制製程參數以確保在所要求的條件下進行該化學反應。在製程條件中即使小的變化也可能不利地影響器件品質和生產良率。例如,如果沉積氮化鎵銦層(gallium and indium nitride layer),晶圓表面溫度的變化將會引起沉積層的成分和帶隙的變化。因為銦具有相對高的蒸氣壓,在表面溫度較高的晶圓區域中該沉積層將會具有較低的銦比例和較大的帶隙。如果該沉積層為主動、LED結構的發光層,那麼由該晶圓形成的LED的輻射波長也將會變至不可接受的程度。 In an MOCVD process in which crystal growth occurs by chemical reaction on the surface of the substrate, process parameters must be carefully controlled to ensure that the chemical reaction is carried out under the desired conditions. Even small changes in process conditions can adversely affect device quality and production yield. For example, if a gallium and indium nitride layer is deposited, changes in the surface temperature of the wafer will cause variations in the composition and band gap of the deposited layer. Because indium has a relatively high vapor pressure, the deposited layer will have a lower indium ratio and a larger band gap in the region of the wafer where the surface temperature is higher. If the deposited layer is an active, LED structured light-emitting layer, the wavelength of the radiation formed by the wafer will also become unacceptable.
在MOCVD處理艙體中,在其上生長薄膜層的半導體晶圓設置於被稱作晶圓載具的快速旋轉的旋轉料架(carousel)上,以在反應艙體之內使它們的表面均勻暴露於氣體環境中,以沉積半導體材料。轉速是大約1000RPM。該晶圓載具典型地是由諸如石墨的高導熱材料機械加工出來的,並且經常塗覆有諸如碳化矽材料的保護層。每個晶圓載具具有一組圓形凹部(indentation),或容置區(pocket),在其頂表面中放置有單個的晶圓。典型地,晶圓被支撐為與每個容置區的底部表面成間隔關係以允許在該晶圓的邊緣周圍流動氣體。在U.S.專利申請公開No.2012/0040097、U.S.專利No.8092599、U.S.專利No.8021487、U.S.專利申請公開No.2007/0186853、U.S.專利No.6902623、U.S.專利No.6506252和U.S.專利No.6492625中描述了有關技術的一些實例,藉由引用將其公開內容合併於此。 In the MOCVD processing chamber, the semiconductor wafer on which the thin film layer is grown is placed on a rapidly rotating rotating carousel called a wafer carrier to uniformly expose their surfaces within the reaction chamber. In a gaseous environment, a semiconductor material is deposited. The speed is approximately 1000 RPM. The wafer carrier is typically machined from a highly thermally conductive material such as graphite and is often coated with a protective layer such as a tantalum carbide material. Each wafer carrier has a set of circular indentations, or pockets, with a single wafer placed in its top surface. Typically, the wafer is supported in spaced relationship with the bottom surface of each of the accommodating regions to allow gas to flow around the edges of the wafer. US Patent Application Publication No. 2012/0040097, US Patent No. 8092599, US Patent No. 8021487, US Patent Application Publication No. 2007/0186853, US Patent No. 6,902,623, US Patent No. 6,506,252, and US Patent No. 6,492,625 Some examples of related techniques are described herein, the disclosure of which is incorporated herein by reference.
晶圓載具被支撐於反應艙體中的轉軸(spindle)上,使得具有晶圓的暴露表面的晶圓載具的頂表面向上朝向氣體分配 裝置。當該轉軸旋轉時,該氣體被向下引導到該晶圓載具的頂表面上並且經過該頂表面流向該晶圓載具的外周。使用過的氣體透過設置在該晶圓載具下方的通口從反應艙體中排出。藉由加熱元件將該晶圓載具保持在期望的升高溫度,該加熱元件典型地是設置在該晶圓載具的底表面之下的電阻加熱元件。將這些加熱元件保持在比該晶圓表面的期望溫度還要高的溫度,然而典型地將該氣體分配裝置保持在遠低於期望反應溫度的溫度,以防止氣體過早反應。因而,熱量從該加熱元件向該晶圓載具的底表面傳輸並向上通過晶圓載具流向單個晶圓。 The wafer carrier is supported on a spindle in the reaction chamber such that the top surface of the wafer carrier having the exposed surface of the wafer is directed upward toward the gas distribution Device. As the shaft rotates, the gas is directed down onto the top surface of the wafer carrier and through the top surface to the periphery of the wafer carrier. The used gas is discharged from the reaction chamber through a port disposed under the wafer carrier. The wafer carrier is maintained at a desired elevated temperature by a heating element, typically a resistive heating element disposed beneath the bottom surface of the wafer carrier. These heating elements are maintained at a temperature higher than the desired temperature of the wafer surface, however the gas distribution device is typically maintained at a temperature well below the desired reaction temperature to prevent premature gas reaction. Thus, heat is transferred from the heating element to the bottom surface of the wafer carrier and flows upward through the wafer carrier to a single wafer.
在晶圓之上的氣流依賴於每個晶圓的徑向位置而變化,其中位於最外側的晶圓會具有較高流動率,此乃他們在轉動過程中較快的速度所導致。甚至在每個單個晶圓上都可能存在溫度非均勻性,即冷點和熱點。影響溫度非均勻性的形成的一個可變因素是晶圓載具內的容置區的形狀。通常,容置區形狀在該晶圓載具的表面中形成圓形。由於晶圓載具旋轉,因而該晶圓在其最外面的邊緣(即離旋轉軸最遠的邊緣)處受到實質性的向心力,導致晶圓擠靠該晶圓載具中各個容置區的內壁。在這種情況下,在晶圓的這些外部邊緣和容置區的邊緣之間存在緊密接觸。向晶圓的這些最外面部分的增加的熱傳導導致更大的溫度非均勻性,進一步使上述的問題惡化。既有的處理方式為藉由增加晶圓的邊緣和容置區的內壁之間的間隙來最小化溫度非均勻性,包括將晶圓設計為邊緣的一部分上是平的(即平邊晶圓)。晶圓的此平坦部分產生間隙並減小與該容置區的內壁的接觸點,由此緩和溫度非均勻性。其他影響晶圓載具所支撐晶圓各處的熱均勻性的因素包括晶圓載具的熱傳輸和發射特性,並結合晶圓容置區的佈局。 The airflow over the wafer varies depending on the radial position of each wafer, with the wafers on the outermost side having a higher flow rate due to their faster speed during rotation. There may be temperature non-uniformities, ie cold spots and hot spots, even on each individual wafer. One variable factor that affects the formation of temperature non-uniformities is the shape of the containment area within the wafer carrier. Typically, the shape of the receiving area forms a circle in the surface of the wafer carrier. As the wafer carrier rotates, the wafer is subjected to substantial centripetal force at its outermost edge (ie, the edge furthest from the axis of rotation), causing the wafer to be squeezed against the inner wall of each of the accommodating regions of the wafer carrier . In this case, there is close contact between these outer edges of the wafer and the edges of the accommodating area. The increased heat transfer to these outermost portions of the wafer results in greater temperature non-uniformities, further exacerbating the above problems. The existing treatment method is to minimize temperature non-uniformity by increasing the gap between the edge of the wafer and the inner wall of the accommodating area, including designing the wafer as a part of the edge is flat (ie, flat-sided crystal circle). This flat portion of the wafer creates a gap and reduces the point of contact with the inner wall of the accommodating area, thereby alleviating temperature non-uniformity. Other factors that affect the thermal uniformity across the wafer supported by the wafer carrier include the heat transfer and emission characteristics of the wafer carrier, combined with the layout of the wafer containment area.
與溫度均勻性需求相關的,對於晶圓載具的另一個 所希望的特性是增加CVD製程的生產量。在增加製程生產量中該晶圓載具的角色是保持大量的單個晶圓。提供具有更多晶圓的晶圓載具佈局影響熱模型。例如,由於來自晶圓載具邊緣的輻射熱損耗,靠近邊緣的晶圓載具的部分傾向處在比其他部分更低的溫度下。 Related to temperature uniformity requirements, another for wafer carriers The desired property is to increase the throughput of the CVD process. The role of the wafer carrier in increasing process throughput is to maintain a large number of individual wafers. Providing a wafer carrier layout with more wafers affects the thermal model. For example, due to radiant heat loss from the edge of the wafer carrier, portions of the wafer carrier near the edge tend to be at a lower temperature than other portions.
因此,需要在其中解決高密度佈局中的溫度均勻性和機械應力的用於晶圓載具的實用解決方案。 Therefore, there is a need for a practical solution for wafer carriers in which temperature uniformity and mechanical stress in a high density layout are addressed.
本創作提出一種晶圓載具,其包括新的容置區配置。本文所描述的配置係有助於熱傳輸,以及有助於達成圓晶圓生長之容置區的高填充密度(high packing density)。 This creation proposes a wafer carrier that includes a new accommodating zone configuration. The configuration described herein facilitates heat transfer and helps to achieve high packing density of the accommodating area for wafer growth.
142‧‧‧晶圓載具 142‧‧‧ wafer carrier
146‧‧‧本體 146‧‧‧ body
148‧‧‧頂表面 148‧‧‧ top surface
152‧‧‧底表面 152‧‧‧ bottom surface
162‧‧‧容置區 162‧‧‧Receiving area
164‧‧‧鎖定特徵部 164‧‧‧Locking feature
166‧‧‧側壁 166‧‧‧ side wall
168‧‧‧基板 168‧‧‧Substrate
R1、R2‧‧‧圓 R1, R2‧‧‧ round
在連同圖式考慮下列本創作各種實施例的詳細描述後,可以更完整地理解本創作,其中:圖1是根據一實施例的具有14個容置區配置的晶圓載具的立體圖。 The present invention can be more completely understood after considering the following detailed description of various embodiments of the present invention, in which: FIG. 1 is a perspective view of a wafer carrier having 14 accommodating zone configurations, in accordance with an embodiment.
圖2是根據一實施例的具有14個容置區配置的晶圓載具的俯視圖。 2 is a top plan view of a wafer carrier having 14 accommodating zone configurations, in accordance with an embodiment.
圖3是根據一實施例的具有14個容置區配置的晶圓載具的側視圖。 3 is a side view of a wafer carrier having 14 accommodating zone configurations, in accordance with an embodiment.
圖4是根據一實施例的具有14個容置區配置的晶圓載具的仰視圖。 4 is a bottom view of a wafer carrier having 14 accommodating zone configurations, in accordance with an embodiment.
圖5是根據一實施例的具有14個容置區配置的晶圓載具的部分細節圖,其顯示來自立體圖的單個容置區。 5 is a partial detail view of a wafer carrier having 14 accommodating zone configurations showing a single accommodating zone from a perspective view, in accordance with an embodiment.
圖1是根據一實施例的晶圓載具142的立體圖,該晶圓載具142係用於化學氣相沉積裝置中。圖2是同一晶圓載具142的俯視圖。晶圓載具142包括:具有頂表面148的本體146,和限定於其中的十四個容置區162。在圖1和圖2所示的實施例中,容置區162布置在兩個圓R1和R2中,每個圓與由本體146的外邊緣限定的圓是同心的。在徑向內圓R1中,四個容置區162在方位上均勻地間隔開。同樣地,在徑向外圓R2中,十個容置區162在方位上均勻地間隔開。每個容置區162是形成在本體146中的孔口,該孔口實質上延伸垂直於將頂表面148歸在內的平面。 1 is a perspective view of a wafer carrier 142 for use in a chemical vapor deposition apparatus, in accordance with an embodiment. 2 is a top plan view of the same wafer carrier 142. Wafer carrier 142 includes a body 146 having a top surface 148 and fourteen receiving regions 162 defined therein. In the embodiment illustrated in Figures 1 and 2, the receiving area 162 is disposed in two circles R1 and R2, each circle being concentric with a circle defined by the outer edge of the body 146. In the radially inner circle R1, the four accommodating regions 162 are evenly spaced apart in the azimuth. Similarly, in the radially outer circle R2, the ten accommodating regions 162 are evenly spaced apart in the azimuth. Each of the receiving regions 162 is an aperture formed in the body 146 that extends substantially perpendicular to a plane that centers the top surface 148.
在圖1和圖2中描繪的容置區的布置的優點在於:在頂表面148上保持相對高密度的容置區162的同時,其提供了期望水準的熱均勻性。而容置區162的尺寸可容納於此頂表面148的區域中。 An advantage of the arrangement of the accommodating regions depicted in Figures 1 and 2 is that while maintaining a relatively high density of accommodating regions 162 on the top surface 148, it provides a desired level of thermal uniformity. The receiving area 162 is sized to be received in the area of the top surface 148.
圖2更描繪了代表性的圓,容置區162布置在該圓的周圍。在圖2所示的實施例中,有兩個圓,R1和R2,每個圓具有不同的半徑,並且被布置為彼此同心以及與頂表面148的圓形輪廓同心。 Figure 2 further depicts a representative circle in which the accommodating area 162 is disposed. In the embodiment shown in Figure 2, there are two circles, R1 and R2, each having a different radius and arranged to be concentric with one another and concentric with the circular contour of the top surface 148.
圖3為一側視圖,其為圖1和圖2的晶圓載具142的側視圖。在圖3所示的視圖中,可以看出頂表面148和底表面152之間的尺寸上的相對差異。尤其是,頂表面更朝向如圖3中顯示的頁面的頂部和底部延伸,或者在圖1和圖2中顯示的圖中進一步向徑向延伸。先前在圖1和圖2中描繪的每個容置區162都從頂表面148朝向底表面152延伸。底表面152提供固態基底,在該固態基底上可以將晶圓生長在晶圓載具142中。 3 is a side elevational view of the wafer carrier 142 of FIGS. 1 and 2. In the view shown in Figure 3, the relative difference in size between the top surface 148 and the bottom surface 152 can be seen. In particular, the top surface extends further toward the top and bottom of the page as shown in Figure 3, or further radially in the figures shown in Figures 1 and 2. Each of the accommodating regions 162 previously depicted in FIGS. 1 and 2 extends from the top surface 148 toward the bottom surface 152. The bottom surface 152 provides a solid substrate on which wafers can be grown in the wafer carrier 142.
圖4是先前關於圖1至圖3所描述的晶圓載具142的仰視圖。如圖4中所示,晶圓載具142包括在底表面152的中心的鎖定 特徵部164。 4 is a bottom view of the wafer carrier 142 previously described with respect to FIGS. 1-3. As shown in FIG. 4, wafer carrier 142 includes a lock at the center of bottom surface 152. Feature portion 164.
圖5為顯示一個容置區162的部分立體圖。每個容置區162包括側壁166,其實質上是圓柱形的。由側壁166形成的圓柱的底部是基板168。 FIG. 5 is a partial perspective view showing an accommodation area 162. Each receiving area 162 includes a side wall 166 that is substantially cylindrical. The bottom of the cylinder formed by side wall 166 is substrate 168.
這些實施例是用作示例的目的而非限制。附加的實施例為在申請專利範圍內。另外,儘管已參考具體實施例來描述本創作的多個方面,但是所屬領域的技術人員將會認識到可以在不脫離由申請專利範圍所限定的本創作的範圍的情況下對形式和細節上作出改變。 These examples are for illustrative purposes and are not limiting. Additional embodiments are within the scope of the patent application. In addition, while the various aspects of the present invention have been described with reference to the specific embodiments, those skilled in the art will recognize that the form and details can be made without departing from the scope of the present invention as defined by the scope of the claims. Make a change.
142‧‧‧晶圓載具 142‧‧‧ wafer carrier
148‧‧‧頂表面 148‧‧‧ top surface
162‧‧‧容置區 162‧‧‧Receiving area
R1、R2‧‧‧圓 R1, R2‧‧‧ round
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-
2015
- 2015-03-27 US US29/522,212 patent/USD793971S1/en active Active
- 2015-09-25 DE DE202015006765.4U patent/DE202015006765U1/en not_active Expired - Lifetime
- 2015-09-25 TW TW104305352F patent/TWD181302S/en unknown
- 2015-09-25 TW TW105205252U patent/TWM531053U/en not_active IP Right Cessation
- 2015-09-30 KR KR2020150006435U patent/KR20160003442U/en not_active Application Discontinuation
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2017
- 2017-08-01 US US29/612,468 patent/USD852762S1/en active Active
Also Published As
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TWD181302S (en) | 2017-02-11 |
KR20160003442U (en) | 2016-10-06 |
DE202015006765U1 (en) | 2016-01-22 |
USD852762S1 (en) | 2019-07-02 |
USD793971S1 (en) | 2017-08-08 |
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