M420823 五、新型說明： 【新型所屬之技術領域】 本創作係有關一種晶圓承載板，特別是一種可提供複數 種尺寸之晶圓使用的晶圓承載板（susceptor)。 【先前技術】 現行在半導體或光電產業生產製造廠中，加熱機台上所設計之 承載板所可承載之晶圓皆為單一尺寸，圖丨至圖3所示分別為2吋 晶圓12、4忖晶圓14及6忖晶圓16於一承載板1〇上的排列示意圖， 其中此承載板10所能承载的晶圓數量分別為37個2时晶圓12(如圖 1 一所示）’9個4忖晶圓14(如圖2所示)及4偏6忖晶圓16(如圖3所 示）。雖^心81 12、4对晶圓14以时晶BI 16於承載板10上 以緊密排列來達到最佳的_率，然關晶圓片之幾何形狀及單一 尺寸的關’仍無法翻全部㈣承載板1〇，使得製作成本益法有 效降低。 ‘ ' q =方面卩化學*汽沈積祕巾為例，在 中，晶圓係與晶圓表面所經過的氣體產生反應 將使得 生蟲晶材㈣，若承触上無法有效承載數量較多之^ 反應氣體的使贿法_最铜神的要求。 【新型内容】 載板，其係可承種複尺寸晶圓承 應氣體的最佳利料，呈有，以達到承載板本體之面積與反 〃有増加產量及降低成本支出之優點。 4 入為了達到上述目的，本創作—實施例之複尺寸晶圓承載板包 含.-承载板本體；-第—凹槽組設置於承载板本體之中央，第一 凹槽組包含至少—具有-第—尺寸之第ϋΐ放置槽；以及-第二 凹槽組包含複數個具有—第二尺寸之第二晶圓放置槽，該些第二晶 圓放置槽對齡佈於第-凹槽組周邊，其巾第-尺寸相異於該第二 尺寸。 本創作又-實施例之複尺寸晶圓承載板，包含··—承載板本體； 第外凹槽、，且β又置於承載板本體之中央，第一凹槽組包含複數個具 有第尺寸之第—晶圓放置槽；以及一第二凹槽組包含複數個具 有第一尺寸之第二晶圓放置槽，該些第二晶圓放置槽對稱分佈於 第-凹槽组周邊，其中第—尺寸相異於該第二尺寸。 【實施方式】 圖_4所不為本創作一實施例複尺寸晶圓承載板之結構示意圖。 如圖所不’―複尺寸晶圓承載板20包含-承載板本體22,於-實施 j中承載板本體22係為圓板狀；一第一凹槽組設置於承載板本體 22的中央’於_實施例中’第—凹槽組包含單—第—晶圓放置槽^ 2置於承載板本體22的中央，第一晶圓放置槽24具有—第一尺寸； 一第二凹槽组包含複數個第二晶圓放置槽26，對齡佈於第一晶圓 放置槽24的周邊，其中每―第二晶圓放置槽26具有-第二尺寸， 且第一尺寸相異於第—尺寸，於—實施例中，如圖4所示，第二晶 圓放，槽26之第二尺寸係小於第-晶圓放置槽24之第一尺寸，且 ^24曰曰圓放置槽26彼此緊鄰在一起。於本實施例中，第-晶圓放置 之第一尺寸為6对，以供放置6 °寸晶圓(圖中未示），第二晶圓M420823 V. New Description: [New Technology Area] This creation is about a wafer carrier board, especially a wafer carrier (susceptor) that can be used for a plurality of sizes of wafers. [Prior Art] In the current semiconductor or optoelectronic industry manufacturing plants, the wafers that can be carried by the carrier board designed on the heating machine are all of a single size, as shown in Figure 3, respectively, 2 wafers 12 4排列 wafer 14 and 6忖 wafer 16 are arranged on a carrier board 1,, wherein the carrier board 10 can carry 37 wafers at 2 o'clock respectively (as shown in FIG. 1) ) '9 4 忖 wafers 14 (shown in Figure 2) and 4 忖 6 忖 wafers 16 (shown in Figure 3). Although the cores of the 12, 12, and 4 pairs of wafers 14 are arranged in a tightly aligned manner on the carrier 10 to achieve an optimum ratio, the geometry of the wafer and the single size of the wafer cannot be turned over. (4) The load plate is 1〇, which makes the cost of production cost effectively reduced. ' ' q = aspect 卩 chemistry * vapor deposition secret towel as an example, in which the wafer system reacts with the gas passing through the surface of the wafer to make the insect crystal material (4), if the contact can not effectively carry a large number of ^ Responsible gas bribery _ the most copper god's request. [New content] The carrier board is the best material for bearing the multi-size wafer to support the gas, so as to achieve the advantages of the area of the carrier board and the increase in output and cost. In order to achieve the above object, the multi-size wafer carrier of the present invention-embodiment includes: a carrier body; the first groove set is disposed at the center of the carrier body, and the first groove group includes at least - a second size groove of the first dimension; and - the second groove set includes a plurality of second wafer placement grooves having a second size, the second wafer placement grooves being disposed adjacent to the periphery of the first groove group The towel-size is different from the second size. The multi-size wafer carrier board of the present invention is further comprising: a carrier body; an outer groove, wherein β is placed in the center of the carrier body, and the first groove group comprises a plurality of sizes a second wafer set groove; and a second groove set includes a plurality of second wafer placement grooves having a first size, wherein the second wafer placement grooves are symmetrically distributed around the first groove group, wherein - The size is different from the second size. [Embodiment] FIG. 4 is a schematic view showing the structure of a multi-size wafer carrier according to an embodiment of the present invention. As shown in the figure, the multi-size wafer carrier 20 includes a carrier body 22, and in the implementation j, the carrier body 22 is in the shape of a disk; a first groove group is disposed in the center of the carrier body 22 In the embodiment, the 'first groove group includes a single-first wafer placement groove 2 disposed in the center of the carrier body 22, and the first wafer placement groove 24 has a first size; a second groove group A plurality of second wafer placement slots 26 are included, which are disposed on the periphery of the first wafer placement slot 24, wherein each of the second wafer placement slots 26 has a second size, and the first size is different from the first Dimensions, in the embodiment, as shown in FIG. 4, the second wafer is placed, the second size of the groove 26 is smaller than the first size of the first wafer placement groove 24, and the circular groove 26 is placed at each other. Close together. In this embodiment, the first size of the first wafer placement is 6 pairs for placing a 6 ° inch wafer (not shown), the second wafer
a 26之第—尺寸為4吋，以供放置複數個4吋晶 惟不限於此。 VMT不丨J 圖二斤不為本創作另一實施例複尺寸晶圓承載板之結構示意 於此實知例中，如圖所示，第二晶圓放置槽26之第二尺寸係大 於中央之第一晶圓放置槽24的第一— 放置槽26之間分別設置—第：二，了二相鄰之第二晶圓 28且右當0 置槽烈，每—第三晶圓放置槽 28具有-第二尺才’且第三尺寸相異於第 f 一晶圓放置槽24之第-尺寸為〜，以供放置-圖中中 未示），第二晶圓放置槽26之第二 、于日日®(a中 忖晶_中未示），第三晶圓放::尺^放置複數個6 置複數個2侧(圖中未示)，惟二 2寸，以供放 於第一尺十。 μ限於此’弟二尺寸可相同或相異 圖6所示為本創作又_實施例複尺寸 圖。於此實施例中，設置於承載板 =:=、 包含單一第-晶圓放置槽24 ’而係邮組並不只 ^ 30 -30·, 3：1：!Γ!；βΒβ：： 6所示，其中一第_ θ m嫌要秘 八有第尺寸’如圖 场之第1日圓放罟:叩，設置於承載板本體22之中央，而 的則對稱分佈於中央之第-晶圓放置槽3〇 的周邊’ 凹槽组包含複數個具有第 ί6尺=r:r之第一晶圓放置槽3。 之第本實施例中，第-晶圓放細、30, 不限於此。於另施例;二H槽26之第-尺寸係為4寸’惟 鄰之第二晶圓放置;:::別==^^ 置槽的尺柯與第-尺侧二尺謝==皆t圓放 照本積下，依 晶圓’所涵蓋之加熱板本體的:積二：3圓及，^ Γ二5所示之排列可容納5個2对心二= Ξ’/Γ-盍之，的面積為83°97— 涵蓋==則可容納8個4时晶圓及7個2忖晶圓，所 七盍之加熱板的面積為79G44.G4_2;相較於先前技術中之 M420823 37個2吋晶圓所涵蓋的加熱板面積為7499〇 5〇 mm2 ; 9個4吋曰 圓所涵蓋的加熱板面積為72963.73mni2 ; 4個6吋晶圓所涵苗的: 熱板面積為72963.73mm2而言，本創作皆具有較大的加埶 本體覆蓋面積。 综合上述，本創作複尺寸晶圓承載板可承載多種尺寸之晶 圓，以達到承載板本體之面積與反應氣體的最佳利用率，具有增加 產量及降低成本支出之優點。 以上所述之實施例僅係為說明本創作之技術思想及特點，其目 的在使熟習此項技藝之人士能夠瞭解本創作之内容並據以實施，當 不能以之限定本創作之專利範圍，即大凡依本創作所揭示之精神所 作之均等變化或修飾，仍應涵蓋在本創作之專利範圍内。 M420823 【圖式簡單說明】 圖1所示為習知2吋晶圓於承載板上之排列示意圖。 圖2所示為習知4吋晶圓於承載板上之排列示意圖。 圖3所示為習知6叶晶圓於承載板上之排列示意圖。 圖4所示為本創作一實施例複尺寸晶圓承載板之結構示意圖。 圖5所示為本創作另一實施例複尺寸晶圓承載板之結構示意圖。 圖6所示為本創作又一實施例複尺寸晶圓承載板之結構示意圖。 【主要元件符號說明】 10 承載板 12 2 p寸晶圓 14 4吋晶圓 16 6 σ寸晶圓 20 複尺寸晶圓承載板 22 承載板本體 24 第一晶圓放置槽 26 第二晶圓放置槽 28 第三晶圓放置槽 30、30, 第一晶圓放置槽The size of a 26 - size 4 吋 for placing a plurality of 4 吋 crystals is not limited to this. VMT is not the same as the second embodiment. In the embodiment of the present invention, as shown in the figure, the second size of the second wafer placement groove 26 is larger than the central portion. The first-placement slot 26 of the first wafer placement slot 24 is respectively disposed between the first and the second, the second adjacent wafer 28, and the right is 0, and the slot is placed every third wafer. 28 has a second dimension and the third dimension is different from the first dimension of the fth wafer placement slot 24, for placement - not shown in the figure, and the second wafer placement slot 26 Second, in the day ® (a middle crystal _ not shown), the third wafer placed:: ruler ^ placed a plurality of 6 placed a plurality of 2 sides (not shown), only 2 inches for the release At the first ten feet. μ is limited to this. The size of the two brothers may be the same or different. Fig. 6 shows a complex size diagram of the creation and the embodiment. In this embodiment, it is disposed on the carrier board =:=, including a single first-wafer placement slot 24', and the postal group is not only ^ 30 -30·, 3:1:!Γ!; βΒβ:: 6 One of the first _ θ m is suspected to have a size of 'the first Japanese yen of the field of view: 叩, placed in the center of the carrier body 22, and symmetrically distributed in the center of the first - wafer placement slot The 3's perimeter 'groove set contains a plurality of first wafer placement slots 3 having a ί6 ft = r:r. In the first embodiment, the first wafer is thinned and 30, and is not limited thereto. In another embodiment; the second dimension of the two H-slots 26 is 4 inches 'the second wafer placed adjacent to each other;:::===^^ The ruler of the groove and the second ruler of the first-foot side == All are rounded and placed under the product, according to the wafer's covered heating plate body: product two: 3 circles and ^ Γ 2 5 arrangement can accommodate 5 2 pairs of hearts 2 = Ξ ' / Γ - In fact, the area is 83°97—covering == can accommodate 8 4 o'clock wafers and 7 2 忖 wafers, and the area of the heating plate of 7 盍 is 79G44.G4_2; compared with the prior art M420823 37 2吋 wafers cover a heating plate area of 7499〇5〇mm2; 9 4吋曰 circles cover a heating plate area of 72963.73mni2; 4 6吋 wafers contain the following: Hot plate area For the 72963.73mm2, this creation has a larger area of the body of the twisted body. In summary, the present multi-size wafer carrier can carry a variety of sizes of crystals to achieve the optimal utilization of the area of the carrier body and the reaction gas, and has the advantages of increased throughput and reduced cost. The embodiments described above are only for explaining the technical idea and characteristics of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement them according to the scope of the patent. That is, the equivalent changes or modifications made by the people in accordance with the spirit revealed by this creation should still be covered by the scope of the patent of this creation. M420823 [Simplified Schematic] FIG. 1 is a schematic view showing the arrangement of a conventional 2 吋 wafer on a carrier board. FIG. 2 is a schematic view showing the arrangement of a conventional silicon wafer on a carrier board. FIG. 3 is a schematic view showing the arrangement of a conventional 6-leaf wafer on a carrier board. FIG. 4 is a schematic structural view of a multi-size wafer carrier board according to an embodiment of the present invention. FIG. 5 is a schematic structural view of a multi-size wafer carrier board according to another embodiment of the present invention. FIG. 6 is a schematic structural view of a multi-size wafer carrier board according to still another embodiment of the present invention. [Main component symbol description] 10 carrier board 12 2 p inch wafer 14 4 吋 wafer 16 6 σ inch wafer 20 multiplexed wafer carrier 22 carrier board body 24 first wafer placement slot 26 second wafer placement Slot 28 third wafer placement slots 30, 30, first wafer placement slot