TWM428493U - Semiconductor packaging structure - Google Patents

Semiconductor packaging structure Download PDF

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Publication number
TWM428493U
TWM428493U TW101200066U TW101200066U TWM428493U TW M428493 U TWM428493 U TW M428493U TW 101200066 U TW101200066 U TW 101200066U TW 101200066 U TW101200066 U TW 101200066U TW M428493 U TWM428493 U TW M428493U
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TW
Taiwan
Prior art keywords
conductive
free
copper
semiconductor package
contact regions
Prior art date
Application number
TW101200066U
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English (en)
Inventor
Cheng-Hung Shih
Shu-Chen Lin
Cheng-Fan Lin
Yung-Wei Hsieh
Bo-Shiun Jiang
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Chipbond Technology Corp
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Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Priority to TW101200066U priority Critical patent/TWM428493U/zh
Publication of TWM428493U publication Critical patent/TWM428493U/zh
Priority to JP2012003721U priority patent/JP3178122U/ja
Priority to KR2020120006872U priority patent/KR20130004317U/ko

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

M428493 五、新型說明: 【新型所屬之技術領成】 [0001] 本創作係有關於一種半導體封裝結構’特別係有關 於一種可防止銅離子游離之半導體封裝結構° [先前技術]
[0002] 基於電子產品之體積越來越趨向輕薄短小之方向, 使得電子產品内部之電路布局也必須越來越趨向微細間 距發展,然電路佈線之間距越微細將使得短路之機率提 昇。 【新型内容】 [00〇3] 本創作之主要目的係在於提供一種半導體封裝結構 ’其包含一基板、一可導電之防游離膠體以及一晶片, 該基板係具有一上表面及複數個設置於該上表面之接點 ,各該接點係具有一第一接合表面,且該第一接合表面 係具有複數個第一導電顆粒接觸區及複數偭第一非導電 顆粒接觸區,該可導電之防游轉體係形成於該基板之 該上表面及該些接點上,該可導電之防游轉體係混合 貝粒及複數個防游離材,該晶片係覆 合於該基板,該晶片係具有一主動面及複數個設置 主動面之含鋼凸塊,該主動面係朝向該基板之該上 ’該可導電之防游_體係、包覆該些含銅凸塊, 銅&塊係具有—第二接合表面及—環壁該第二 系/、有複數個第—導電顆粒接觸區及複數個第 電顆粒接觸區,嗜此人k «二3銅凸塊係藉由該些導 連接於該些接點,該此 成些導電顆粒係位於該些第_ 10120006^^^^* A0101 ^ 4 I / ., ’共13頁 1012000212-0 M428493
面及該些第二接合表面之間,且該些導電顆粒係電性連 接該些第一接合表面之該些第一導電顆粒接觸區及該些 第二接合表面之該些第二導電顆粒接觸區,該些防游離 材係位於相鄰導電顆粒之間,且該些防游離材係位於各 該第一接合表面及各該第二接合表面之間,該些防游離 材係結合於該些第二接合表面之該些第二非導電顆粒接 觸區,且該些防游離材更包覆該些含銅凸塊之該些環壁 。由於該可導電之防游離膠體所具有之該些防游離材係 包覆該些含銅凸塊之該些環壁,因此當該些含銅凸塊中 之銅離子產生游離時,該些防游離材係可即時捕捉游離 之銅離子以防止短路之情形發生。 【實施方式】 [0004] 請參閱第1A至1C圖,其係本創作之一較佳實施例, 一種半導體封裝方法係包含下列步驟:首先,請參閱第 1A圖,提供一基板110,該基板110係具有一上表面111 及複數個設置於該上表面111之接點112,該些接點112 φ 係可為基板110上之引腳或是連接線路之凸塊接墊,各該 接點112係具有一第一接合表面113及一側壁114,且該 第一接合表面113係具有複數個第一導電顆粒接觸區113a 及複數個第一非導電顆粒接觸區113b ;接著,請參閱第 1B圖,形成一可導電之防游離膠體120於該基板110之該 上表面111及該些接點112上,該可導電之防游離膠體 120係混合有複數個導電顆粒121及複數個防游離材122 ,在本實施例中,該些防游離材122之材質係為有機保焊 劑,且該有機保焊劑之材質係選自於咪唑化合物或咪唑 衍生物其中之一,該°米°坐衍生物係可為苯基聯三連。坐、 10120006^^^^* A〇101 ^ 5 I / * 13 I 1012000212-0 M428493 苯基咪唑、替代性笨基咪唑或芳香族羥基咪唑或其混合 體其中之一,該咪唑化合物可為苯基聯三連唑、苯基咪 唑、替代性笨基咪唑或芳香族經基咮„坐或其混合體其中 之一。 最後,請參閱第ic圖,覆晶結合一晶片130於該基板 110,该晶片130係具有一主動面131及複數個設置於該 主動面131之含銅凸塊132 ,在本實施例中,該些含銅凸 塊132之材質係選自於銅/鎳或銅/錄/金其中之一,該主 動面131係朝向該基板11〇之該上表面ill,該可導電之 防游離膠體120係包覆該些含鋼凸塊132,各該含銅凸塊 132係具有一第二接合表面133及一環壁134,該第二接 合表面133係具有複數個第二導電顆粒接觸區133a及複數 個第二非導電顆粒接觸區133b,該些含銅·凸塊132係藉由 該些導電顆粒121電性連接於該些接點112,該些導電顆 粒121係位於該些第一接合表面113及該些第二接合表面 133之間,且該些導電顆粒121係電性連接該些第一接合 表面113之該些第一導電顆粒接觸區ii3a及該些第二接合 表面133之該些第二導電顆粒接觸區133a,該些防游離材 122係位於相鄰導電顆粒121之間,且該些防游離材122 係位於各該第一接合表面113及各該第二接合表面133之 間,該些防游離材122係結合於該些第二接合表面133之 該些第二非導電顆粒接觸區133b,且該些防游離材122更 包覆該些含銅凸塊132之該些環壁134,此外,該些防游 離材122係亦結合於該些第一接合表面113之該些第一非 導電顆粒接觸區113b,且該些防游離材122係包覆該些接 點112之該些侧壁114以形成一半導體封裝結構100。由 ⑻讓产單编號麵1 第6頁/共‘13頁 1012000212-0 M428493 於該可導電之防游離膠體120所具有之該些防游離材122 係可包覆該些含銅凸塊132之該些環壁134,因此當該些 含銅&塊132中之銅離子產生游離時,該些防游離材122 係可即時捕捉游離之銅離子以防止短路之情形發生,進 而提高該半導體封裝結構1〇〇之良率。 請再參閱第1C圖,其係本創作之一較佳實施例之一 種半導體封裝結構1〇〇,其係包含有一基板110、一可導 電之防游離膠體120以及一晶片130,該基板110係具有 一上表面111及複數個設置於該上表面U1之接點112, 各該接點112係具有一第一接合表面113,且該第一接合 表面113係具有複數個第一導電顆粒接觸區1 i3a及複數個 第一非導電顆粒接觸區113b,該可導電之防游離膠體120 係形成於該基板110之該上表面111及該些接點112上, 該可導電之防游離膠體120係混合有複數個導電顆粒121 及複數個防游離材122,該晶片130係覆晶結合於篇基板 110,該晶片130係具有一主動面131及複數個設置於該 主動面131之含銅凸塊132,該主動面131係朝向該基板 110之該上表面111,該可導電之防游離膠體120係包覆 該些含銅凸塊132,各該含銅凸塊132係具有一第二接合 表面133及一環壁134 ’該第二接合表面133係具有複數 個第二導電顆粒接觸區133a及複數個第二非導電顆粒接 觸區133b,該些含銅凸塊132係藉由該些導電顆粒121電 性連接於該些接點112,該些導電顆粒121係位於該些第 一接合表面113及該些第二接合表面133之間,且該些導 電顆粒121係電性連接該些第一接合表面113之該些第一 導電顆粒接觸區113a及該些第二接合表面133之該些第二 1012000212-0 10120006#單編號A0101 第7頁/共13頁 M428493 導電顆粒接觸區133a,該些防游離材122係位於相鄰導電 顆粒121之間,且該些防游離材122係位於各該第一接合 表面113及各該第二接合表面133之間,該些防游離材 122係結合於該些第二接合表面133之該些第二非導電顆 粒接觸區133b及該些第一接合表面113之該些第一非導電 顆粒接觸區113b,且該些防游離材122更包覆該些含銅凸 塊132之該些環壁134及該些接點112之該些側壁114。
本創作之保護範圍當視後附之申請專利範圍所界定 者為準,任何熟知此項技藝者,在不脫離本創作之精神 和範®内所作之任何變化與修改,均屬於本創作之保護 範圍。 【圖式簡單說明】 [0005] 第1A至1C圖:依據本創作之一較佳實施例,一種半導體 封裝方法之截面示意圖。 η
I 【主要元件符號說明】 [0006] 100半導體封裝結構 110基板
111上表面 112接點 113第一接合表面 113a第一導電顆粒接觸區 113b第一非導電顆粒接觸區 114側壁 120可導電之防游離膠體 121導電顆粒 122防游離材 130晶片 131主動面 132含銅凸塊 133第二接合表面 133a第二導電顆粒接觸區 133b第二非導電顆粒接觸區 10120006^^^^ A0101 第8頁/共13頁 1012000212-0 M428493 134環壁
順議#單編號A0101 第9頁/共13頁 1012000212-0

Claims (1)

  1. M428493 六、申請專利範圍: 1 . 一種半導體封裝結構,其至少包含: 一基板,其係具有一上表面及複數個設置於該上表面之 接點,各該接點係具有一第一接合表面,且該第一接合表 面係具有複數個第一導電顆粒接觸區及複數個第一非導電 顆粒接觸區; 一可導電之防游離膠體,其係形成於該基板之該上表面 及該些接點上,該可導電之防游離膠體係混合有複數個導
    電顆粒及複數個防游離材;以及
    一晶片,其係覆晶結合於該基板,該晶片係具有一主動 面及複數個設置於該主動面之含銅凸塊,該主動面係朝向 該基板之該上表面,該可導電之防游離膠體係包覆該些含 銅凸塊,各該含斜凸塊係具有一第二接合表面及一環壁, 該第二接合表面係具有複數個第二導電顆粒接觸區及複數 個第二非導電顆粒接觸區,該些含銅凸塊係藉由該些導電 顆粒電性連接於該些接點,該些導電顆粒係位於該些第一 接合表面及該些第二接合表面之間,且該些導電顆粒係電 性連接該些第一接合表面之該些第一導電顆粒接觸區及該 些第二接合表面之該些第二導電顆粒接觸區,該些防游離 材係位於相鄰導電顆粒之間,且該些防游離材係位於各該 第一接合表面及各該第二接合表面之間,該些防游離材係 結合於該些第二接合表面之該些第二非導電顆粒接觸區, 且該些防游離材更包覆該些含銅凸塊之該些環壁。 2.如申請專利範圍第1項所述之半導體封裝結構,其中該些 防游離材係結合於該些第一接合表面之該些第一非導電顆 粒接觸區。 1012000212-0 10120006^^^ A〇101 ^ 10 1 7 ^ 13 1 .如申凊專利範圍第1項所述之半導體封裝結構,其中各該 接點係具有一侧壁,該些防游離材係包覆該些側壁。 .如申請專利範圍第1項所述之半導體封裝結構,其中該些 防游離材之材質係為有機保焊劑。 .如申請專利範圍第4項所述之半導體封裝結構,其中該有 機保焊劑之材質係選自於咪唑化合物或咪唑衍生物其中之 —。 .如申請專利範圍第5項所述之半導體封裝結構,其中該咪 唑衍生物係可為笨基聯三連唑、笨基咪唑、替代性苯基咪 唑或芳香族羥基咪唑或其混合體其中之一,該咪唑化合物 可為苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族 羥基咪唑或其混合體其中之一。 .如申請專利範圍第1項所述之半導體封裝結構,其中該些 含銅凸塊之材質係選自於銅/鎳或銅/鎳/金其中之一。 10120006产單編號 A0101 第11頁/共13頁 1012000212-0
TW101200066U 2012-01-03 2012-01-03 Semiconductor packaging structure TWM428493U (en)

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TW101200066U TWM428493U (en) 2012-01-03 2012-01-03 Semiconductor packaging structure
JP2012003721U JP3178122U (ja) 2012-01-03 2012-06-20 半導体実装品
KR2020120006872U KR20130004317U (ko) 2012-01-03 2012-07-31 반도체 패키지 구조

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