TWI456674B - 半導體封裝方法及其結構 - Google Patents

半導體封裝方法及其結構 Download PDF

Info

Publication number
TWI456674B
TWI456674B TW101100131A TW101100131A TWI456674B TW I456674 B TWI456674 B TW I456674B TW 101100131 A TW101100131 A TW 101100131A TW 101100131 A TW101100131 A TW 101100131A TW I456674 B TWI456674 B TW I456674B
Authority
TW
Taiwan
Prior art keywords
conductive
free
copper
bonding surfaces
contact regions
Prior art date
Application number
TW101100131A
Other languages
English (en)
Other versions
TW201330126A (zh
Inventor
Cheng Hung Shih
Shu Chen Lin
Cheng Fan Lin
Yung Wei Hsieh
Bo Shiun Jiang
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Priority to TW101100131A priority Critical patent/TWI456674B/zh
Priority to JP2012138164A priority patent/JP2013140937A/ja
Priority to KR1020120083789A priority patent/KR101395175B1/ko
Priority to SG2012069589A priority patent/SG191464A1/en
Publication of TW201330126A publication Critical patent/TW201330126A/zh
Application granted granted Critical
Publication of TWI456674B publication Critical patent/TWI456674B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Claims (14)

  1. 一種半導體封裝方法，其至少包含： 　提供一基板，該基板係具有一上表面及複數個設置於該上表面之接點，各該接點係具有一第一接合表面，且該第一接合表面係具有複數個第一導電顆粒接觸區及複數個第一非導電顆粒接觸區； 　形成一可導電之防游離膠體於該基板之該上表面及該些接點上，該可導電之防游離膠體係混合有複數個導電顆粒及複數個防游離材；以及 　覆晶結合一晶片於該基板，該晶片係具有一主動面及複數個設置於該主動面之含銅凸塊，該主動面係朝向該基板之該上表面，該可導電之防游離膠體係包覆該些含銅凸塊，各該含銅凸塊係具有一第二接合表面及一環壁，該第二接合表面係具有複數個第二導電顆粒接觸區及複數個第二非導電顆粒接觸區，該些含銅凸塊係藉由該些導電顆粒電性連接於該些接點，該些導電顆粒係位於該些第一接合表面及該些第二接合表面之間，且該些導電顆粒係電性連接該些第一接合表面之該些第一導電顆粒接觸區及該些第二接合表面之該些第二導電顆粒接觸區，該些防游離材係位於相鄰導電顆粒之間，且該些防游離材係位於各該第一接合表面及各該第二接合表面之間，該些防游離材係結合於該些第二接合表面之該些第二非導電顆粒接觸區，且該些防游離材更包覆該些含銅凸塊之該些環壁。
  2. 如申請專利範圍第1項所述之半導體封裝方法，其中該些防游離材係結合於該些第一接合表面之該些第一非導電顆粒接觸區。
  3. 如申請專利範圍第1項所述之半導體封裝方法，其中各該接點係具有一側壁，該些防游離材係包覆該些側壁。
  4. 如申請專利範圍第1項所述之半導體封裝方法，其中該些防游離材之材質係為有機保焊劑。
  5. 如申請專利範圍第4項所述之半導體封裝方法，其中該有機保焊劑之材質係選自於咪唑化合物或咪唑衍生物其中之一。
  6. 如申請專利範圍第5項所述之半導體封裝方法，其中該咪唑衍生物係可為苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑或其混合體其中之一，該咪唑化合物可為苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑或其混合體其中之一。
  7. 如申請專利範圍第1項所述之半導體封裝方法，其中該些含銅凸塊之材質係選自於銅/鎳或銅/鎳/金其中之一。
  8. 一種半導體封裝結構，其至少包含： 　一基板，其係具有一上表面及複數個設置於該上表面之接點，各該接點係具有一第一接合表面，且該第一接合表面係具有複數個第一導電顆粒接觸區及複數個第一非導電顆粒接觸區； 　一可導電之防游離膠體，其係形成於該基板之該上表面及該些接點上，該可導電之防游離膠體係混合有複數個導電顆粒及複數個防游離材；以及 　一晶片，其係覆晶結合於該基板，該晶片係具有一主動面及複數個設置於該主動面之含銅凸塊，該主動面係朝向該基板之該上表面，該可導電之防游離膠體係包覆該些含銅凸塊，各該含銅凸塊係具有一第二接合表面及一環壁，該第二接合表面係具有複數個第二導電顆粒接觸區及複數個第二非導電顆粒接觸區，該些含銅凸塊係藉由該些導電顆粒電性連接於該些接點，該些導電顆粒係位於該些第一接合表面及該些第二接合表面之間，且該些導電顆粒係電性連接該些第一接合表面之該些第一導電顆粒接觸區及該些第二接合表面之該些第二導電顆粒接觸區，該些防游離材係位於相鄰導電顆粒之間，且該些防游離材係位於各該第一接合表面及各該第二接合表面之間，該些防游離材係結合於該些第二接合表面之該些第二非導電顆粒接觸區，且該些防游離材更包覆該些含銅凸塊之該些環壁。
  9. 如申請專利範圍第8項所述之半導體封裝結構，其中該些防游離材係結合於該些第一接合表面之該些第一非導電顆粒接觸區。
  10. 如申請專利範圍第8項所述之半導體封裝結構，其中各該接點係具有一側壁，該些防游離材係包覆該些側壁。
  11. 如申請專利範圍第8項所述之半導體封裝結構，其中該些防游離材之材質係為有機保焊劑。
  12. 如申請專利範圍第11項所述之半導體封裝結構，其中該有機保焊劑之材質係選自於咪唑化合物或咪唑衍生物其中之一。
  13. 如申請專利範圍第12項所述之半導體封裝結構，其中該咪唑衍生物係可為苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑或其混合體其中之一，該咪唑化合物可為苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑或其混合體其中之一。
  14. 如申請專利範圍第8項所述之半導體封裝結構，其中該些含銅凸塊之材質係選自於銅/鎳或銅/鎳/金其中之一。
TW101100131A 2012-01-03 2012-01-03 半導體封裝方法及其結構 TWI456674B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW101100131A TWI456674B (zh) 2012-01-03 2012-01-03 半導體封裝方法及其結構
JP2012138164A JP2013140937A (ja) 2012-01-03 2012-06-19 半導体実装方法および半導体実装品
KR1020120083789A KR101395175B1 (ko) 2012-01-03 2012-07-31 반도체 패키징 방법 및 반도체 패키지 구조
SG2012069589A SG191464A1 (en) 2012-01-03 2012-09-19 Semiconductor packaging method and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101100131A TWI456674B (zh) 2012-01-03 2012-01-03 半導體封裝方法及其結構

Publications (2)

Publication Number Publication Date
TW201330126A TW201330126A (zh) 2013-07-16
TWI456674B true TWI456674B (zh) 2014-10-11

Family

ID=48992265

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101100131A TWI456674B (zh) 2012-01-03 2012-01-03 半導體封裝方法及其結構

Country Status (4)

Country Link
JP (1) JP2013140937A (zh)
KR (1) KR101395175B1 (zh)
SG (1) SG191464A1 (zh)
TW (1) TWI456674B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW452950B (en) * 2000-09-19 2001-09-01 Siliconware Precision Industries Co Ltd Packaging structure of bonding pad with increased space height
TW200725828A (en) * 2005-12-30 2007-07-01 Int Semiconductor Tech Ltd Flip-chip bonding method utilizing non-conductive paste and its product
TW201140777A (en) * 2010-05-04 2011-11-16 Raydium Semiconductor Corp IC chip and an IC chip manufacturing method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3633422B2 (ja) * 2000-02-22 2005-03-30 ソニーケミカル株式会社 接続材料
JP4993880B2 (ja) * 2005-07-06 2012-08-08 旭化成イーマテリアルズ株式会社 異方導電性接着シート及び微細接続構造体
JP5622137B2 (ja) * 2007-10-29 2014-11-12 デクセリアルズ株式会社 電気的接続体及びその製造方法
JP5296116B2 (ja) * 2011-02-16 2013-09-25 シャープ株式会社 半導体装置
JP2012212864A (ja) * 2011-03-18 2012-11-01 Sekisui Chem Co Ltd 接続構造体の製造方法及び接続構造体
TWM428493U (en) * 2012-01-03 2012-05-01 Chipbond Technology Corp Semiconductor packaging structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW452950B (en) * 2000-09-19 2001-09-01 Siliconware Precision Industries Co Ltd Packaging structure of bonding pad with increased space height
TW200725828A (en) * 2005-12-30 2007-07-01 Int Semiconductor Tech Ltd Flip-chip bonding method utilizing non-conductive paste and its product
TW201140777A (en) * 2010-05-04 2011-11-16 Raydium Semiconductor Corp IC chip and an IC chip manufacturing method thereof

Also Published As

Publication number Publication date
KR20130079979A (ko) 2013-07-11
SG191464A1 (en) 2013-07-31
KR101395175B1 (ko) 2014-05-15
TW201330126A (zh) 2013-07-16
JP2013140937A (ja) 2013-07-18

Similar Documents

Publication Publication Date Title
CN102157391B (zh) 半导体器件和形成垂直互连的薄外形wlcsp的方法
US8018034B2 (en) Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
TWI611533B (zh) 半導體封裝件及其製法
US9607963B2 (en) Semiconductor device and fabrication method thereof
TWI594390B (zh) 半導體封裝件及其製法
TWI520285B (zh) 半導體封裝件及其製法
JP2009170802A (ja) 半導体装置
TW201812932A (zh) 電子封裝件及其製法
TWI589059B (zh) 電子封裝件
TW201719829A (zh) 電子封裝件及其製法
TW201807796A (zh) 電子封裝結構及其製法
TWI556402B (zh) 封裝堆疊結構及其製法
US8497579B1 (en) Semiconductor packaging method and structure thereof
TW201247093A (en) Semiconductor packaging method to form double side electromagnetic shielding layers and device fabricated from the same
TWI556383B (zh) 封裝結構及其製法
US9640503B2 (en) Package substrate, semiconductor package and method of manufacturing the same
TW201446089A (zh) 半導體封裝件及其製法
TWI456674B (zh) 半導體封裝方法及其結構
TWI604593B (zh) 半導體封裝件及其製法
JP3178122U (ja) 半導体実装品
US20140027930A1 (en) Semiconductor device including semiconductor package
TWI463585B (zh) 半導體封裝方法及其結構
TWI491014B (zh) 半導體堆疊單元與半導體封裝件之製法
TW201822331A (zh) 電子封裝件
TWM428492U (en) Semiconductor packaging structure